Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/1.0/patches/2175185/?format=api
{ "id": 2175185, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2175185/?format=api", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.0/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20251217143150.94463-14-philmd@linaro.org>", "date": "2025-12-17T14:31:49", "name": "[13/14] system/memory: Pass device_endian argument as MemOp bit", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "fd66a8d24adafe9dd014356242eb3b90b1ea31ea", "submitter": { "id": 85046, "url": "http://patchwork.ozlabs.org/api/1.0/people/85046/?format=api", "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20251217143150.94463-14-philmd@linaro.org/mbox/", "series": [ { "id": 485701, "url": "http://patchwork.ozlabs.org/api/1.0/series/485701/?format=api", "date": "2025-12-17T14:31:37", "name": "system/memory: Clean ups around address_space_ldst() endian variants", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/485701/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2175185/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=GH2MbCMP;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4dWbtX5Khyz1xty\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 18 Dec 2025 01:35:16 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1vVsax-0002Pd-6O; Wed, 17 Dec 2025 09:33:39 -0500", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <philmd@linaro.org>) id 1vVsav-0002Lj-PF\n for qemu-devel@nongnu.org; Wed, 17 Dec 2025 09:33:37 -0500", "from mail-wm1-x344.google.com ([2a00:1450:4864:20::344])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <philmd@linaro.org>) id 1vVsat-0007RF-PR\n for qemu-devel@nongnu.org; Wed, 17 Dec 2025 09:33:37 -0500", "by mail-wm1-x344.google.com with SMTP id\n 5b1f17b1804b1-477aa218f20so39438215e9.0\n for <qemu-devel@nongnu.org>; Wed, 17 Dec 2025 06:33:35 -0800 (PST)", "from localhost.localdomain (88-187-86-199.subs.proxad.net.\n [88.187.86.199]) by smtp.gmail.com with ESMTPSA id\n 5b1f17b1804b1-47bdc2221e3sm38847355e9.10.2025.12.17.06.33.31\n (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256);\n Wed, 17 Dec 2025 06:33:31 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=linaro.org; s=google; t=1765982013; x=1766586813; darn=nongnu.org;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:from:to:cc:subject:date\n :message-id:reply-to;\n bh=ruVgiLAX4pIcKIdX5Gb+1F0dTqHySf0+5Iyb0GQxoak=;\n b=GH2MbCMP0PC6IENO0Lm9oOlwyptLOlSxFevQ9Rch49qlTmRPy9O3+zMp2iTSRr1zO3\n y88lBzE6INSABm6yOOPTeQApvA4B6JNTQrCGTb+81Ehh5rO0ghy77jxf+pQxRTiCrTYu\n 49B5W20Klk/kEX13Gc3LbZLx2housSlmnmk+tPLw/Qgv/afeZvS3I0ufkx/xFzty5jRk\n 4P8ak9cQucTfKMchS3m87isIzrztcgCFruKrtOurb97hq0TlxinnjvTIm/ncbhSPJ2T7\n JjeGUdYMW/7hKzlZ4fmGEqXdyWAWV29nFJMaEmPK4U0+Hba2huRKM2ZzmJEkOFnbhDgU\n nzIw==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20230601; t=1765982013; x=1766586813;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from\n :to:cc:subject:date:message-id:reply-to;\n bh=ruVgiLAX4pIcKIdX5Gb+1F0dTqHySf0+5Iyb0GQxoak=;\n b=uhlnyPDSLuM/4+YrCUYJ3vHCPaAx+0hbFRGWxvo4NDdRyvbKPzHTtxiDhr7r+kJ5ud\n 7raSjDJF5dwizH2ZPivlcYx+sAyoG3pJrou8qoDUwAwAmrobZdh8guk1fCxdLvdJyrRf\n UWyAS4ZMNlpH4GqFDjKKz8Kk55ewB2bSB5RuO3F6VdPctuBxai6DVj3WcWiXQo4noEJi\n 4PEa28y9LRU8RF3B61RuX6/W3lDL0eLYecQEq4V4NMhNcfs86xhz6pdxJ/A3qQ9Ni7ud\n gaQRjb4OenrJWcMNt+sljfnC39xWVr4DrqZLBjCAlmbHfczATkxO9IH7Sk2yoktIrsdD\n ZXpA==", "X-Gm-Message-State": "AOJu0YyAJuLITT1cA7WVoDmH+CZuBf0SvXe5m6Fb+jVLTgPJYkP7BLDn\n ovFAEGXFHU7i+igbzDQy4znXn9hZ7kF4Ups22Uh5rMq5vnANT906fmuRFpYSQ6EmXZE6Qtk+tP8\n zmAx5+SEMXP/a", "X-Gm-Gg": "AY/fxX4YB03RWF76hsXCJpVLcYCKTknOYeVH3PlyUaAfMCTinDxvOxQ8qwDyfZz3ruE\n behm/+aMIlKqLZLqHRv+nN46NE/1wATWYADAdTjtVhXVskLe6h5oHuTv5IbTYR2LEgJAnIr/DQW\n uyaDUKzgDkoNo2Ukh7ZHfpPIsfPBAGGEcaKmgDKoIUxqNGdnxvADYLpxuZw2nTW8o7aiPFLbm+L\n jCNw/GtNeD7UXsyHyIvHh71+6+Ow/sM2070GnRu/kKMIeTWogVviGGs19uKZ02+jc8iZ1KUhj/4\n M9lTly1Ra0KhEXsH0RaT7DbZyEetjvKSpX6HjPt29D69z0KLxcZAjHujSYA9OIcj17jE2OxX2KJ\n Lwln1m0N1gl3199FjFWHHWCcM4U0W0Kdo2JAoEmDt7EJlJaO2V/6m5outHcUOYr248ADqIkND7L\n aYzOUnXYtT0Kt7uxdcpAPlDNvG9OAg4f0cg+TtoLFgb3w7tlp6LuEf3GYe19EO", "X-Google-Smtp-Source": "\n AGHT+IFbwGs5GMaGym0pvXkgDiFIXfgS0x9fXYvOKPoEBdrV9yaQyQYlbKisrdSkEYf1RQdx6Pp9Ug==", "X-Received": "by 2002:a05:600c:4711:b0:475:da1a:53f9 with SMTP id\n 5b1f17b1804b1-47a8f8c13a4mr158132765e9.14.1765982012772;\n Wed, 17 Dec 2025 06:33:32 -0800 (PST)", "From": "=?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <philmd@linaro.org>", "To": "qemu-devel@nongnu.org", "Cc": "=?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <philmd@linaro.org>,\n Anton Johansson <anjo@rev.ng>, qemu-arm@nongnu.org,\n Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>,\n Paolo Bonzini <pbonzini@redhat.com>, \"Michael S. Tsirkin\" <mst@redhat.com>,\n Artyom Tarasenko <atar4qemu@gmail.com>,\n Peter Maydell <peter.maydell@linaro.org>,\n David Hildenbrand <david@kernel.org>, Peter Xu <peterx@redhat.com>", "Subject": "[PATCH 13/14] system/memory: Pass device_endian argument as MemOp bit", "Date": "Wed, 17 Dec 2025 15:31:49 +0100", "Message-ID": "<20251217143150.94463-14-philmd@linaro.org>", "X-Mailer": "git-send-email 2.52.0", "In-Reply-To": "<20251217143150.94463-1-philmd@linaro.org>", "References": "<20251217143150.94463-1-philmd@linaro.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::344;\n envelope-from=philmd@linaro.org; helo=mail-wm1-x344.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Use the MemOp argument to hold both the access size and\nits endianness.\n\nSigned-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>\n---\n system/memory_ldst.c.inc | 86 ++++++++++++---------------------\n system/memory_ldst_endian.c.inc | 20 +++-----\n 2 files changed, 38 insertions(+), 68 deletions(-)", "diff": "diff --git a/system/memory_ldst.c.inc b/system/memory_ldst.c.inc\nindex e0c0c3f5dca..6387bb9d332 100644\n--- a/system/memory_ldst.c.inc\n+++ b/system/memory_ldst.c.inc\n@@ -24,8 +24,7 @@ static inline\n uint64_t glue(address_space_ldm_internal, SUFFIX)(ARG1_DECL, MemOp mop,\n hwaddr addr,\n MemTxAttrs attrs,\n- MemTxResult *result,\n- enum device_endian endian)\n+ MemTxResult *result)\n {\n const unsigned size = memop_size(mop);\n uint8_t *ptr;\n@@ -42,22 +41,15 @@ uint64_t glue(address_space_ldm_internal, SUFFIX)(ARG1_DECL, MemOp mop,\n release_lock |= prepare_mmio_access(mr);\n \n /* I/O case */\n- r = memory_region_dispatch_read(mr, addr1, &val,\n- mop | devend_memop(endian), attrs);\n+ r = memory_region_dispatch_read(mr, addr1, &val, mop, attrs);\n } else {\n /* RAM case */\n fuzz_dma_read_cb(addr, size, mr);\n ptr = qemu_map_ram_ptr(mr->ram_block, addr1);\n- switch (endian) {\n- case DEVICE_LITTLE_ENDIAN:\n+ if ((mop & MO_BSWAP) == MO_LE) {\n val = ldn_le_p(ptr, size);\n- break;\n- case DEVICE_BIG_ENDIAN:\n+ } else {\n val = ldn_be_p(ptr, size);\n- break;\n- default:\n- val = ldn_p(ptr, size);\n- break;\n }\n r = MEMTX_OK;\n }\n@@ -73,45 +65,40 @@ uint64_t glue(address_space_ldm_internal, SUFFIX)(ARG1_DECL, MemOp mop,\n \n /* warning: addr must be aligned */\n static inline uint32_t glue(address_space_ldl_internal, SUFFIX)(ARG1_DECL,\n- hwaddr addr, MemTxAttrs attrs, MemTxResult *result,\n- enum device_endian endian)\n+ MemOp mop, hwaddr addr, MemTxAttrs attrs, MemTxResult *result)\n {\n- return glue(address_space_ldm_internal, SUFFIX)(ARG1, MO_32, addr,\n- attrs, result, endian);\n+ return glue(address_space_ldm_internal, SUFFIX)(ARG1, mop | MO_32, addr,\n+ attrs, result);\n }\n \n /* warning: addr must be aligned */\n static inline uint64_t glue(address_space_ldq_internal, SUFFIX)(ARG1_DECL,\n- hwaddr addr, MemTxAttrs attrs, MemTxResult *result,\n- enum device_endian endian)\n+ MemOp mop, hwaddr addr, MemTxAttrs attrs, MemTxResult *result)\n {\n- return glue(address_space_ldm_internal, SUFFIX)(ARG1, MO_64, addr,\n- attrs, result, endian);\n+ return glue(address_space_ldm_internal, SUFFIX)(ARG1, mop | MO_64, addr,\n+ attrs, result);\n }\n \n uint8_t glue(address_space_ldub, SUFFIX)(ARG1_DECL,\n hwaddr addr, MemTxAttrs attrs, MemTxResult *result)\n {\n return glue(address_space_ldm_internal, SUFFIX)(ARG1, MO_8, addr,\n- attrs, result,\n- DEVICE_NATIVE_ENDIAN);\n+ attrs, result);\n }\n \n /* warning: addr must be aligned */\n static inline uint16_t glue(address_space_lduw_internal, SUFFIX)(ARG1_DECL,\n- hwaddr addr, MemTxAttrs attrs, MemTxResult *result,\n- enum device_endian endian)\n+ MemOp mop, hwaddr addr, MemTxAttrs attrs, MemTxResult *result)\n {\n- return glue(address_space_ldm_internal, SUFFIX)(ARG1, MO_16, addr,\n- attrs, result, endian);\n+ return glue(address_space_ldm_internal, SUFFIX)(ARG1, mop | MO_16, addr,\n+ attrs, result);\n }\n \n static inline\n void glue(address_space_stm_internal, SUFFIX)(ARG1_DECL, MemOp mop,\n hwaddr addr, uint64_t val,\n MemTxAttrs attrs,\n- MemTxResult *result,\n- enum device_endian endian)\n+ MemTxResult *result)\n {\n const unsigned size = memop_size(mop);\n uint8_t *ptr;\n@@ -125,21 +112,14 @@ void glue(address_space_stm_internal, SUFFIX)(ARG1_DECL, MemOp mop,\n mr = TRANSLATE(addr, &addr1, &l, true, attrs);\n if (l < size || !memory_access_is_direct(mr, true, attrs)) {\n release_lock |= prepare_mmio_access(mr);\n- r = memory_region_dispatch_write(mr, addr1, val,\n- mop | devend_memop(endian), attrs);\n+ r = memory_region_dispatch_write(mr, addr1, val, mop, attrs);\n } else {\n /* RAM case */\n ptr = qemu_map_ram_ptr(mr->ram_block, addr1);\n- switch (endian) {\n- case DEVICE_LITTLE_ENDIAN:\n+ if ((mop & MO_BSWAP) == MO_LE) {\n stn_le_p(ptr, size, val);\n- break;\n- case DEVICE_BIG_ENDIAN:\n+ } else {\n stn_be_p(ptr, size, val);\n- break;\n- default:\n- stn_p(ptr, size, val);\n- break;\n }\n invalidate_and_set_dirty(mr, addr1, size);\n r = MEMTX_OK;\n@@ -155,48 +135,44 @@ void glue(address_space_stm_internal, SUFFIX)(ARG1_DECL, MemOp mop,\n \n /* warning: addr must be aligned */\n static inline void glue(address_space_stl_internal, SUFFIX)(ARG1_DECL,\n- hwaddr addr, uint32_t val, MemTxAttrs attrs,\n- MemTxResult *result, enum device_endian endian)\n+ MemOp mop, hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result)\n {\n- glue(address_space_stm_internal, SUFFIX)(ARG1, MO_32, addr, val,\n- attrs, result, endian);\n+ glue(address_space_stm_internal, SUFFIX)(ARG1, mop | MO_32, addr, val,\n+ attrs, result);\n }\n \n void glue(address_space_stb, SUFFIX)(ARG1_DECL,\n hwaddr addr, uint8_t val, MemTxAttrs attrs, MemTxResult *result)\n {\n glue(address_space_stm_internal, SUFFIX)(ARG1, MO_8, addr, val,\n- attrs, result,\n- DEVICE_NATIVE_ENDIAN);\n+ attrs, result);\n }\n \n /* warning: addr must be aligned */\n static inline void glue(address_space_stw_internal, SUFFIX)(ARG1_DECL,\n- hwaddr addr, uint16_t val, MemTxAttrs attrs,\n- MemTxResult *result, enum device_endian endian)\n+ MemOp mop, hwaddr addr, uint16_t val, MemTxAttrs attrs, MemTxResult *result)\n {\n- glue(address_space_stm_internal, SUFFIX)(ARG1, MO_16, addr, val,\n- attrs, result, endian);\n+ glue(address_space_stm_internal, SUFFIX)(ARG1, mop | MO_16, addr, val,\n+ attrs, result);\n }\n \n static inline void glue(address_space_stq_internal, SUFFIX)(ARG1_DECL,\n- hwaddr addr, uint64_t val, MemTxAttrs attrs,\n- MemTxResult *result, enum device_endian endian)\n+ MemOp mop, hwaddr addr, uint64_t val, MemTxAttrs attrs, MemTxResult *result)\n {\n- glue(address_space_stm_internal, SUFFIX)(ARG1, MO_64, addr, val,\n- attrs, result, endian);\n+ glue(address_space_stm_internal, SUFFIX)(ARG1, mop | MO_64, addr, val,\n+ attrs, result);\n }\n \n #define ENDIANNESS\n-#define DEVICE_ENDIANNESS DEVICE_NATIVE_ENDIAN\n+#define MO_ENDIAN (target_big_endian() ? MO_BE : MO_LE)\n #include \"memory_ldst_endian.c.inc\"\n \n #define ENDIANNESS _le\n-#define DEVICE_ENDIANNESS DEVICE_LITTLE_ENDIAN\n+#define MO_ENDIAN MO_LE\n #include \"memory_ldst_endian.c.inc\"\n \n #define ENDIANNESS _be\n-#define DEVICE_ENDIANNESS DEVICE_BIG_ENDIAN\n+#define MO_ENDIAN MO_BE\n #include \"memory_ldst_endian.c.inc\"\n \n #undef ARG1_DECL\ndiff --git a/system/memory_ldst_endian.c.inc b/system/memory_ldst_endian.c.inc\nindex 16d686b50f7..8a4b4a3d220 100644\n--- a/system/memory_ldst_endian.c.inc\n+++ b/system/memory_ldst_endian.c.inc\n@@ -22,43 +22,37 @@\n uint16_t ADDRESS_SPACE_LD(uw)(ARG1_DECL, hwaddr addr,\n MemTxAttrs attrs, MemTxResult *result)\n {\n- return ADDRESS_SPACE_LD_INTERNAL(uw)(ARG1, addr, attrs, result,\n- DEVICE_ENDIANNESS);\n+ return ADDRESS_SPACE_LD_INTERNAL(uw)(ARG1, MO_ENDIAN, addr, attrs, result);\n }\n \n uint32_t ADDRESS_SPACE_LD(l)(ARG1_DECL, hwaddr addr,\n MemTxAttrs attrs, MemTxResult *result)\n {\n- return ADDRESS_SPACE_LD_INTERNAL(l)(ARG1, addr, attrs, result,\n- DEVICE_ENDIANNESS);\n+ return ADDRESS_SPACE_LD_INTERNAL(l)(ARG1, MO_ENDIAN, addr, attrs, result);\n }\n \n uint64_t ADDRESS_SPACE_LD(q)(ARG1_DECL, hwaddr addr,\n MemTxAttrs attrs, MemTxResult *result)\n {\n- return ADDRESS_SPACE_LD_INTERNAL(q)(ARG1, addr, attrs, result,\n- DEVICE_ENDIANNESS);\n+ return ADDRESS_SPACE_LD_INTERNAL(q)(ARG1, MO_ENDIAN, addr, attrs, result);\n }\n \n void ADDRESS_SPACE_ST(w)(ARG1_DECL, hwaddr addr, uint16_t val,\n MemTxAttrs attrs, MemTxResult *result)\n {\n- ADDRESS_SPACE_ST_INTERNAL(w)(ARG1, addr, val, attrs, result,\n- DEVICE_ENDIANNESS);\n+ ADDRESS_SPACE_ST_INTERNAL(w)(ARG1, MO_ENDIAN, addr, val, attrs, result);\n }\n \n void ADDRESS_SPACE_ST(l)(ARG1_DECL, hwaddr addr, uint32_t val,\n MemTxAttrs attrs, MemTxResult *result)\n {\n- ADDRESS_SPACE_ST_INTERNAL(l)(ARG1, addr, val, attrs, result,\n- DEVICE_ENDIANNESS);\n+ ADDRESS_SPACE_ST_INTERNAL(l)(ARG1, MO_ENDIAN, addr, val, attrs, result);\n }\n \n void ADDRESS_SPACE_ST(q)(ARG1_DECL, hwaddr addr, uint64_t val,\n MemTxAttrs attrs, MemTxResult *result)\n {\n- ADDRESS_SPACE_ST_INTERNAL(q)(ARG1, addr, val, attrs, result,\n- DEVICE_ENDIANNESS);\n+ ADDRESS_SPACE_ST_INTERNAL(q)(ARG1, MO_ENDIAN, addr, val, attrs, result);\n }\n \n #undef ADDRESS_SPACE_LD\n@@ -67,4 +61,4 @@ void ADDRESS_SPACE_ST(q)(ARG1_DECL, hwaddr addr, uint64_t val,\n #undef ADDRESS_SPACE_ST_INTERNAL\n \n #undef ENDIANNESS\n-#undef DEVICE_ENDIANNESS\n+#undef MO_ENDIAN\n", "prefixes": [ "13/14" ] }