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GET /api/1.0/patches/2175184/?format=api
{ "id": 2175184, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2175184/?format=api", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.0/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20251217143150.94463-13-philmd@linaro.org>", "date": "2025-12-17T14:31:48", "name": "[12/14] system/memory: Factor address_space_ldst[M]_internal() helper out", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "ff8061a7690e76de91c9221515a77d8cdcdb8e6b", "submitter": { "id": 85046, "url": "http://patchwork.ozlabs.org/api/1.0/people/85046/?format=api", "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20251217143150.94463-13-philmd@linaro.org/mbox/", "series": [ { "id": 485701, "url": "http://patchwork.ozlabs.org/api/1.0/series/485701/?format=api", "date": "2025-12-17T14:31:37", "name": "system/memory: Clean ups around address_space_ldst() endian variants", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/485701/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2175184/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=Sl3Y7HCf;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Tsirkin\" <mst@redhat.com>,\n Artyom Tarasenko <atar4qemu@gmail.com>,\n Peter Maydell <peter.maydell@linaro.org>,\n David Hildenbrand <david@kernel.org>, Peter Xu <peterx@redhat.com>", "Subject": "[PATCH 12/14] system/memory: Factor address_space_ldst[M]_internal()\n helper out", "Date": "Wed, 17 Dec 2025 15:31:48 +0100", "Message-ID": "<20251217143150.94463-13-philmd@linaro.org>", "X-Mailer": "git-send-email 2.52.0", "In-Reply-To": "<20251217143150.94463-1-philmd@linaro.org>", "References": "<20251217143150.94463-1-philmd@linaro.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::332;\n envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "All the LD/ST[W,L,Q] variants use the same template, only\nmodifying the access size used. Unify as a single pair of\nLD/ST methods taking a MemOp argument. Thus use the 'm'\nsuffix for MemOp.\n\nSigned-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>\n---\n system/memory_ldst.c.inc | 289 ++++++++-------------------------------\n 1 file changed, 58 insertions(+), 231 deletions(-)", "diff": "diff --git a/system/memory_ldst.c.inc b/system/memory_ldst.c.inc\nindex 823fc3a7561..e0c0c3f5dca 100644\n--- a/system/memory_ldst.c.inc\n+++ b/system/memory_ldst.c.inc\n@@ -20,39 +20,43 @@\n */\n \n /* warning: addr must be aligned */\n-static inline uint32_t glue(address_space_ldl_internal, SUFFIX)(ARG1_DECL,\n- hwaddr addr, MemTxAttrs attrs, MemTxResult *result,\n- enum device_endian endian)\n+static inline\n+uint64_t glue(address_space_ldm_internal, SUFFIX)(ARG1_DECL, MemOp mop,\n+ hwaddr addr,\n+ MemTxAttrs attrs,\n+ MemTxResult *result,\n+ enum device_endian endian)\n {\n+ const unsigned size = memop_size(mop);\n uint8_t *ptr;\n uint64_t val;\n MemoryRegion *mr;\n- hwaddr l = 4;\n+ hwaddr l = size;\n hwaddr addr1;\n MemTxResult r;\n bool release_lock = false;\n \n RCU_READ_LOCK();\n mr = TRANSLATE(addr, &addr1, &l, false, attrs);\n- if (l < 4 || !memory_access_is_direct(mr, false, attrs)) {\n+ if (l < size || !memory_access_is_direct(mr, false, attrs)) {\n release_lock |= prepare_mmio_access(mr);\n \n /* I/O case */\n r = memory_region_dispatch_read(mr, addr1, &val,\n- MO_32 | devend_memop(endian), attrs);\n+ mop | devend_memop(endian), attrs);\n } else {\n /* RAM case */\n- fuzz_dma_read_cb(addr, 4, mr);\n+ fuzz_dma_read_cb(addr, size, mr);\n ptr = qemu_map_ram_ptr(mr->ram_block, addr1);\n switch (endian) {\n case DEVICE_LITTLE_ENDIAN:\n- val = ldl_le_p(ptr);\n+ val = ldn_le_p(ptr, size);\n break;\n case DEVICE_BIG_ENDIAN:\n- val = ldl_be_p(ptr);\n+ val = ldn_be_p(ptr, size);\n break;\n default:\n- val = ldl_p(ptr);\n+ val = ldn_p(ptr, size);\n break;\n }\n r = MEMTX_OK;\n@@ -67,87 +71,30 @@ static inline uint32_t glue(address_space_ldl_internal, SUFFIX)(ARG1_DECL,\n return val;\n }\n \n+/* warning: addr must be aligned */\n+static inline uint32_t glue(address_space_ldl_internal, SUFFIX)(ARG1_DECL,\n+ hwaddr addr, MemTxAttrs attrs, MemTxResult *result,\n+ enum device_endian endian)\n+{\n+ return glue(address_space_ldm_internal, SUFFIX)(ARG1, MO_32, addr,\n+ attrs, result, endian);\n+}\n+\n /* warning: addr must be aligned */\n static inline uint64_t glue(address_space_ldq_internal, SUFFIX)(ARG1_DECL,\n hwaddr addr, MemTxAttrs attrs, MemTxResult *result,\n enum device_endian endian)\n {\n- uint8_t *ptr;\n- uint64_t val;\n- MemoryRegion *mr;\n- hwaddr l = 8;\n- hwaddr addr1;\n- MemTxResult r;\n- bool release_lock = false;\n-\n- RCU_READ_LOCK();\n- mr = TRANSLATE(addr, &addr1, &l, false, attrs);\n- if (l < 8 || !memory_access_is_direct(mr, false, attrs)) {\n- release_lock |= prepare_mmio_access(mr);\n-\n- /* I/O case */\n- r = memory_region_dispatch_read(mr, addr1, &val,\n- MO_64 | devend_memop(endian), attrs);\n- } else {\n- /* RAM case */\n- fuzz_dma_read_cb(addr, 8, mr);\n- ptr = qemu_map_ram_ptr(mr->ram_block, addr1);\n- switch (endian) {\n- case DEVICE_LITTLE_ENDIAN:\n- val = ldq_le_p(ptr);\n- break;\n- case DEVICE_BIG_ENDIAN:\n- val = ldq_be_p(ptr);\n- break;\n- default:\n- val = ldq_p(ptr);\n- break;\n- }\n- r = MEMTX_OK;\n- }\n- if (result) {\n- *result = r;\n- }\n- if (release_lock) {\n- bql_unlock();\n- }\n- RCU_READ_UNLOCK();\n- return val;\n+ return glue(address_space_ldm_internal, SUFFIX)(ARG1, MO_64, addr,\n+ attrs, result, endian);\n }\n \n uint8_t glue(address_space_ldub, SUFFIX)(ARG1_DECL,\n hwaddr addr, MemTxAttrs attrs, MemTxResult *result)\n {\n- uint8_t *ptr;\n- uint64_t val;\n- MemoryRegion *mr;\n- hwaddr l = 1;\n- hwaddr addr1;\n- MemTxResult r;\n- bool release_lock = false;\n-\n- RCU_READ_LOCK();\n- mr = TRANSLATE(addr, &addr1, &l, false, attrs);\n- if (!memory_access_is_direct(mr, false, attrs)) {\n- release_lock |= prepare_mmio_access(mr);\n-\n- /* I/O case */\n- r = memory_region_dispatch_read(mr, addr1, &val, MO_8, attrs);\n- } else {\n- /* RAM case */\n- fuzz_dma_read_cb(addr, 1, mr);\n- ptr = qemu_map_ram_ptr(mr->ram_block, addr1);\n- val = ldub_p(ptr);\n- r = MEMTX_OK;\n- }\n- if (result) {\n- *result = r;\n- }\n- if (release_lock) {\n- bql_unlock();\n- }\n- RCU_READ_UNLOCK();\n- return val;\n+ return glue(address_space_ldm_internal, SUFFIX)(ARG1, MO_8, addr,\n+ attrs, result,\n+ DEVICE_NATIVE_ENDIAN);\n }\n \n /* warning: addr must be aligned */\n@@ -155,37 +102,46 @@ static inline uint16_t glue(address_space_lduw_internal, SUFFIX)(ARG1_DECL,\n hwaddr addr, MemTxAttrs attrs, MemTxResult *result,\n enum device_endian endian)\n {\n+ return glue(address_space_ldm_internal, SUFFIX)(ARG1, MO_16, addr,\n+ attrs, result, endian);\n+}\n+\n+static inline\n+void glue(address_space_stm_internal, SUFFIX)(ARG1_DECL, MemOp mop,\n+ hwaddr addr, uint64_t val,\n+ MemTxAttrs attrs,\n+ MemTxResult *result,\n+ enum device_endian endian)\n+{\n+ const unsigned size = memop_size(mop);\n uint8_t *ptr;\n- uint64_t val;\n MemoryRegion *mr;\n- hwaddr l = 2;\n+ hwaddr l = size;\n hwaddr addr1;\n MemTxResult r;\n bool release_lock = false;\n \n RCU_READ_LOCK();\n- mr = TRANSLATE(addr, &addr1, &l, false, attrs);\n- if (l < 2 || !memory_access_is_direct(mr, false, attrs)) {\n+ mr = TRANSLATE(addr, &addr1, &l, true, attrs);\n+ if (l < size || !memory_access_is_direct(mr, true, attrs)) {\n release_lock |= prepare_mmio_access(mr);\n-\n- /* I/O case */\n- r = memory_region_dispatch_read(mr, addr1, &val,\n- MO_16 | devend_memop(endian), attrs);\n+ r = memory_region_dispatch_write(mr, addr1, val,\n+ mop | devend_memop(endian), attrs);\n } else {\n /* RAM case */\n- fuzz_dma_read_cb(addr, 2, mr);\n ptr = qemu_map_ram_ptr(mr->ram_block, addr1);\n switch (endian) {\n case DEVICE_LITTLE_ENDIAN:\n- val = lduw_le_p(ptr);\n+ stn_le_p(ptr, size, val);\n break;\n case DEVICE_BIG_ENDIAN:\n- val = lduw_be_p(ptr);\n+ stn_be_p(ptr, size, val);\n break;\n default:\n- val = lduw_p(ptr);\n+ stn_p(ptr, size, val);\n break;\n }\n+ invalidate_and_set_dirty(mr, addr1, size);\n r = MEMTX_OK;\n }\n if (result) {\n@@ -195,7 +151,6 @@ static inline uint16_t glue(address_space_lduw_internal, SUFFIX)(ARG1_DECL,\n bql_unlock();\n }\n RCU_READ_UNLOCK();\n- return val;\n }\n \n /* warning: addr must be aligned */\n@@ -203,74 +158,16 @@ static inline void glue(address_space_stl_internal, SUFFIX)(ARG1_DECL,\n hwaddr addr, uint32_t val, MemTxAttrs attrs,\n MemTxResult *result, enum device_endian endian)\n {\n- uint8_t *ptr;\n- MemoryRegion *mr;\n- hwaddr l = 4;\n- hwaddr addr1;\n- MemTxResult r;\n- bool release_lock = false;\n-\n- RCU_READ_LOCK();\n- mr = TRANSLATE(addr, &addr1, &l, true, attrs);\n- if (l < 4 || !memory_access_is_direct(mr, true, attrs)) {\n- release_lock |= prepare_mmio_access(mr);\n- r = memory_region_dispatch_write(mr, addr1, val,\n- MO_32 | devend_memop(endian), attrs);\n- } else {\n- /* RAM case */\n- ptr = qemu_map_ram_ptr(mr->ram_block, addr1);\n- switch (endian) {\n- case DEVICE_LITTLE_ENDIAN:\n- stl_le_p(ptr, val);\n- break;\n- case DEVICE_BIG_ENDIAN:\n- stl_be_p(ptr, val);\n- break;\n- default:\n- stl_p(ptr, val);\n- break;\n- }\n- invalidate_and_set_dirty(mr, addr1, 4);\n- r = MEMTX_OK;\n- }\n- if (result) {\n- *result = r;\n- }\n- if (release_lock) {\n- bql_unlock();\n- }\n- RCU_READ_UNLOCK();\n+ glue(address_space_stm_internal, SUFFIX)(ARG1, MO_32, addr, val,\n+ attrs, result, endian);\n }\n \n void glue(address_space_stb, SUFFIX)(ARG1_DECL,\n hwaddr addr, uint8_t val, MemTxAttrs attrs, MemTxResult *result)\n {\n- uint8_t *ptr;\n- MemoryRegion *mr;\n- hwaddr l = 1;\n- hwaddr addr1;\n- MemTxResult r;\n- bool release_lock = false;\n-\n- RCU_READ_LOCK();\n- mr = TRANSLATE(addr, &addr1, &l, true, attrs);\n- if (!memory_access_is_direct(mr, true, attrs)) {\n- release_lock |= prepare_mmio_access(mr);\n- r = memory_region_dispatch_write(mr, addr1, val, MO_8, attrs);\n- } else {\n- /* RAM case */\n- ptr = qemu_map_ram_ptr(mr->ram_block, addr1);\n- stb_p(ptr, val);\n- invalidate_and_set_dirty(mr, addr1, 1);\n- r = MEMTX_OK;\n- }\n- if (result) {\n- *result = r;\n- }\n- if (release_lock) {\n- bql_unlock();\n- }\n- RCU_READ_UNLOCK();\n+ glue(address_space_stm_internal, SUFFIX)(ARG1, MO_8, addr, val,\n+ attrs, result,\n+ DEVICE_NATIVE_ENDIAN);\n }\n \n /* warning: addr must be aligned */\n@@ -278,86 +175,16 @@ static inline void glue(address_space_stw_internal, SUFFIX)(ARG1_DECL,\n hwaddr addr, uint16_t val, MemTxAttrs attrs,\n MemTxResult *result, enum device_endian endian)\n {\n- uint8_t *ptr;\n- MemoryRegion *mr;\n- hwaddr l = 2;\n- hwaddr addr1;\n- MemTxResult r;\n- bool release_lock = false;\n-\n- RCU_READ_LOCK();\n- mr = TRANSLATE(addr, &addr1, &l, true, attrs);\n- if (l < 2 || !memory_access_is_direct(mr, true, attrs)) {\n- release_lock |= prepare_mmio_access(mr);\n- r = memory_region_dispatch_write(mr, addr1, val,\n- MO_16 | devend_memop(endian), attrs);\n- } else {\n- /* RAM case */\n- ptr = qemu_map_ram_ptr(mr->ram_block, addr1);\n- switch (endian) {\n- case DEVICE_LITTLE_ENDIAN:\n- stw_le_p(ptr, val);\n- break;\n- case DEVICE_BIG_ENDIAN:\n- stw_be_p(ptr, val);\n- break;\n- default:\n- stw_p(ptr, val);\n- break;\n- }\n- invalidate_and_set_dirty(mr, addr1, 2);\n- r = MEMTX_OK;\n- }\n- if (result) {\n- *result = r;\n- }\n- if (release_lock) {\n- bql_unlock();\n- }\n- RCU_READ_UNLOCK();\n+ glue(address_space_stm_internal, SUFFIX)(ARG1, MO_16, addr, val,\n+ attrs, result, endian);\n }\n \n static inline void glue(address_space_stq_internal, SUFFIX)(ARG1_DECL,\n hwaddr addr, uint64_t val, MemTxAttrs attrs,\n MemTxResult *result, enum device_endian endian)\n {\n- uint8_t *ptr;\n- MemoryRegion *mr;\n- hwaddr l = 8;\n- hwaddr addr1;\n- MemTxResult r;\n- bool release_lock = false;\n-\n- RCU_READ_LOCK();\n- mr = TRANSLATE(addr, &addr1, &l, true, attrs);\n- if (l < 8 || !memory_access_is_direct(mr, true, attrs)) {\n- release_lock |= prepare_mmio_access(mr);\n- r = memory_region_dispatch_write(mr, addr1, val,\n- MO_64 | devend_memop(endian), attrs);\n- } else {\n- /* RAM case */\n- ptr = qemu_map_ram_ptr(mr->ram_block, addr1);\n- switch (endian) {\n- case DEVICE_LITTLE_ENDIAN:\n- stq_le_p(ptr, val);\n- break;\n- case DEVICE_BIG_ENDIAN:\n- stq_be_p(ptr, val);\n- break;\n- default:\n- stq_p(ptr, val);\n- break;\n- }\n- invalidate_and_set_dirty(mr, addr1, 8);\n- r = MEMTX_OK;\n- }\n- if (result) {\n- *result = r;\n- }\n- if (release_lock) {\n- bql_unlock();\n- }\n- RCU_READ_UNLOCK();\n+ glue(address_space_stm_internal, SUFFIX)(ARG1, MO_64, addr, val,\n+ attrs, result, endian);\n }\n \n #define ENDIANNESS\n", "prefixes": [ "12/14" ] }