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GET /api/1.0/patches/2175152/?format=api
{ "id": 2175152, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2175152/?format=api", "project": { "id": 42, "url": "http://patchwork.ozlabs.org/api/1.0/projects/42/?format=api", "name": "Linux GPIO development", "link_name": "linux-gpio", "list_id": "linux-gpio.vger.kernel.org", "list_email": "linux-gpio@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20251217-eyeq6lplus-v1-6-e9cdbd3af4c2@bootlin.com>", "date": "2025-12-17T13:35:56", "name": "[06/13] pinctrl: eyeq5: Add Mobileye EyeQ6Lplus OLB", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "d1d22f3ecc7cdfdcf7e8d5034b3039820e558715", "submitter": { "id": 91083, "url": "http://patchwork.ozlabs.org/api/1.0/people/91083/?format=api", "name": "Benoît Monin", "email": "benoit.monin@bootlin.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20251217-eyeq6lplus-v1-6-e9cdbd3af4c2@bootlin.com/mbox/", "series": [ { "id": 485688, "url": "http://patchwork.ozlabs.org/api/1.0/series/485688/?format=api", "date": "2025-12-17T13:35:54", "name": "Introducing the Mobileye EyeQ6Lplus SoC", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/485688/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2175152/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-gpio+bounces-29701-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-gpio@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=bootlin.com header.i=@bootlin.com header.a=rsa-sha256\n header.s=dkim header.b=q02tmnOT;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.105.105.114; helo=tor.lore.kernel.org;\n envelope-from=linux-gpio+bounces-29701-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com\n header.b=\"q02tmnOT\"", "smtp.subspace.kernel.org;\n arc=none smtp.client-ip=185.171.202.116", "smtp.subspace.kernel.org;\n dmarc=pass (p=reject dis=none) header.from=bootlin.com", "smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=bootlin.com" ], "Received": [ "from tor.lore.kernel.org (tor.lore.kernel.org [172.105.105.114])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4dWZjw0yS6z1xpw\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 18 Dec 2025 00:42:44 +1100 (AEDT)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby tor.lore.kernel.org (Postfix) with ESMTP id C1F6F3048F54\n\tfor <incoming@patchwork.ozlabs.org>; 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a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1765978587; cv=none;\n b=cGHhFSrxes50LsW2MVffxHfTsf2pbNcPbYpEz0LTwz3qwtAzLbXzjITrP3LUa32UZ/b8xxEqcO4nTfsaCAviJKWvoltdV3KfnGWPDTpcEhMHKbHM8577NexUMCZXPFj3Ibx6MnABlWM4TcEgLXFfn/7dh/gr1cJaSNT4JLtfF1Q=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1765978587; c=relaxed/simple;\n\tbh=SoxJyWG+uDvGBd7nn/eX3mmV9272H7mtNAyvRhnavHE=;\n\th=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References:\n\t In-Reply-To:To:Cc;\n b=lW2x34gECHvNxLPiGMI03kYk2fJwBliu+hso5rmd4x0xYHLrRIVBInXzNahgW/V/VrpQejVsCPOM0+mhv94C+ZHyM8vOiTmq9x+AQR4PRUdVsCpxzWnAWiO8ir3nOt/UXAtFsflFWXjHpLo4VfUQsP09RsfRo5O3CJ3FfcDfDD8=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dmarc=pass (p=reject dis=none) header.from=bootlin.com;\n spf=pass smtp.mailfrom=bootlin.com;\n dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com\n header.b=q02tmnOT; arc=none smtp.client-ip=185.171.202.116", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim;\n\tt=1765978582; h=from:subject:date:message-id:to:cc:mime-version:content-type:\n\t content-transfer-encoding:in-reply-to:references;\n\tbh=s8K0G8h9AHd3sk2Ye5cfjJVPS3MdVGECmnKjmPBxoaE=;\n\tb=q02tmnOTv314ztcTNRO2K1wdl5Ak8Na8BErfJBSxRs9q7eTSzLrsi/KKMEj+/F0SFaDqZ/\n\tsmRyMK6Om6LEwjfglA9hPwxugWJZt3vRl0i/x6yvfgoU385ZRZiSM+TXx3BeA7A5cmFZbl\n\t4ZTIfZaJ2p5EltEO18DbQRc988HiYTT31179TnPyM5H2NyhJ16fsZmE5rXCxQZqPqxDyb/\n\t8FkdpmbEE5E/J/RVoNa1Rmgw3zJS2Gg/EAmNQNNt5wJ4SKShp8bKMPLXk6jRHbOLrS1dqy\n\tzvEQXuWCHriOYlcmAv9AI7stIhyM689YIgbkt/WqsoIFVqAMayquJ8h2Ibi7ng==", "From": "=?utf-8?q?Beno=C3=AEt_Monin?= <benoit.monin@bootlin.com>", "Date": "Wed, 17 Dec 2025 14:35:56 +0100", "Subject": "[PATCH 06/13] pinctrl: eyeq5: Add Mobileye EyeQ6Lplus OLB", "Precedence": "bulk", "X-Mailing-List": "linux-gpio@vger.kernel.org", "List-Id": "<linux-gpio.vger.kernel.org>", "List-Subscribe": "<mailto:linux-gpio+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-gpio+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "8bit", "Message-Id": "<20251217-eyeq6lplus-v1-6-e9cdbd3af4c2@bootlin.com>", "References": "<20251217-eyeq6lplus-v1-0-e9cdbd3af4c2@bootlin.com>", "In-Reply-To": "<20251217-eyeq6lplus-v1-0-e9cdbd3af4c2@bootlin.com>", "To": "Vladimir Kondratiev <vladimir.kondratiev@mobileye.com>,\n Gregory CLEMENT <gregory.clement@bootlin.com>,\n =?utf-8?q?Th=C3=A9o_Lebrun?= <theo.lebrun@bootlin.com>,\n Thomas Bogendoerfer <tsbogend@alpha.franken.de>,\n Rob Herring <robh@kernel.org>, Krzysztof Kozlowski <krzk+dt@kernel.org>,\n Conor Dooley <conor+dt@kernel.org>,\n Michael Turquette <mturquette@baylibre.com>,\n Stephen Boyd <sboyd@kernel.org>, Philipp Zabel <p.zabel@pengutronix.de>,\n Linus Walleij <linusw@kernel.org>", "Cc": "Thomas Petazzoni <thomas.petazzoni@bootlin.com>,\n Tawfik Bayouk <tawfik.bayouk@mobileye.com>, linux-mips@vger.kernel.org,\n devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, =?utf-8?q?Beno?=\n\t=?utf-8?q?=C3=AEt_Monin?= <benoit.monin@bootlin.com>", "X-Mailer": "b4 0.14.3", "X-Last-TLS-Session-Version": "TLSv1.3" }, "content": "Add the match data for the pinctrl found in the EyeQ6Lplus OLB. The pin\ncontrol is identical in function to the one present in the EyeQ5 but\nhas a single bank of 32 pins.\n\nSigned-off-by: Benoît Monin <benoit.monin@bootlin.com>\n---\n drivers/pinctrl/Kconfig | 4 +-\n drivers/pinctrl/pinctrl-eyeq5.c | 95 +++++++++++++++++++++++++++++++++++++++++\n 2 files changed, 97 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig\nindex bc7f37afc48b..c81568d835e6 100644\n--- a/drivers/pinctrl/Kconfig\n+++ b/drivers/pinctrl/Kconfig\n@@ -248,11 +248,11 @@ config PINCTRL_EQUILIBRIUM\n config PINCTRL_EYEQ5\n \tbool \"Mobileye EyeQ5 pinctrl driver\"\n \tdepends on OF\n-\tdepends on MACH_EYEQ5 || COMPILE_TEST\n+\tdepends on MACH_EYEQ5 || MACH_EYEQ6LPLUS || COMPILE_TEST\n \tselect PINMUX\n \tselect GENERIC_PINCONF\n \tselect AUXILIARY_BUS\n-\tdefault MACH_EYEQ5\n+\tdefault MACH_EYEQ5 || MACH_EYEQ6LPLUS\n \thelp\n \t Pin controller driver for the Mobileye EyeQ5 platform. It does both\n \t pin config & pin muxing. It does not handle GPIO.\ndiff --git a/drivers/pinctrl/pinctrl-eyeq5.c b/drivers/pinctrl/pinctrl-eyeq5.c\nindex e48add1d965d..729fdf7cbbc2 100644\n--- a/drivers/pinctrl/pinctrl-eyeq5.c\n+++ b/drivers/pinctrl/pinctrl-eyeq5.c\n@@ -229,6 +229,100 @@ static const struct eq5p_match_data eq5p_eyeq5_data = {\n \t.banks = eq5p_eyeq5_banks,\n };\n \n+static const struct pinctrl_pin_desc eq5p_eyeq6lplus_pins[] = {\n+\tPINCTRL_PIN(0, \"PA0\"), /* GPIO_A0_TIMER0_CK0 */\n+\tPINCTRL_PIN(1, \"PA1\"), /* GPIO_A1_TIMER0_EOC */\n+\tPINCTRL_PIN(2, \"PA2\"), /* GPIO_A2_TIMER1_CK */\n+\tPINCTRL_PIN(3, \"PA3\"), /* GPIO_A3_TIMER1_EOC1 */\n+\tPINCTRL_PIN(4, \"PA4\"), /* GPIO_A4_SSI_UART_RX */\n+\tPINCTRL_PIN(5, \"PA5\"), /* GPIO_A5_SSI_UART_TX */\n+\tPINCTRL_PIN(6, \"PA6\"), /* GPIO_A6_SPI_0_CS */\n+\tPINCTRL_PIN(7, \"PA7\"), /* GPIO_A7_SPI_0_DI */\n+\tPINCTRL_PIN(8, \"PA8\"), /* GPIO_A8_SPI_0_CK */\n+\tPINCTRL_PIN(9, \"PA9\"), /* GPIO_A9_SPI_0_DO */\n+\tPINCTRL_PIN(10, \"PA10\"), /* GPIO_A10_SPI_0_CS1 */\n+\tPINCTRL_PIN(11, \"PA11\"), /* GPIO_A11_UART_0_RX */\n+\tPINCTRL_PIN(12, \"PA12\"), /* GPIO_A12_UART_0_TX */\n+\tPINCTRL_PIN(13, \"PA13\"), /* GPIO_A13_TIMER2_CK */\n+\tPINCTRL_PIN(14, \"PA14\"), /* GPIO_A14_TIMER2_EOC */\n+\tPINCTRL_PIN(15, \"PA15\"), /* GPIO_A15_TIMER3_CK */\n+\tPINCTRL_PIN(16, \"PA16\"), /* GPIO_A16_TIMER_EOC */\n+\tPINCTRL_PIN(17, \"PA17\"), /* GPIO_A17_TIMER_EXT0_INCA P1 */\n+\tPINCTRL_PIN(18, \"PA18\"), /* GPIO_A18_TIMER_EXT0_INCA P2 */\n+\tPINCTRL_PIN(19, \"PA19\"), /* GPIO_A19_TIMER_EXT0_OUT CMP1 */\n+\tPINCTRL_PIN(20, \"PA20\"), /* GPIO_A20_TIMER_EXT0_OUT CMP2 */\n+\tPINCTRL_PIN(21, \"PA21\"), /* GPIO_A21_SPI_1_CS0 */\n+\tPINCTRL_PIN(22, \"PA22\"), /* GPIO_A22_SPI_1_DI */\n+\tPINCTRL_PIN(23, \"PA23\"), /* GPIO_A23_SPI_1_CK */\n+\tPINCTRL_PIN(24, \"PA24\"), /* GPIO_A24_SPI_1_DO */\n+\tPINCTRL_PIN(25, \"PA25\"), /* GPIO_A25_SPI_1_CS1 */\n+\tPINCTRL_PIN(26, \"PA26\"), /* GPIO_A26_TIMER_EXT1_INCA P1 */\n+\tPINCTRL_PIN(27, \"PA27\"), /* GPIO_A27_TIMER_EXT1_INCA P2 */\n+\tPINCTRL_PIN(28, \"PA28\"), /* GPIO_A28_TIMER_EXT1_OUTC MP1 */\n+\tPINCTRL_PIN(29, \"PA29\"), /* GPIO_A29_TIMER_EXT1_OUTC MP2 */\n+\tPINCTRL_PIN(30, \"PA30\"), /* GPIO_A30_EXT_CLK */\n+\tPINCTRL_PIN(31, \"PA31\"), /* GPIO_A31_VDI_MCLK */\n+};\n+\n+static const char * const eq5p_eyeq6lplus_gpio_groups[] = {\n+\t/* Bank A */\n+\t\"PA0\", \"PA1\", \"PA2\", \"PA3\", \"PA4\", \"PA5\", \"PA6\", \"PA7\",\n+\t\"PA8\", \"PA9\", \"PA10\", \"PA11\", \"PA12\", \"PA13\", \"PA14\", \"PA15\",\n+\t\"PA16\", \"PA17\", \"PA18\", \"PA19\", \"PA20\", \"PA21\", \"PA22\", \"PA23\",\n+\t\"PA24\", \"PA25\", \"PA26\", \"PA27\", \"PA28\", \"PA29\", \"PA30\", \"PA31\",\n+};\n+\n+/* Groups of functions on bank A */\n+static const char * const eq5p_eyeq6lplus_timer0_groups[] = { \"PA0\", \"PA1\" };\n+static const char * const eq5p_eyeq6lplus_timer1_groups[] = { \"PA2\", \"PA3\" };\n+static const char * const eq5p_eyeq6lplus_uart_ssi_groups[] = { \"PA4\", \"PA5\" };\n+static const char * const eq5p_eyeq6lplus_spi0_groups[] = { \"PA6\", \"PA7\", \"PA8\", \"PA9\", \"PA10\" };\n+static const char * const eq5p_eyeq6lplus_uart0_groups[] = { \"PA11\", \"PA12\" };\n+static const char * const eq5p_eyeq6lplus_timer2_groups[] = { \"PA13\", \"PA14\" };\n+static const char * const eq5p_eyeq6lplus_timer3_groups[] = { \"PA15\", \"PA16\" };\n+static const char * const eq5p_eyeq6lplus_timer_ext0_groups[] = { \"PA17\", \"PA18\", \"PA19\", \"PA20\" };\n+static const char * const eq5p_eyeq6lplus_spi1_groups[] = {\n+\t\"PA21\", \"PA22\", \"PA23\", \"PA24\", \"PA25\"\n+};\n+static const char * const eq5p_eyeq6lplus_timer_ext1_groups[] = { \"PA26\", \"PA27\", \"PA28\", \"PA29\" };\n+static const char * const eq5p_eyeq6lplus_ext_ref_clk_groups[] = { \"PA30\" };\n+static const char * const eq5p_eyeq6lplus_mipi_ref_clk_groups[] = { \"PA31\" };\n+\n+static const struct pinfunction eq5p_eyeq6lplus_functions[] = {\n+\t/* gpios function */\n+\tEQ5P_PINFUNCTION(\"gpio\", eq5p_eyeq6lplus_gpio_groups),\n+\n+\t/* Bank A alternate functions */\n+\tEQ5P_PINFUNCTION(\"timer0\", eq5p_eyeq6lplus_timer0_groups),\n+\tEQ5P_PINFUNCTION(\"timer1\", eq5p_eyeq6lplus_timer1_groups),\n+\tEQ5P_PINFUNCTION(\"uart_ssi\", eq5p_eyeq6lplus_uart_ssi_groups),\n+\tEQ5P_PINFUNCTION(\"spi0\", eq5p_eyeq6lplus_spi0_groups),\n+\tEQ5P_PINFUNCTION(\"uart0\", eq5p_eyeq6lplus_uart0_groups),\n+\tEQ5P_PINFUNCTION(\"timer2\", eq5p_eyeq6lplus_timer2_groups),\n+\tEQ5P_PINFUNCTION(\"timer3\", eq5p_eyeq6lplus_timer3_groups),\n+\tEQ5P_PINFUNCTION(\"timer_ext0\", eq5p_eyeq6lplus_timer_ext0_groups),\n+\tEQ5P_PINFUNCTION(\"spi1\", eq5p_eyeq6lplus_spi1_groups),\n+\tEQ5P_PINFUNCTION(\"timer_ext1\", eq5p_eyeq6lplus_timer_ext1_groups),\n+\tEQ5P_PINFUNCTION(\"ext_ref_clk\", eq5p_eyeq6lplus_ext_ref_clk_groups),\n+\tEQ5P_PINFUNCTION(\"mipi_ref_clk\", eq5p_eyeq6lplus_mipi_ref_clk_groups),\n+};\n+\n+static const struct eq5p_bank eq5p_eyeq6lplus_banks[] = {\n+\t{\n+\t\t.npins = ARRAY_SIZE(eq5p_eyeq6lplus_pins),\n+\t\t.regs = {0x0C0, 0x0C4, 0x0D0, 0x0D4, 0x0B0},\n+\t},\n+};\n+\n+static const struct eq5p_match_data eq5p_eyeq6lplus_data = {\n+\t.npins = ARRAY_SIZE(eq5p_eyeq6lplus_pins),\n+\t.nfunctions = ARRAY_SIZE(eq5p_eyeq6lplus_functions),\n+\t.nbanks = ARRAY_SIZE(eq5p_eyeq6lplus_banks),\n+\t.pins = eq5p_eyeq6lplus_pins,\n+\t.functions = eq5p_eyeq6lplus_functions,\n+\t.banks = eq5p_eyeq6lplus_banks,\n+};\n+\n static void eq5p_update_bits(const struct eq5p_pinctrl *pctrl,\n \t\t\t const struct eq5p_bank *bank,\n \t\t\t enum eq5p_regs reg, u32 mask, u32 val)\n@@ -666,6 +760,7 @@ static int eq5p_probe(struct auxiliary_device *adev,\n \n static const struct of_device_id eq5p_match_table[] = {\n \t{ .compatible = \"mobileye,eyeq5-olb\", .data = &eq5p_eyeq5_data },\n+\t{ .compatible = \"mobileye,eyeq6lplus-olb\", .data = &eq5p_eyeq6lplus_data },\n \t{}\n };\n MODULE_DEVICE_TABLE(of, eq5p_match_table);\n", "prefixes": [ "06/13" ] }