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GET /api/1.0/patches/2175149/?format=api
{ "id": 2175149, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2175149/?format=api", "project": { "id": 42, "url": "http://patchwork.ozlabs.org/api/1.0/projects/42/?format=api", "name": "Linux GPIO development", "link_name": "linux-gpio", "list_id": "linux-gpio.vger.kernel.org", "list_email": "linux-gpio@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20251217-eyeq6lplus-v1-10-e9cdbd3af4c2@bootlin.com>", "date": "2025-12-17T13:36:00", "name": "[10/13] MIPS: Add Mobileye EyeQ6Lplus SoC dtsi", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "3a6b973267c2d99f92dfe5a7feccded7fb9d7454", "submitter": { "id": 91083, "url": "http://patchwork.ozlabs.org/api/1.0/people/91083/?format=api", "name": "Benoît Monin", "email": "benoit.monin@bootlin.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20251217-eyeq6lplus-v1-10-e9cdbd3af4c2@bootlin.com/mbox/", "series": [ { "id": 485688, "url": "http://patchwork.ozlabs.org/api/1.0/series/485688/?format=api", "date": "2025-12-17T13:35:54", "name": "Introducing the Mobileye EyeQ6Lplus SoC", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/485688/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2175149/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-gpio+bounces-29705-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-gpio@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=bootlin.com header.i=@bootlin.com header.a=rsa-sha256\n header.s=dkim header.b=WQQZQaAS;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c15:e001:75::12fc:5321; helo=sin.lore.kernel.org;\n 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(Mailerdaemon)\n with ESMTPSA id 77244102F0AD4;\n\tWed, 17 Dec 2025 14:36:28 +0100 (CET)" ], "ARC-Seal": "i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1765978596; cv=none;\n b=VG+htn5g8qumbG7uVYLDxYsebG0HpO9+KVoxgQr6/e6aFbmBgm7cke3EkJw9bJYRg8Xi1yI1hv4ebcBU7SorCwz0tUUd77/1/9TNCpu39fi3GG27rsSSuyJoNRQCBwNuolqwhXO5IFd6woiD4N+s8zpBtGeLy5kTjf489HZu4AA=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1765978596; c=relaxed/simple;\n\tbh=jHCMrBULvwVzv5JpCqHP1Kn3GqfcRs7OGNudExX2Uo4=;\n\th=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References:\n\t In-Reply-To:To:Cc;\n b=UQUImJ5hjGEXc+v5gu6Q27eXKAAysP8Sh+0FFozImFtfKvjgnJuwkZh2PH5q+PtbAKdCRjbaG6sD61vbnfFv5xWdeKL7kb2xWv1r4ep7DfxtwAcpPwrnan1tPKlqZ+sK7Uxsq9IDmpIKH60RU8gBeUiavz0few+wjJdn717oCgs=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dmarc=pass (p=reject dis=none) header.from=bootlin.com;\n spf=pass smtp.mailfrom=bootlin.com;\n dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com\n header.b=WQQZQaAS; arc=none smtp.client-ip=185.246.84.56", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim;\n\tt=1765978590; h=from:subject:date:message-id:to:cc:mime-version:content-type:\n\t content-transfer-encoding:in-reply-to:references;\n\tbh=riB5KJaXNeA6IOitdQ8kr+NsrOyX+9YKQFa5ylL1kOc=;\n\tb=WQQZQaAS4RzC6T8XyEgU9+UZMsTpXeLQLaFNCaz478UWvZxqawsQSrvM8sekfhvRsmMb7q\n\tPZoG1qJaoy3eSl4hW7SeTn5vMOilGsGRIr9XsW572ST+BLJVQb0g2bsrFyYYoZLY1RvEEC\n\toy46bib+LQarC7OOjOrClvvYfy681fL1PIQ40IsPaCab1sY2QjmKVv50jlsepNFfRqnEVj\n\tV8TKYW/h122oonqMXQfiWyoh7I5buJtwrZhRrisVXCP9HzBQf84GC9I8cTbTCr4OwMqYGe\n\tvbXV1dnMemvXzhy/7FR6nedpYqnXsn1l4ExUQPpFQOBLRKgFdDQ6HORzG3hbwg==", "From": "=?utf-8?q?Beno=C3=AEt_Monin?= <benoit.monin@bootlin.com>", "Date": "Wed, 17 Dec 2025 14:36:00 +0100", "Subject": "[PATCH 10/13] MIPS: Add Mobileye EyeQ6Lplus SoC dtsi", "Precedence": "bulk", "X-Mailing-List": "linux-gpio@vger.kernel.org", "List-Id": "<linux-gpio.vger.kernel.org>", "List-Subscribe": "<mailto:linux-gpio+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-gpio+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "8bit", "Message-Id": "<20251217-eyeq6lplus-v1-10-e9cdbd3af4c2@bootlin.com>", "References": "<20251217-eyeq6lplus-v1-0-e9cdbd3af4c2@bootlin.com>", "In-Reply-To": "<20251217-eyeq6lplus-v1-0-e9cdbd3af4c2@bootlin.com>", "To": "Vladimir Kondratiev <vladimir.kondratiev@mobileye.com>,\n Gregory CLEMENT <gregory.clement@bootlin.com>,\n =?utf-8?q?Th=C3=A9o_Lebrun?= <theo.lebrun@bootlin.com>,\n Thomas Bogendoerfer <tsbogend@alpha.franken.de>,\n Rob Herring <robh@kernel.org>, Krzysztof Kozlowski <krzk+dt@kernel.org>,\n Conor Dooley <conor+dt@kernel.org>,\n Michael Turquette <mturquette@baylibre.com>,\n Stephen Boyd <sboyd@kernel.org>, Philipp Zabel <p.zabel@pengutronix.de>,\n Linus Walleij <linusw@kernel.org>", "Cc": "Thomas Petazzoni <thomas.petazzoni@bootlin.com>,\n Tawfik Bayouk <tawfik.bayouk@mobileye.com>, linux-mips@vger.kernel.org,\n devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, =?utf-8?q?Beno?=\n\t=?utf-8?q?=C3=AEt_Monin?= <benoit.monin@bootlin.com>", "X-Mailer": "b4 0.14.3", "X-Last-TLS-Session-Version": "TLSv1.3" }, "content": "Add the device tree include files for the EyeQ6Lplus system on chip\nfrom Mobileye.\n\nThose files provide the initial support of the SoC:\n* The I6500 CPU and GIC interrupt controller.\n* The OLB (\"Other Logic Block\") providing clocks, resets and pin controls.\n* One UART.\n* One GPIO controller.\n* Two SPI controllers, one in host mode and one in target mode.\n* One octoSPI flash controller.\n* Two I2C controllers.\n\nSigned-off-by: Benoît Monin <benoit.monin@bootlin.com>\n---\n arch/mips/boot/dts/mobileye/eyeq6lplus-pins.dtsi | 84 +++++++++++\n arch/mips/boot/dts/mobileye/eyeq6lplus.dtsi | 169 +++++++++++++++++++++++\n 2 files changed, 253 insertions(+)", "diff": "diff --git a/arch/mips/boot/dts/mobileye/eyeq6lplus-pins.dtsi b/arch/mips/boot/dts/mobileye/eyeq6lplus-pins.dtsi\nnew file mode 100644\nindex 000000000000..5cb0660f46c6\n--- /dev/null\n+++ b/arch/mips/boot/dts/mobileye/eyeq6lplus-pins.dtsi\n@@ -0,0 +1,84 @@\n+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)\n+\n+&olb {\n+\ttimer0_pins: timer0-pins {\n+\t\tfunction = \"timer0\";\n+\t\tpins = \"PA0\", \"PA1\";\n+\t};\n+\ttimer1_pins: timer1-pins {\n+\t\tfunction = \"timer1\";\n+\t\tpins = \"PA2\", \"PA3\";\n+\t};\n+\tuart_ssi_pins: uart-ssi-pins {\n+\t\tfunction = \"uart_ssi\";\n+\t\tpins = \"PA4\", \"PA5\";\n+\t};\n+\tspi0_pins: spi0-pins {\n+\t\tfunction = \"spi0\";\n+\t\tpins = \"PA6\", \"PA7\", \"PA8\", \"PA9\";\n+\t};\n+\tuart0_pins: uart0-pins {\n+\t\tfunction = \"uart0\";\n+\t\tpins = \"PA11\", \"PA12\";\n+\t};\n+\ttimer2_pins: timer2-pins {\n+\t\tfunction = \"timer2\";\n+\t\tpins = \"PA13\", \"PA14\";\n+\t};\n+\ttimer3_pins: timer3-pins {\n+\t\tfunction = \"timer3\";\n+\t\tpins = \"PA15\", \"PA16\";\n+\t};\n+\ttimer_ext0_pins: timer-ext0-pins {\n+\t\tfunction = \"timer_ext0\";\n+\t\tpins = \"PA17\", \"PA18\", \"PA19\", \"PA20\";\n+\t};\n+\ttimer_ext0_input_a_pins: timer-ext0-input-a-pins {\n+\t\tfunction = \"timer_ext0\";\n+\t\tpins = \"PA17\";\n+\t};\n+\tpps0_pins: pps0-pins {\n+\t\tfunction = \"timer_ext0\";\n+\t\tpins = \"PA17\";\n+\t};\n+\ttimer_ext0_input_b_pins: timer-ext0-input-b-pins {\n+\t\tfunction = \"timer_ext0\";\n+\t\tpins = \"PA18\";\n+\t};\n+\ttimer_ext0_output_pins: timer-ext0-output-pins {\n+\t\tfunction = \"timer_ext0\";\n+\t\tpins = \"PA19\", \"PA20\";\n+\t};\n+\tspi1_pins: spi1-pins {\n+\t\tfunction = \"spi1\";\n+\t\tpins = \"PA21\", \"PA22\", \"PA23\", \"PA24\";\n+\t};\n+\tspi1_reduced_pins: spi1-reduced-pins {\n+\t\tfunction = \"spi1\";\n+\t\tpins = \"PA21\", \"PA22\", \"PA23\";\n+\t};\n+\ttimer_ext1_pins: timer-ext1-pins {\n+\t\tfunction = \"timer_ext1\";\n+\t\tpins = \"PA26\", \"PA27\", \"PA28\", \"PA29\";\n+\t};\n+\ttimer_ext1_input_a_pins: timer-ext1-input-a-pins {\n+\t\tfunction = \"timer_ext1\";\n+\t\tpins = \"PA26\";\n+\t};\n+\ttimer_ext1_input_b_pins: timer-ext1-input-b-pins {\n+\t\tfunction = \"timer_ext1\";\n+\t\tpins = \"PA27\";\n+\t};\n+\ttimer_ext1_output_pins: timer-ext1-output-pins {\n+\t\tfunction = \"timer_ext1\";\n+\t\tpins = \"PA28\", \"PA29\";\n+\t};\n+\text_ref_clk_pins: ext-ref-clk-pins {\n+\t\tfunction = \"ext_ref_clk\";\n+\t\tpins = \"PA30\";\n+\t};\n+\tmipi_ref_clk_pins: mipi-ref-clk-pins {\n+\t\tfunction = \"mipi_ref_clk\";\n+\t\tpins = \"PA31\";\n+\t};\n+};\ndiff --git a/arch/mips/boot/dts/mobileye/eyeq6lplus.dtsi b/arch/mips/boot/dts/mobileye/eyeq6lplus.dtsi\nnew file mode 100644\nindex 000000000000..28131ea558f6\n--- /dev/null\n+++ b/arch/mips/boot/dts/mobileye/eyeq6lplus.dtsi\n@@ -0,0 +1,169 @@\n+// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause\n+/*\n+ * Copyright 2025 Mobileye Vision Technologies Ltd.\n+ */\n+\n+#include <dt-bindings/interrupt-controller/mips-gic.h>\n+\n+#include <dt-bindings/clock/mobileye,eyeq6lplus-clk.h>\n+\n+/ {\n+\t#address-cells = <2>;\n+\t#size-cells = <2>;\n+\tcpus {\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\tcpu@0 {\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\tcompatible = \"img,i6500\";\n+\t\t\treg = <0>;\n+\t\t\tclocks = <&olb EQ6LPC_CPU_OCC>;\n+\t\t};\n+\t};\n+\n+\tcpu_intc: interrupt-controller {\n+\t\tcompatible = \"mti,cpu-interrupt-controller\";\n+\t\tinterrupt-controller;\n+\t\t#address-cells = <0>;\n+\t\t#interrupt-cells = <1>;\n+\t};\n+\n+\tcoherency-manager {\n+\t\tcompatible = \"mobileye,eyeq6-cm\";\n+\t};\n+\n+\txtal: clock-30000000 {\n+\t\tcompatible = \"fixed-clock\";\n+\t\t#clock-cells = <0>;\n+\t\tclock-frequency = <30000000>;\n+\t};\n+\n+\tsoc: soc {\n+\t\tcompatible = \"simple-bus\";\n+\t\t#address-cells = <2>;\n+\t\t#size-cells = <2>;\n+\t\tranges;\n+\n+\t\tolb: system-controller@e8400000 {\n+\t\t\tcompatible = \"mobileye,eyeq6lplus-olb\", \"syscon\";\n+\t\t\treg = <0 0xe8400000 0x0 0x80000>;\n+\t\t\t#reset-cells = <2>;\n+\t\t\t#clock-cells = <1>;\n+\t\t\tclocks = <&xtal>;\n+\t\t\tclock-names = \"ref\";\n+\t\t};\n+\n+\t\tospi: spi@e8800000 {\n+\t\t\tcompatible = \"mobileye,eyeq5-ospi\", \"cdns,qspi-nor\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <0 0xe8800000 0x0 0x100000>,\n+\t\t\t <0 0xb0000000 0x0 0x30000000>;\n+\t\t\tinterrupt-parent = <&gic>;\n+\t\t\tinterrupts = <GIC_SHARED 10 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tcdns,fifo-width = <4>;\n+\t\t\tcdns,trigger-address = <0x00000000>;\n+\t\t\tclocks = <&olb EQ6LPC_PER_OSPI>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tspi0: spi@eac0d000 {\n+\t\t\tcompatible = \"snps,dw-apb-ssi\";\n+\t\t\treg = <0 0xeac0d000 0x0 0x1000>;\n+\t\t\tclocks = <&olb EQ6LPC_PER_SPI>;\n+\t\t\tinterrupt-parent = <&gic>;\n+\t\t\tinterrupts = <GIC_SHARED 11 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tresets = <&olb 0 0>;\n+\t\t\treset-names = \"spi\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tspi1: spi@eac0e000 {\n+\t\t\tcompatible = \"snps,dw-apb-ssi\";\n+\t\t\treg = <0 0xeac0e000 0x0 0x1000>;\n+\t\t\tspi-slave;\n+\t\t\tclocks = <&olb EQ6LPC_PER_SPI>;\n+\t\t\tinterrupt-parent = <&gic>;\n+\t\t\tinterrupts = <GIC_SHARED 12 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tresets = <&olb 0 1>;\n+\t\t\treset-names = \"spi\";\n+\t\t\t#address-cells = <0>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tuart0: serial@eac10000 {\n+\t\t\tcompatible = \"snps,dw-apb-uart\";\n+\t\t\treg-shift = <2>;\n+\t\t\treg-io-width = <4>;\n+\t\t\tclocks = <&olb EQ6LPC_PER_UART>;\n+\t\t\tclock-frequency = <15625000>;\n+\t\t\treg = <0 0xeac10000 0x0 0x1000>;\n+\t\t\tinterrupt-parent = <&gic>;\n+\t\t\tinterrupts = <GIC_SHARED 8 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tresets = <&olb 0 2>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\ti2c0: i2c@eac11000 {\n+\t\t\tcompatible = \"mobileye,eyeq6lplus-i2c\", \"snps,designware-i2c\";\n+\t\t\treg = <0 0xeac11000 0x0 0x1000>;\n+\t\t\tinterrupt-parent = <&gic>;\n+\t\t\tinterrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tclock-frequency = <400000>;\n+\t\t\tclocks = <&olb EQ6LPC_PER_I2C_SER>;\n+\t\t\tresets = <&olb 0 3>;\n+\t\t\ti2c-sda-hold-time-ns = <50>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\ti2c1: i2c@eac12000 {\n+\t\t\tcompatible = \"mobileye,eyeq6lplus-i2c\", \"snps,designware-i2c\";\n+\t\t\treg = <0 0xeac12000 0x0 0x1000>;\n+\t\t\tinterrupt-parent = <&gic>;\n+\t\t\tinterrupts = <GIC_SHARED 7 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tclock-frequency = <400000>;\n+\t\t\tclocks = <&olb EQ6LPC_PER_I2C_SER>;\n+\t\t\tresets = <&olb 0 4>;\n+\t\t\ti2c-sda-hold-time-ns = <50>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tgpio: gpio@eac14000 {\n+\t\t\tcompatible = \"snps,dw-apb-gpio\";\n+\t\t\treg = <0x0 0xeac14000 0x0 0x1000>;\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tresets = <&olb 0 13>;\n+\t\t\tporta: gpio-port@0 {\n+\t\t\t\tcompatible = \"snps,dw-apb-gpio-port\";\n+\t\t\t\tgpio-controller;\n+\t\t\t\t#gpio-cells = <2>;\n+\t\t\t\tsnps,nr-gpios = <32>;\n+\t\t\t\tgpio-ranges = <&olb 0 0 32>;\n+\t\t\t\treg = <0>;\n+\t\t\t\tinterrupt-controller;\n+\t\t\t\t#interrupt-cells = <2>;\n+\t\t\t\tinterrupt-parent = <&gic>;\n+\t\t\t\tinterrupts = <GIC_SHARED 13 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\t};\n+\t\t};\n+\n+\t\tgic: interrupt-controller@f0920000 {\n+\t\t\tcompatible = \"mti,gic\";\n+\t\t\treg = <0x0 0xf0920000 0x0 0x20000>;\n+\t\t\tinterrupt-controller;\n+\t\t\t#interrupt-cells = <3>;\n+\t\t\tinterrupt-parent = <&cpu_intc>;\n+\t\t\ttimer {\n+\t\t\t\tcompatible = \"mti,gic-timer\";\n+\t\t\t\tinterrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;\n+\t\t\t\tclocks = <&olb EQ6LPC_CPU_OCC>;\n+\t\t\t};\n+\t\t};\n+\t};\n+};\n+\n+#include \"eyeq6lplus-pins.dtsi\"\n", "prefixes": [ "10/13" ] }