Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/1.0/patches/2175148/?format=api
{ "id": 2175148, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2175148/?format=api", "project": { "id": 42, "url": "http://patchwork.ozlabs.org/api/1.0/projects/42/?format=api", "name": "Linux GPIO development", "link_name": "linux-gpio", "list_id": "linux-gpio.vger.kernel.org", "list_email": "linux-gpio@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20251217-eyeq6lplus-v1-5-e9cdbd3af4c2@bootlin.com>", "date": "2025-12-17T13:35:55", "name": "[05/13] pinctrl: eyeq5: Use match data", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "5f8f1045652a093c707436aebeb99dbb5df6575c", "submitter": { "id": 91083, "url": "http://patchwork.ozlabs.org/api/1.0/people/91083/?format=api", "name": "Benoît Monin", "email": "benoit.monin@bootlin.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20251217-eyeq6lplus-v1-5-e9cdbd3af4c2@bootlin.com/mbox/", "series": [ { "id": 485688, "url": "http://patchwork.ozlabs.org/api/1.0/series/485688/?format=api", "date": "2025-12-17T13:35:54", "name": "Introducing the Mobileye EyeQ6Lplus SoC", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/485688/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2175148/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-gpio+bounces-29700-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-gpio@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=bootlin.com header.i=@bootlin.com header.a=rsa-sha256\n header.s=dkim header.b=V3+FXfi1;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=104.64.211.4; helo=sin.lore.kernel.org;\n envelope-from=linux-gpio+bounces-29700-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com\n header.b=\"V3+FXfi1\"", "smtp.subspace.kernel.org;\n arc=none smtp.client-ip=185.246.85.4", "smtp.subspace.kernel.org;\n dmarc=pass (p=reject dis=none) header.from=bootlin.com", "smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=bootlin.com" ], "Received": [ "from sin.lore.kernel.org (sin.lore.kernel.org [104.64.211.4])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4dWZd90HFrz1xty\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 18 Dec 2025 00:38:37 +1100 (AEDT)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sin.lore.kernel.org (Postfix) with ESMTP id AE0E63007B6D\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 17 Dec 2025 13:38:18 +0000 (UTC)", "from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 07D5934F247;\n\tWed, 17 Dec 2025 13:36:26 +0000 (UTC)", "from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id 19D4E346798;\n\tWed, 17 Dec 2025 13:36:22 +0000 (UTC)", "from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233])\n\tby smtpout-03.galae.net (Postfix) with ESMTPS id B307E4E41C5E;\n\tWed, 17 Dec 2025 13:36:21 +0000 (UTC)", "from mail.galae.net (mail.galae.net [212.83.136.155])\n\tby smtpout-01.galae.net (Postfix) with ESMTPS id 87FBC6072F;\n\tWed, 17 Dec 2025 13:36:21 +0000 (UTC)", "from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon)\n with ESMTPSA id E2207102F0ACE;\n\tWed, 17 Dec 2025 14:36:18 +0100 (CET)" ], "ARC-Seal": "i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1765978585; cv=none;\n b=iy0Q0mCwORC8GFq1fVfCU7gqWkTV7KOCiBtdN+KigJIRWYMqEbObT/PAEOsMVggfa20lRuCK92caxRc5G9iRY5xNUQgnw718Z5JqpEPw7oVQyHieWaJQ1IfDfc8mEOJxkJOZVvoVUIcitletQpUhvKb+pQ32j7zHppgcjpgW3+U=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1765978585; c=relaxed/simple;\n\tbh=bifdEjZFh7jinf0VhgdQJTXgZctdBLRhBgSP3vqBPKw=;\n\th=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References:\n\t In-Reply-To:To:Cc;\n b=EfmNTMcuRtrX+xZPUkm6uIt35qDXC7+HZdKpbjqY/2F3Css1eDFpxz5jEKltW3HkBnxg0sRdFITo6kXKkGPtbwZacwyES1Top6mrJJVNtDsk/BqfDsX635HkeskT8tZu+Jsx4E1sROtliLr7qdKBJ1inpQTPWV3zYZZlc65G44k=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dmarc=pass (p=reject dis=none) header.from=bootlin.com;\n spf=pass smtp.mailfrom=bootlin.com;\n dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com\n header.b=V3+FXfi1; arc=none smtp.client-ip=185.246.85.4", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim;\n\tt=1765978580; h=from:subject:date:message-id:to:cc:mime-version:content-type:\n\t content-transfer-encoding:in-reply-to:references;\n\tbh=62siuHUcQd2mNAFQkpqGve50puThCnRtOsOMamK3HiA=;\n\tb=V3+FXfi1YyUa9/L/43Tat4JQJvNYwKKr3gEsStUFOIDEGyHnuTTuIT9pv4vUGlVgvdLGZG\n\tAzXAJqj4VK8QjFLglAISc6n0yu/UjNSbkGtECeoCuFFIQZc+hNP1fK3w8X+AlwchbkafLh\n\tyMbrswqLzvtNdSYeoeWR2PGL3Jxn4Sm/Md3SxefynTRLg+g9p1osAvCdIkEBR65ohWUtM5\n\tVQ8fdFNLWBcpiGNQdDqw3qYEsQg1YGib39cZ387BDMSTtysmrI0IG2d6nSiMc2+hHhicXo\n\tCT1rkK1nqjjM6wlcnmBESVy6Ls0bw+QkH3dSxyocbZsw1MVRSfRUnCQNzDgHLw==", "From": "=?utf-8?q?Beno=C3=AEt_Monin?= <benoit.monin@bootlin.com>", "Date": "Wed, 17 Dec 2025 14:35:55 +0100", "Subject": "[PATCH 05/13] pinctrl: eyeq5: Use match data", "Precedence": "bulk", "X-Mailing-List": "linux-gpio@vger.kernel.org", "List-Id": "<linux-gpio.vger.kernel.org>", "List-Subscribe": "<mailto:linux-gpio+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-gpio+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "8bit", "Message-Id": "<20251217-eyeq6lplus-v1-5-e9cdbd3af4c2@bootlin.com>", "References": "<20251217-eyeq6lplus-v1-0-e9cdbd3af4c2@bootlin.com>", "In-Reply-To": "<20251217-eyeq6lplus-v1-0-e9cdbd3af4c2@bootlin.com>", "To": "Vladimir Kondratiev <vladimir.kondratiev@mobileye.com>,\n Gregory CLEMENT <gregory.clement@bootlin.com>,\n =?utf-8?q?Th=C3=A9o_Lebrun?= <theo.lebrun@bootlin.com>,\n Thomas Bogendoerfer <tsbogend@alpha.franken.de>,\n Rob Herring <robh@kernel.org>, Krzysztof Kozlowski <krzk+dt@kernel.org>,\n Conor Dooley <conor+dt@kernel.org>,\n Michael Turquette <mturquette@baylibre.com>,\n Stephen Boyd <sboyd@kernel.org>, Philipp Zabel <p.zabel@pengutronix.de>,\n Linus Walleij <linusw@kernel.org>", "Cc": "Thomas Petazzoni <thomas.petazzoni@bootlin.com>,\n Tawfik Bayouk <tawfik.bayouk@mobileye.com>, linux-mips@vger.kernel.org,\n devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, =?utf-8?q?Beno?=\n\t=?utf-8?q?=C3=AEt_Monin?= <benoit.monin@bootlin.com>", "X-Mailer": "b4 0.14.3", "X-Last-TLS-Session-Version": "TLSv1.3" }, "content": "Instead of using the pin descriptions, pin functions and register offsets\nof the EyeQ5 directly, access those via a pointer to a newly introduced\nstruct eq5p_match_data.\n\nThis structure contains, in addition to the pin descriptions and pin\nfunctions, an array of pin banks. Each bank holds the number of pins\nand the register offsets.\n\nAll functions accessing a pin now use a pointer to a bank structure and\nan offset inside that bank. The conversion from a pin number to a bank\nand an offset is done in the new function eq5p_pin_to_bank_offset(),\nwhich replace eq5p_pin_to_bank() and eq5p_pin_to_offset().\n\nAll the data related to the EyeQ5 is declared with the eq5p_eyeq5_\nprefix to distinguish it from the common code.\n\nDuring the probe, we now get a reference to the parent OF node if we\ndon't already have it and use that node to get the match data. We cannot\ndirectly use an OF node since pinctrl-eyeq5 is an auxiliary device\nof clk-eyeq.\n\nSigned-off-by: Benoît Monin <benoit.monin@bootlin.com>\n---\n drivers/pinctrl/pinctrl-eyeq5.c | 367 ++++++++++++++++++++++++++--------------\n 1 file changed, 239 insertions(+), 128 deletions(-)", "diff": "diff --git a/drivers/pinctrl/pinctrl-eyeq5.c b/drivers/pinctrl/pinctrl-eyeq5.c\nindex 5f6af934a516..e48add1d965d 100644\n--- a/drivers/pinctrl/pinctrl-eyeq5.c\n+++ b/drivers/pinctrl/pinctrl-eyeq5.c\n@@ -26,6 +26,7 @@\n #include <linux/errno.h>\n #include <linux/io.h>\n #include <linux/mod_devicetable.h>\n+#include <linux/of.h>\n #include <linux/seq_file.h>\n #include <linux/slab.h>\n #include <linux/types.h>\n@@ -38,18 +39,6 @@\n #include \"core.h\"\n #include \"pinctrl-utils.h\"\n \n-struct eq5p_pinctrl {\n-\tstruct pinctrl_desc\tdesc;\n-\tvoid __iomem\t\t*base;\n-};\n-\n-enum eq5p_bank {\n-\tEQ5P_BANK_A,\n-\tEQ5P_BANK_B,\n-\n-\tEQ5P_BANK_COUNT,\n-};\n-\n enum eq5p_regs {\n \tEQ5P_PD,\n \tEQ5P_PU,\n@@ -60,9 +49,24 @@ enum eq5p_regs {\n \tEQ5P_REG_COUNT,\n };\n \n-static const unsigned int eq5p_regs[EQ5P_BANK_COUNT][EQ5P_REG_COUNT] = {\n-\t[EQ5P_BANK_A] = {0x0C0, 0x0C4, 0x0D0, 0x0D4, 0x0B0},\n-\t[EQ5P_BANK_B] = {0x0C8, 0x0CC, 0x0D8, 0x0DC, 0x0B4},\n+struct eq5p_bank {\n+\tconst unsigned int npins;\n+\tconst unsigned int regs[EQ5P_REG_COUNT];\n+};\n+\n+struct eq5p_match_data {\n+\tconst unsigned int npins;\n+\tconst unsigned int nfunctions;\n+\tconst unsigned int nbanks;\n+\tconst struct pinctrl_pin_desc *pins;\n+\tconst struct pinfunction *functions;\n+\tconst struct eq5p_bank *banks;\n+};\n+\n+struct eq5p_pinctrl {\n+\tstruct pinctrl_desc\t\tdesc;\n+\tvoid __iomem\t\t\t*base;\n+\tconst struct eq5p_match_data\t*data;\n };\n \n /*\n@@ -70,10 +74,18 @@ static const unsigned int eq5p_regs[EQ5P_BANK_COUNT][EQ5P_REG_COUNT] = {\n */\n #define EQ5P_DS_MASK\tGENMASK(1, 0)\n \n+/*\n+ * The GPIO function is always the first function\n+ */\n+#define EQ5P_GPIO_FUNC_SELECTOR 0\n+\n+/* Helper to declare pinfunction */\n+#define EQ5P_PINFUNCTION(func, groups) PINCTRL_PINFUNCTION(func, groups, ARRAY_SIZE(groups))\n+\n /*\n * Comments to the right of each pin are the \"signal name\" in the datasheet.\n */\n-static const struct pinctrl_pin_desc eq5p_pins[] = {\n+static const struct pinctrl_pin_desc eq5p_eyeq5_pins[] = {\n \t/* Bank A */\n \tPINCTRL_PIN(0, \"PA0\"), /* A0_TIMER0_CK */\n \tPINCTRL_PIN(1, \"PA1\"), /* A1_TIMER0_EOC */\n@@ -105,35 +117,35 @@ static const struct pinctrl_pin_desc eq5p_pins[] = {\n \tPINCTRL_PIN(27, \"PA27\"), /* A27_SPI_1_CS1 */\n \tPINCTRL_PIN(28, \"PA28\"), /* A28_REF_CLK0 */\n \n-#define EQ5P_PIN_OFFSET_BANK_B\t29\n+#define EQ5P_EYEQ5_PIN_OFFSET_BANK_B\t29\n \n \t/* Bank B */\n-\tPINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 0, \"PB0\"), /* B0_TIMER3_CK */\n-\tPINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 1, \"PB1\"), /* B1_TIMER3_EOC */\n-\tPINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 2, \"PB2\"), /* B2_TIMER4_CK */\n-\tPINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 3, \"PB3\"), /* B3_TIMER4_EOC */\n-\tPINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 4, \"PB4\"), /* B4_TIMER6_EXT_INCAP1 */\n-\tPINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 5, \"PB5\"), /* B5_TIMER6_EXT_INCAP2 */\n-\tPINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 6, \"PB6\"), /* B6_TIMER6_EXT_OUTCMP1 */\n-\tPINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 7, \"PB7\"), /* B7_TIMER6_EXT_OUTCMP2 */\n-\tPINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 8, \"PB8\"), /* B8_UART_2_TX */\n-\tPINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 9, \"PB9\"), /* B9_UART_2_RX */\n-\tPINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 10, \"PB10\"), /* B10_CAN_2_TX */\n-\tPINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 11, \"PB11\"), /* B11_CAN_2_RX */\n-\tPINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 12, \"PB12\"), /* B12_SPI_2_DO */\n-\tPINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 13, \"PB13\"), /* B13_SPI_2_DI */\n-\tPINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 14, \"PB14\"), /* B14_SPI_2_CK */\n-\tPINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 15, \"PB15\"), /* B15_SPI_2_CS0 */\n-\tPINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 16, \"PB16\"), /* B16_SPI_2_CS1 */\n-\tPINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 17, \"PB17\"), /* B17_SPI_3_DO */\n-\tPINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 18, \"PB18\"), /* B18_SPI_3_DI */\n-\tPINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 19, \"PB19\"), /* B19_SPI_3_CK */\n-\tPINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 20, \"PB20\"), /* B20_SPI_3_CS0 */\n-\tPINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 21, \"PB21\"), /* B21_SPI_3_CS1 */\n-\tPINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 22, \"PB22\"), /* B22_MCLK0 */\n+\tPINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 0, \"PB0\"), /* B0_TIMER3_CK */\n+\tPINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 1, \"PB1\"), /* B1_TIMER3_EOC */\n+\tPINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 2, \"PB2\"), /* B2_TIMER4_CK */\n+\tPINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 3, \"PB3\"), /* B3_TIMER4_EOC */\n+\tPINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 4, \"PB4\"), /* B4_TIMER6_EXT_INCAP1 */\n+\tPINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 5, \"PB5\"), /* B5_TIMER6_EXT_INCAP2 */\n+\tPINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 6, \"PB6\"), /* B6_TIMER6_EXT_OUTCMP1 */\n+\tPINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 7, \"PB7\"), /* B7_TIMER6_EXT_OUTCMP2 */\n+\tPINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 8, \"PB8\"), /* B8_UART_2_TX */\n+\tPINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 9, \"PB9\"), /* B9_UART_2_RX */\n+\tPINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 10, \"PB10\"), /* B10_CAN_2_TX */\n+\tPINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 11, \"PB11\"), /* B11_CAN_2_RX */\n+\tPINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 12, \"PB12\"), /* B12_SPI_2_DO */\n+\tPINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 13, \"PB13\"), /* B13_SPI_2_DI */\n+\tPINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 14, \"PB14\"), /* B14_SPI_2_CK */\n+\tPINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 15, \"PB15\"), /* B15_SPI_2_CS0 */\n+\tPINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 16, \"PB16\"), /* B16_SPI_2_CS1 */\n+\tPINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 17, \"PB17\"), /* B17_SPI_3_DO */\n+\tPINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 18, \"PB18\"), /* B18_SPI_3_DI */\n+\tPINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 19, \"PB19\"), /* B19_SPI_3_CK */\n+\tPINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 20, \"PB20\"), /* B20_SPI_3_CS0 */\n+\tPINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 21, \"PB21\"), /* B21_SPI_3_CS1 */\n+\tPINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 22, \"PB22\"), /* B22_MCLK0 */\n };\n \n-static const char * const gpio_groups[] = {\n+static const char * const eq5p_eyeq5_gpio_groups[] = {\n \t/* Bank A */\n \t\"PA0\", \"PA1\", \"PA2\", \"PA3\", \"PA4\", \"PA5\", \"PA6\", \"PA7\",\n \t\"PA8\", \"PA9\", \"PA10\", \"PA11\", \"PA12\", \"PA13\", \"PA14\", \"PA15\",\n@@ -147,70 +159,90 @@ static const char * const gpio_groups[] = {\n };\n \n /* Groups of functions on bank A */\n-static const char * const timer0_groups[] = { \"PA0\", \"PA1\" };\n-static const char * const timer1_groups[] = { \"PA2\", \"PA3\" };\n-static const char * const timer2_groups[] = { \"PA4\", \"PA5\" };\n-static const char * const timer5_groups[] = { \"PA6\", \"PA7\", \"PA8\", \"PA9\" };\n-static const char * const uart0_groups[] = { \"PA10\", \"PA11\" };\n-static const char * const uart1_groups[] = { \"PA12\", \"PA13\" };\n-static const char * const can0_groups[] = { \"PA14\", \"PA15\" };\n-static const char * const can1_groups[] = { \"PA16\", \"PA17\" };\n-static const char * const spi0_groups[] = { \"PA18\", \"PA19\", \"PA20\", \"PA21\", \"PA22\" };\n-static const char * const spi1_groups[] = { \"PA23\", \"PA24\", \"PA25\", \"PA26\", \"PA27\" };\n-static const char * const refclk0_groups[] = { \"PA28\" };\n+static const char * const eq5p_eyeq5_timer0_groups[] = { \"PA0\", \"PA1\" };\n+static const char * const eq5p_eyeq5_timer1_groups[] = { \"PA2\", \"PA3\" };\n+static const char * const eq5p_eyeq5_timer2_groups[] = { \"PA4\", \"PA5\" };\n+static const char * const eq5p_eyeq5_timer5_groups[] = { \"PA6\", \"PA7\", \"PA8\", \"PA9\" };\n+static const char * const eq5p_eyeq5_uart0_groups[] = { \"PA10\", \"PA11\" };\n+static const char * const eq5p_eyeq5_uart1_groups[] = { \"PA12\", \"PA13\" };\n+static const char * const eq5p_eyeq5_can0_groups[] = { \"PA14\", \"PA15\" };\n+static const char * const eq5p_eyeq5_can1_groups[] = { \"PA16\", \"PA17\" };\n+static const char * const eq5p_eyeq5_spi0_groups[] = { \"PA18\", \"PA19\", \"PA20\", \"PA21\", \"PA22\" };\n+static const char * const eq5p_eyeq5_spi1_groups[] = { \"PA23\", \"PA24\", \"PA25\", \"PA26\", \"PA27\" };\n+static const char * const eq5p_eyeq5_refclk0_groups[] = { \"PA28\" };\n \n /* Groups of functions on bank B */\n-static const char * const timer3_groups[] = { \"PB0\", \"PB1\" };\n-static const char * const timer4_groups[] = { \"PB2\", \"PB3\" };\n-static const char * const timer6_groups[] = { \"PB4\", \"PB5\", \"PB6\", \"PB7\" };\n-static const char * const uart2_groups[] = { \"PB8\", \"PB9\" };\n-static const char * const can2_groups[] = { \"PB10\", \"PB11\" };\n-static const char * const spi2_groups[] = { \"PB12\", \"PB13\", \"PB14\", \"PB15\", \"PB16\" };\n-static const char * const spi3_groups[] = { \"PB17\", \"PB18\", \"PB19\", \"PB20\", \"PB21\" };\n-static const char * const mclk0_groups[] = { \"PB22\" };\n+static const char * const eq5p_eyeq5_timer3_groups[] = { \"PB0\", \"PB1\" };\n+static const char * const eq5p_eyeq5_timer4_groups[] = { \"PB2\", \"PB3\" };\n+static const char * const eq5p_eyeq5_timer6_groups[] = { \"PB4\", \"PB5\", \"PB6\", \"PB7\" };\n+static const char * const eq5p_eyeq5_uart2_groups[] = { \"PB8\", \"PB9\" };\n+static const char * const eq5p_eyeq5_can2_groups[] = { \"PB10\", \"PB11\" };\n+static const char * const eq5p_eyeq5_spi2_groups[] = { \"PB12\", \"PB13\", \"PB14\", \"PB15\", \"PB16\" };\n+static const char * const eq5p_eyeq5_spi3_groups[] = { \"PB17\", \"PB18\", \"PB19\", \"PB20\", \"PB21\" };\n+static const char * const eq5p_eyeq5_mclk0_groups[] = { \"PB22\" };\n \n-static const struct pinfunction eq5p_functions[] = {\n-\t/* GPIO having a fixed index is depended upon, see GPIO_FUNC_SELECTOR. */\n-\tPINCTRL_PINFUNCTION(\"gpio\", gpio_groups, ARRAY_SIZE(gpio_groups)),\n-#define GPIO_FUNC_SELECTOR 0\n+static const struct pinfunction eq5p_eyeq5_functions[] = {\n+\t/* GPIO having a fixed index is depended upon, see EQ5P_GPIO_FUNC_SELECTOR. */\n+\tEQ5P_PINFUNCTION(\"gpio\", eq5p_eyeq5_gpio_groups),\n \n \t/* Bank A functions */\n-\tPINCTRL_PINFUNCTION(\"timer0\", timer0_groups, ARRAY_SIZE(timer0_groups)),\n-\tPINCTRL_PINFUNCTION(\"timer1\", timer1_groups, ARRAY_SIZE(timer1_groups)),\n-\tPINCTRL_PINFUNCTION(\"timer2\", timer2_groups, ARRAY_SIZE(timer2_groups)),\n-\tPINCTRL_PINFUNCTION(\"timer5\", timer5_groups, ARRAY_SIZE(timer5_groups)),\n-\tPINCTRL_PINFUNCTION(\"uart0\", uart0_groups, ARRAY_SIZE(uart0_groups)),\n-\tPINCTRL_PINFUNCTION(\"uart1\", uart1_groups, ARRAY_SIZE(uart1_groups)),\n-\tPINCTRL_PINFUNCTION(\"can0\", can0_groups, ARRAY_SIZE(can0_groups)),\n-\tPINCTRL_PINFUNCTION(\"can1\", can1_groups, ARRAY_SIZE(can1_groups)),\n-\tPINCTRL_PINFUNCTION(\"spi0\", spi0_groups, ARRAY_SIZE(spi0_groups)),\n-\tPINCTRL_PINFUNCTION(\"spi1\", spi1_groups, ARRAY_SIZE(spi1_groups)),\n-\tPINCTRL_PINFUNCTION(\"refclk0\", refclk0_groups, ARRAY_SIZE(refclk0_groups)),\n+\tEQ5P_PINFUNCTION(\"timer0\", eq5p_eyeq5_timer0_groups),\n+\tEQ5P_PINFUNCTION(\"timer1\", eq5p_eyeq5_timer1_groups),\n+\tEQ5P_PINFUNCTION(\"timer2\", eq5p_eyeq5_timer2_groups),\n+\tEQ5P_PINFUNCTION(\"timer5\", eq5p_eyeq5_timer5_groups),\n+\tEQ5P_PINFUNCTION(\"uart0\", eq5p_eyeq5_uart0_groups),\n+\tEQ5P_PINFUNCTION(\"uart1\", eq5p_eyeq5_uart1_groups),\n+\tEQ5P_PINFUNCTION(\"can0\", eq5p_eyeq5_can0_groups),\n+\tEQ5P_PINFUNCTION(\"can1\", eq5p_eyeq5_can1_groups),\n+\tEQ5P_PINFUNCTION(\"spi0\", eq5p_eyeq5_spi0_groups),\n+\tEQ5P_PINFUNCTION(\"spi1\", eq5p_eyeq5_spi1_groups),\n+\tEQ5P_PINFUNCTION(\"refclk0\", eq5p_eyeq5_refclk0_groups),\n \n \t/* Bank B functions */\n-\tPINCTRL_PINFUNCTION(\"timer3\", timer3_groups, ARRAY_SIZE(timer3_groups)),\n-\tPINCTRL_PINFUNCTION(\"timer4\", timer4_groups, ARRAY_SIZE(timer4_groups)),\n-\tPINCTRL_PINFUNCTION(\"timer6\", timer6_groups, ARRAY_SIZE(timer6_groups)),\n-\tPINCTRL_PINFUNCTION(\"uart2\", uart2_groups, ARRAY_SIZE(uart2_groups)),\n-\tPINCTRL_PINFUNCTION(\"can2\", can2_groups, ARRAY_SIZE(can2_groups)),\n-\tPINCTRL_PINFUNCTION(\"spi2\", spi2_groups, ARRAY_SIZE(spi2_groups)),\n-\tPINCTRL_PINFUNCTION(\"spi3\", spi3_groups, ARRAY_SIZE(spi3_groups)),\n-\tPINCTRL_PINFUNCTION(\"mclk0\", mclk0_groups, ARRAY_SIZE(mclk0_groups)),\n+\tEQ5P_PINFUNCTION(\"timer3\", eq5p_eyeq5_timer3_groups),\n+\tEQ5P_PINFUNCTION(\"timer4\", eq5p_eyeq5_timer4_groups),\n+\tEQ5P_PINFUNCTION(\"timer6\", eq5p_eyeq5_timer6_groups),\n+\tEQ5P_PINFUNCTION(\"uart2\", eq5p_eyeq5_uart2_groups),\n+\tEQ5P_PINFUNCTION(\"can2\", eq5p_eyeq5_can2_groups),\n+\tEQ5P_PINFUNCTION(\"spi2\", eq5p_eyeq5_spi2_groups),\n+\tEQ5P_PINFUNCTION(\"spi3\", eq5p_eyeq5_spi3_groups),\n+\tEQ5P_PINFUNCTION(\"mclk0\", eq5p_eyeq5_mclk0_groups),\n+};\n+\n+static const struct eq5p_bank eq5p_eyeq5_banks[] = {\n+\t{\n+\t\t.npins = EQ5P_EYEQ5_PIN_OFFSET_BANK_B,\n+\t\t.regs = {0x0C0, 0x0C4, 0x0D0, 0x0D4, 0x0B0},\n+\t},\n+\t{\n+\t\t.npins = ARRAY_SIZE(eq5p_eyeq5_pins) - EQ5P_EYEQ5_PIN_OFFSET_BANK_B,\n+\t\t.regs = {0x0C8, 0x0CC, 0x0D8, 0x0DC, 0x0B4},\n+\t},\n+};\n+\n+static const struct eq5p_match_data eq5p_eyeq5_data = {\n+\t.npins = ARRAY_SIZE(eq5p_eyeq5_pins),\n+\t.nfunctions = ARRAY_SIZE(eq5p_eyeq5_functions),\n+\t.nbanks = ARRAY_SIZE(eq5p_eyeq5_banks),\n+\t.pins = eq5p_eyeq5_pins,\n+\t.functions = eq5p_eyeq5_functions,\n+\t.banks = eq5p_eyeq5_banks,\n };\n \n static void eq5p_update_bits(const struct eq5p_pinctrl *pctrl,\n-\t\t\t enum eq5p_bank bank, enum eq5p_regs reg,\n-\t\t\t u32 mask, u32 val)\n+\t\t\t const struct eq5p_bank *bank,\n+\t\t\t enum eq5p_regs reg, u32 mask, u32 val)\n {\n-\tvoid __iomem *ptr = pctrl->base + eq5p_regs[bank][reg];\n+\tvoid __iomem *ptr = pctrl->base + bank->regs[reg];\n \n \twritel((readl(ptr) & ~mask) | (val & mask), ptr);\n }\n \n static bool eq5p_test_bit(const struct eq5p_pinctrl *pctrl,\n-\t\t\t enum eq5p_bank bank, enum eq5p_regs reg, int offset)\n+\t\t\t const struct eq5p_bank *bank,\n+\t\t\t enum eq5p_regs reg, int offset)\n {\n-\tu32 val = readl(pctrl->base + eq5p_regs[bank][reg]);\n+\tu32 val = readl(pctrl->base + bank->regs[reg]);\n \n \tif (WARN_ON(offset > 31))\n \t\treturn false;\n@@ -218,25 +250,29 @@ static bool eq5p_test_bit(const struct eq5p_pinctrl *pctrl,\n \treturn (val & BIT(offset)) != 0;\n }\n \n-static enum eq5p_bank eq5p_pin_to_bank(unsigned int pin)\n+static int eq5p_pin_to_bank_offset(const struct eq5p_pinctrl *pctrl, unsigned int pin,\n+\t\t\t\t const struct eq5p_bank **bank, unsigned int *offset)\n {\n-\tif (pin < EQ5P_PIN_OFFSET_BANK_B)\n-\t\treturn EQ5P_BANK_A;\n-\telse\n-\t\treturn EQ5P_BANK_B;\n-}\n+\tfor (unsigned int i = 0; i < pctrl->data->nbanks; i++) {\n+\t\tconst struct eq5p_bank *_bank = &pctrl->data->banks[i];\n+\t\tunsigned int npins = _bank->npins;\n \n-static unsigned int eq5p_pin_to_offset(unsigned int pin)\n-{\n-\tif (pin < EQ5P_PIN_OFFSET_BANK_B)\n-\t\treturn pin;\n-\telse\n-\t\treturn pin - EQ5P_PIN_OFFSET_BANK_B;\n+\t\tif (pin < npins) {\n+\t\t\t*bank = _bank;\n+\t\t\t*offset = pin;\n+\t\t\treturn 0;\n+\t\t}\n+\t\tpin -= npins;\n+\t}\n+\n+\treturn -EINVAL;\n }\n \n static int eq5p_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)\n {\n-\treturn ARRAY_SIZE(eq5p_pins);\n+\tstruct eq5p_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);\n+\n+\treturn pctrl->data->npins;\n }\n \n static const char *eq5p_pinctrl_get_group_name(struct pinctrl_dev *pctldev,\n@@ -260,10 +296,15 @@ static int eq5p_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,\n {\n \tenum pin_config_param param = pinconf_to_config_param(*config);\n \tstruct eq5p_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);\n-\tunsigned int offset = eq5p_pin_to_offset(pin);\n-\tenum eq5p_bank bank = eq5p_pin_to_bank(pin);\n+\tconst struct eq5p_bank *bank;\n+\tunsigned int offset;\n \tu32 val_ds, arg;\n \tbool pd, pu;\n+\tint ret;\n+\n+\tret = eq5p_pin_to_bank_offset(pctrl, pin, &bank, &offset);\n+\tif (ret)\n+\t\treturn ret;\n \n \tpd = eq5p_test_bit(pctrl, bank, EQ5P_PD, offset);\n \tpu = eq5p_test_bit(pctrl, bank, EQ5P_PU, offset);\n@@ -281,10 +322,10 @@ static int eq5p_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,\n \tcase PIN_CONFIG_DRIVE_STRENGTH:\n \t\toffset *= 2; /* two bits per pin */\n \t\tif (offset >= 32) {\n-\t\t\tval_ds = readl(pctrl->base + eq5p_regs[bank][EQ5P_DS_HIGH]);\n+\t\t\tval_ds = readl(pctrl->base + bank->regs[EQ5P_DS_HIGH]);\n \t\t\toffset -= 32;\n \t\t} else {\n-\t\t\tval_ds = readl(pctrl->base + eq5p_regs[bank][EQ5P_DS_LOW]);\n+\t\t\tval_ds = readl(pctrl->base + bank->regs[EQ5P_DS_LOW]);\n \t\t}\n \t\targ = (val_ds >> offset) & EQ5P_DS_MASK;\n \t\tbreak;\n@@ -302,30 +343,35 @@ static void eq5p_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,\n {\n \tstruct eq5p_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);\n \tconst char *pin_name = pctrl->desc.pins[pin].name;\n-\tunsigned int offset = eq5p_pin_to_offset(pin);\n-\tenum eq5p_bank bank = eq5p_pin_to_bank(pin);\n+\tconst struct eq5p_bank *bank;\n \tconst char *func_name, *bias;\n \tunsigned long ds_config;\n+\tunsigned int offset;\n \tu32 drive_strength;\n \tbool pd, pu;\n \tint i, j;\n \n+\tif (eq5p_pin_to_bank_offset(pctrl, pin, &bank, &offset)) {\n+\t\tseq_puts(s, \"unknown pin\");\n+\t\treturn;\n+\t}\n+\n \t/*\n \t * First, let's get the function name. All pins have only two functions:\n \t * GPIO (IOCR == 0) and something else (IOCR == 1).\n \t */\n \tif (eq5p_test_bit(pctrl, bank, EQ5P_IOCR, offset)) {\n \t\tfunc_name = NULL;\n-\t\tfor (i = 0; i < ARRAY_SIZE(eq5p_functions); i++) {\n-\t\t\tif (i == GPIO_FUNC_SELECTOR)\n+\t\tfor (i = 0; i < pctrl->data->nfunctions; i++) {\n+\t\t\tif (i == EQ5P_GPIO_FUNC_SELECTOR)\n \t\t\t\tcontinue;\n \n-\t\t\tfor (j = 0; j < eq5p_functions[i].ngroups; j++) {\n+\t\t\tfor (j = 0; j < pctrl->data->functions[i].ngroups; j++) {\n \t\t\t\t/* Groups and pins are the same thing for us. */\n-\t\t\t\tconst char *x = eq5p_functions[i].groups[j];\n+\t\t\t\tconst char *x = pctrl->data->functions[i].groups[j];\n \n \t\t\t\tif (strcmp(x, pin_name) == 0) {\n-\t\t\t\t\tfunc_name = eq5p_functions[i].name;\n+\t\t\t\t\tfunc_name = pctrl->data->functions[i].name;\n \t\t\t\t\tbreak;\n \t\t\t\t}\n \t\t\t}\n@@ -341,7 +387,7 @@ static void eq5p_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,\n \t\tif (!func_name)\n \t\t\tfunc_name = \"unknown\";\n \t} else {\n-\t\tfunc_name = eq5p_functions[GPIO_FUNC_SELECTOR].name;\n+\t\tfunc_name = pctrl->data->functions[EQ5P_GPIO_FUNC_SELECTOR].name;\n \t}\n \n \t/* Second, we retrieve the bias. */\n@@ -376,13 +422,17 @@ static const struct pinctrl_ops eq5p_pinctrl_ops = {\n \n static int eq5p_pinmux_get_functions_count(struct pinctrl_dev *pctldev)\n {\n-\treturn ARRAY_SIZE(eq5p_functions);\n+\tstruct eq5p_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);\n+\n+\treturn pctrl->data->nfunctions;\n }\n \n static const char *eq5p_pinmux_get_function_name(struct pinctrl_dev *pctldev,\n \t\t\t\t\t\t unsigned int selector)\n {\n-\treturn eq5p_functions[selector].name;\n+\tstruct eq5p_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);\n+\n+\treturn pctrl->data->functions[selector].name;\n }\n \n static int eq5p_pinmux_get_function_groups(struct pinctrl_dev *pctldev,\n@@ -390,8 +440,10 @@ static int eq5p_pinmux_get_function_groups(struct pinctrl_dev *pctldev,\n \t\t\t\t\t const char * const **groups,\n \t\t\t\t\t unsigned int *num_groups)\n {\n-\t*groups = eq5p_functions[selector].groups;\n-\t*num_groups = eq5p_functions[selector].ngroups;\n+\tstruct eq5p_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);\n+\n+\t*groups = pctrl->data->functions[selector].groups;\n+\t*num_groups = pctrl->data->functions[selector].ngroups;\n \treturn 0;\n }\n \n@@ -399,12 +451,17 @@ static int eq5p_pinmux_set_mux(struct pinctrl_dev *pctldev,\n \t\t\t unsigned int func_selector, unsigned int pin)\n {\n \tstruct eq5p_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);\n-\tconst char *func_name = eq5p_functions[func_selector].name;\n+\tconst char *func_name = pctrl->data->functions[func_selector].name;\n \tconst char *group_name = pctldev->desc->pins[pin].name;\n-\tbool is_gpio = func_selector == GPIO_FUNC_SELECTOR;\n-\tunsigned int offset = eq5p_pin_to_offset(pin);\n-\tenum eq5p_bank bank = eq5p_pin_to_bank(pin);\n+\tbool is_gpio = func_selector == EQ5P_GPIO_FUNC_SELECTOR;\n+\tconst struct eq5p_bank *bank;\n+\tunsigned int offset;\n \tu32 mask, val;\n+\tint ret;\n+\n+\tret = eq5p_pin_to_bank_offset(pctrl, pin, &bank, &offset);\n+\tif (ret)\n+\t\treturn ret;\n \n \tdev_dbg(pctldev->dev, \"func=%s group=%s\\n\", func_name, group_name);\n \n@@ -419,7 +476,7 @@ static int eq5p_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev,\n \t\t\t\t\t unsigned int pin)\n {\n \t/* Pin numbers and group selectors are the same thing in our case. */\n-\treturn eq5p_pinmux_set_mux(pctldev, GPIO_FUNC_SELECTOR, pin);\n+\treturn eq5p_pinmux_set_mux(pctldev, EQ5P_GPIO_FUNC_SELECTOR, pin);\n }\n \n static const struct pinmux_ops eq5p_pinmux_ops = {\n@@ -435,10 +492,15 @@ static int eq5p_pinconf_set_drive_strength(struct pinctrl_dev *pctldev,\n \t\t\t\t\t unsigned int pin, u32 arg)\n {\n \tstruct eq5p_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);\n-\tunsigned int offset = eq5p_pin_to_offset(pin);\n-\tenum eq5p_bank bank = eq5p_pin_to_bank(pin);\n+\tconst struct eq5p_bank *bank;\n+\tunsigned int offset;\n \tunsigned int reg;\n \tu32 mask, val;\n+\tint ret;\n+\n+\tret = eq5p_pin_to_bank_offset(pctrl, pin, &bank, &offset);\n+\tif (ret)\n+\t\treturn ret;\n \n \tif (arg & ~EQ5P_DS_MASK) {\n \t\tdev_err(pctldev->dev, \"Unsupported drive strength: %u\\n\", arg);\n@@ -465,11 +527,16 @@ static int eq5p_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,\n {\n \tstruct eq5p_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);\n \tconst char *pin_name = pctldev->desc->pins[pin].name;\n-\tunsigned int offset = eq5p_pin_to_offset(pin);\n-\tenum eq5p_bank bank = eq5p_pin_to_bank(pin);\n \tstruct device *dev = pctldev->dev;\n+\tconst struct eq5p_bank *bank;\n+\tunsigned int offset;\n \tu32 val = BIT(offset);\n \tunsigned int i;\n+\tint ret;\n+\n+\tret = eq5p_pin_to_bank_offset(pctrl, pin, &bank, &offset);\n+\tif (ret)\n+\t\treturn ret;\n \n \tfor (i = 0; i < num_configs; i++) {\n \t\tenum pin_config_param param = pinconf_to_config_param(configs[i]);\n@@ -530,22 +597,57 @@ static const struct pinconf_ops eq5p_pinconf_ops = {\n \t.pin_config_group_set = eq5p_pinconf_set,\n };\n \n+static void eq5p_of_node_put(void *_dev)\n+{\n+\tstruct device *dev = _dev;\n+\n+\tof_node_put(dev->of_node);\n+}\n+\n static int eq5p_probe(struct auxiliary_device *adev,\n \t\t const struct auxiliary_device_id *id)\n {\n+\tconst struct of_device_id *match;\n \tstruct device *dev = &adev->dev;\n \tstruct pinctrl_dev *pctldev;\n \tstruct eq5p_pinctrl *pctrl;\n+\tbool need_of_put = false;\n \tint ret;\n \n+\t/*\n+\t * We are an auxiliary device of clk-eyeq. We do not have an OF node by\n+\t * default; let's reuse our parent's OF node if not already set.\n+\t */\n+\tif (!dev->of_node) {\n+\t\tdevice_set_of_node_from_dev(dev, dev->parent);\n+\t\tneed_of_put = true;\n+\t}\n+\tif (!dev->of_node)\n+\t\treturn -ENODEV;\n+\n+\tif (need_of_put) {\n+\t\tret = devm_add_action_or_reset(dev, eq5p_of_node_put, dev);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t}\n+\n+\t/*\n+\t * Using our newfound OF node, we can get match data. We cannot use\n+\t * device_get_match_data() because it does not match reused OF nodes.\n+\t */\n+\tmatch = of_match_node(dev->driver->of_match_table, dev->of_node);\n+\tif (!match || !match->data)\n+\t\treturn -ENODEV;\n+\n \tpctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL);\n \tif (!pctrl)\n \t\treturn -ENOMEM;\n \n \tpctrl->base = (void __iomem *)dev_get_platdata(dev);\n+\tpctrl->data = match->data;\n \tpctrl->desc.name = dev_name(dev);\n-\tpctrl->desc.pins = eq5p_pins;\n-\tpctrl->desc.npins = ARRAY_SIZE(eq5p_pins);\n+\tpctrl->desc.pins = pctrl->data->pins;\n+\tpctrl->desc.npins = pctrl->data->npins;\n \tpctrl->desc.pctlops = &eq5p_pinctrl_ops;\n \tpctrl->desc.pmxops = &eq5p_pinmux_ops;\n \tpctrl->desc.confops = &eq5p_pinconf_ops;\n@@ -562,6 +664,12 @@ static int eq5p_probe(struct auxiliary_device *adev,\n \treturn 0;\n }\n \n+static const struct of_device_id eq5p_match_table[] = {\n+\t{ .compatible = \"mobileye,eyeq5-olb\", .data = &eq5p_eyeq5_data },\n+\t{}\n+};\n+MODULE_DEVICE_TABLE(of, eq5p_match_table);\n+\n static const struct auxiliary_device_id eq5p_id_table[] = {\n \t{ .name = \"clk_eyeq.pinctrl\" },\n \t{}\n@@ -571,5 +679,8 @@ MODULE_DEVICE_TABLE(auxiliary, eq5p_id_table);\n static struct auxiliary_driver eq5p_driver = {\n \t.probe = eq5p_probe,\n \t.id_table = eq5p_id_table,\n+\t.driver = {\n+\t\t.of_match_table = eq5p_match_table,\n+\t}\n };\n module_auxiliary_driver(eq5p_driver);\n", "prefixes": [ "05/13" ] }