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GET /api/1.0/patches/2175116/?format=api
{ "id": 2175116, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2175116/?format=api", "project": { "id": 42, "url": "http://patchwork.ozlabs.org/api/1.0/projects/42/?format=api", "name": "Linux GPIO development", "link_name": "linux-gpio", "list_id": "linux-gpio.vger.kernel.org", "list_email": "linux-gpio@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20251217-staging-ad4062-v4-5-7890a2951a8f@analog.com>", "date": "2025-12-17T12:13:28", "name": "[v4,5/9] iio: adc: ad4062: Add IIO Trigger support", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "853c69c4f38cff91019a034fe7f27eb3ac0bd31a", "submitter": { "id": 90425, "url": "http://patchwork.ozlabs.org/api/1.0/people/90425/?format=api", "name": "Jorge Marques", "email": "jorge.marques@analog.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20251217-staging-ad4062-v4-5-7890a2951a8f@analog.com/mbox/", "series": [ { "id": 485673, "url": "http://patchwork.ozlabs.org/api/1.0/series/485673/?format=api", "date": "2025-12-17T12:13:23", "name": "Add support for AD4062 device family", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/485673/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2175116/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-gpio+bounces-29683-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-gpio@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=analog.com header.i=@analog.com header.a=rsa-sha256\n header.s=DKIM header.b=KvAQk4Eo;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.105.105.114; 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t=1765973659; c=relaxed/simple;\n\tbh=IXC04bKVME1MIN4tc1hJfbQ469/2PvuAl9H57VoRJtg=;\n\th=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References:\n\t In-Reply-To:To:CC;\n b=oG7MS8m9cBAoVct6i+rd7gKUrktEyd/+0rafQb5HkV0QTDGIReGN5WcG135HU3g9CdB8sl0XWEOqHnl2NudSGHyOiv+4WEh4nK2EHFSm8hGOpUvofe4QmumnlHJ+qRE3CoED3qdBoE/Kx2D76s26iMzx7fHW6bNO1/KlSO0ZcSM=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dmarc=pass (p=quarantine dis=none) header.from=analog.com;\n spf=pass smtp.mailfrom=analog.com;\n dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com\n header.b=KvAQk4Eo; arc=none smtp.client-ip=148.163.135.77", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=analog.com; h=cc\n\t:content-transfer-encoding:content-type:date:from:in-reply-to\n\t:message-id:mime-version:references:subject:to; s=DKIM; bh=F6kMV\n\tvXDxJtwauqyYrgwjcDvWbFhv8SJKq/0AaQJMTc=; b=KvAQk4EoEemoruT6YjjLS\n\tjABtfuV2ewRYT07T5ws9XVLj92mqVJUKByyfAdwGKKRvy2D59bYm1gIjwRD+jVpI\n\tbdcqPU+7794jo3vPdpADSBaHn4fsq8kOegbvRwAK1E3DhckdZlDtFQ17pwGqwu0w\n\tCMMM0i1+6v+NNUszyQuv/hYddyKOsounuPLLnZG/jWrFJwYQyqnvg1WlzOn/hRK7\n\tP+a79ombVpE2sGIKOmyiknNcyp7Gwawtr3bys+7bnzBWdjlRYQhyd9t9hr7kUtv/\n\tLqLQxOorkINqv0fU3nsfu/SmLJmCnutWX8skT8bqPtCqp+VtTdmUTV3VhxS2bYq5\n\tg==", "From": "Jorge Marques <jorge.marques@analog.com>", "Date": "Wed, 17 Dec 2025 13:13:28 +0100", "Subject": "[PATCH v4 5/9] iio: adc: ad4062: Add IIO Trigger support", "Precedence": "bulk", "X-Mailing-List": "linux-gpio@vger.kernel.org", "List-Id": "<linux-gpio.vger.kernel.org>", "List-Subscribe": "<mailto:linux-gpio+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-gpio+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-ID": "<20251217-staging-ad4062-v4-5-7890a2951a8f@analog.com>", "References": "<20251217-staging-ad4062-v4-0-7890a2951a8f@analog.com>", "In-Reply-To": "<20251217-staging-ad4062-v4-0-7890a2951a8f@analog.com>", "To": "Lars-Peter Clausen <lars@metafoo.de>,\n Michael Hennerich <Michael.Hennerich@analog.com>,\n Jonathan Cameron <jic23@kernel.org>, \"David Lechner\" <dlechner@baylibre.com>,\n\t=?utf-8?q?Nuno_S=C3=A1?= <nuno.sa@analog.com>,\n Andy Shevchenko <andy@kernel.org>, Rob Herring <robh@kernel.org>,\n Krzysztof Kozlowski <krzk+dt@kernel.org>, Conor Dooley <conor+dt@kernel.org>,\n Jonathan Corbet <corbet@lwn.net>, Linus Walleij <linus.walleij@linaro.org>,\n Bartosz Golaszewski <brgl@bgdev.pl>", "CC": "<linux-iio@vger.kernel.org>, <devicetree@vger.kernel.org>,\n <linux-kernel@vger.kernel.org>, <linux-doc@vger.kernel.org>,\n <linux-gpio@vger.kernel.org>, Jorge Marques <jorge.marques@analog.com>", "X-Mailer": "b4 0.14.3", "X-Developer-Signature": "v=1; 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Optionally, gp1 is assigned as Data Ready\nsignal, if not present, fallback to an I3C IBI with the same role.\nThe software trigger is allocated by the device, but must be attached by\nthe user before enabling the buffer. The purpose is to not impede\nremoving the driver due to the increased reference count when\niio_trigger_set_immutable() or iio_trigger_get() is used.\n\nSigned-off-by: Jorge Marques <jorge.marques@analog.com>\n---\n drivers/iio/adc/Kconfig | 2 +\n drivers/iio/adc/ad4062.c | 272 +++++++++++++++++++++++++++++++++++++++++++++--\n 2 files changed, 268 insertions(+), 6 deletions(-)", "diff": "diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig\nindex fda0da422c675..89a6486135f60 100644\n--- a/drivers/iio/adc/Kconfig\n+++ b/drivers/iio/adc/Kconfig\n@@ -74,6 +74,8 @@ config AD4062\n \ttristate \"Analog Devices AD4062 Driver\"\n \tdepends on I3C\n \tselect REGMAP_I3C\n+\tselect IIO_BUFFER\n+\tselect IIO_TRIGGERED_BUFFER\n \thelp\n \t Say yes here to build support for Analog Devices AD4062 I3C analog\n \t to digital converters (ADC).\ndiff --git a/drivers/iio/adc/ad4062.c b/drivers/iio/adc/ad4062.c\nindex 1a7829c507e53..afc8b6969cf08 100644\n--- a/drivers/iio/adc/ad4062.c\n+++ b/drivers/iio/adc/ad4062.c\n@@ -9,10 +9,15 @@\n #include <linux/bitops.h>\n #include <linux/completion.h>\n #include <linux/delay.h>\n+#include <linux/devm-helpers.h>\n #include <linux/err.h>\n #include <linux/i3c/device.h>\n #include <linux/i3c/master.h>\n+#include <linux/iio/buffer.h>\n #include <linux/iio/iio.h>\n+#include <linux/iio/trigger.h>\n+#include <linux/iio/trigger_consumer.h>\n+#include <linux/iio/triggered_buffer.h>\n #include <linux/interrupt.h>\n #include <linux/jiffies.h>\n #include <linux/math.h>\n@@ -59,6 +64,9 @@\n #define AD4062_REG_DEVICE_STATUS_DEVICE_RESET\tBIT(6)\n #define AD4062_REG_IBI_STATUS\t\t\t\t0x48\n #define AD4062_REG_CONV_READ_LSB\t\t\t0x50\n+#define AD4062_REG_CONV_READ_16BITS\t\t\t0x51\n+#define AD4062_REG_CONV_READ_32BITS\t\t\t0x53\n+#define AD4062_REG_CONV_TRIGGER_16BITS\t\t\t0x57\n #define AD4062_REG_CONV_TRIGGER_32BITS\t\t\t0x59\n #define AD4062_REG_CONV_AUTO\t\t\t\t0x61\n #define AD4062_MAX_REG\t\t\t\t\tAD4062_REG_CONV_AUTO\n@@ -94,6 +102,36 @@ enum {\n \tAD4062_SCAN_TYPE_BURST_AVG,\n };\n \n+static const struct iio_scan_type ad4062_scan_type_12_s[] = {\n+\t[AD4062_SCAN_TYPE_SAMPLE] = {\n+\t\t.sign = 's',\n+\t\t.realbits = 12,\n+\t\t.storagebits = 16,\n+\t\t.endianness = IIO_BE,\n+\t},\n+\t[AD4062_SCAN_TYPE_BURST_AVG] = {\n+\t\t.sign = 's',\n+\t\t.realbits = 14,\n+\t\t.storagebits = 16,\n+\t\t.endianness = IIO_BE,\n+\t},\n+};\n+\n+static const struct iio_scan_type ad4062_scan_type_16_s[] = {\n+\t[AD4062_SCAN_TYPE_SAMPLE] = {\n+\t\t.sign = 's',\n+\t\t.realbits = 16,\n+\t\t.storagebits = 16,\n+\t\t.endianness = IIO_BE,\n+\t},\n+\t[AD4062_SCAN_TYPE_BURST_AVG] = {\n+\t\t.sign = 's',\n+\t\t.realbits = 20,\n+\t\t.storagebits = 32,\n+\t\t.endianness = IIO_BE,\n+\t},\n+};\n+\n static const unsigned int ad4062_conversion_freqs[] = {\n \t2000000, 1000000, 300000, 100000,\t/* 0 - 3 */\n \t33300, 10000, 3000, 500,\t\t/* 4 - 7 */\n@@ -105,6 +143,7 @@ struct ad4062_state {\n \tconst struct ad4062_chip_info *chip;\n \tconst struct ad4062_bus_ops *ops;\n \tenum ad4062_operation_mode mode;\n+\tstruct work_struct trig_conv;\n \tstruct completion completion;\n \tstruct iio_trigger *trigger;\n \tstruct iio_dev *indio_dev;\n@@ -112,8 +151,10 @@ struct ad4062_state {\n \tstruct regmap *regmap;\n \tint vref_uV;\n \tunsigned int samp_freqs[ARRAY_SIZE(ad4062_conversion_freqs)];\n+\tbool gpo_irq[2];\n \tu16 sampling_frequency;\n \tu8 oversamp_ratio;\n+\tu8 conv_sizeof;\n \tu8 conv_addr;\n \tunion {\n \t\t__be32 be32;\n@@ -147,7 +188,7 @@ static const struct regmap_access_table ad4062_regmap_wr_table = {\n \t.n_yes_ranges = ARRAY_SIZE(ad4062_regmap_wr_ranges),\n };\n \n-#define AD4062_CHAN {\t\t\t\t\t\t\t\t\t\\\n+#define AD4062_CHAN(bits) {\t\t\t\t\t\t\t\t\\\n \t.type = IIO_VOLTAGE,\t\t\t\t\t\t\t\t\\\n \t.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_RAW) |\t\t\t\t\\\n \t\t\t\t BIT(IIO_CHAN_INFO_SCALE) |\t\t\t\t\\\n@@ -158,18 +199,21 @@ static const struct regmap_access_table ad4062_regmap_wr_table = {\n \t.info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_SAMP_FREQ),\t\t\\\n \t.indexed = 1,\t\t\t\t\t\t\t\t\t\\\n \t.channel = 0,\t\t\t\t\t\t\t\t\t\\\n+\t.has_ext_scan_type = 1,\t\t\t\t\t\t\t\t\\\n+\t.ext_scan_type = ad4062_scan_type_##bits##_s,\t\t\t\t\t\\\n+\t.num_ext_scan_type = ARRAY_SIZE(ad4062_scan_type_##bits##_s),\t\t\t\\\n }\n \n static const struct ad4062_chip_info ad4060_chip_info = {\n \t.name = \"ad4060\",\n-\t.channels = { AD4062_CHAN },\n+\t.channels = { AD4062_CHAN(12) },\n \t.prod_id = AD4060_PROD_ID,\n \t.avg_max = 256,\n };\n \n static const struct ad4062_chip_info ad4062_chip_info = {\n \t.name = \"ad4062\",\n-\t.channels = { AD4062_CHAN },\n+\t.channels = { AD4062_CHAN(16) },\n \t.prod_id = AD4062_PROD_ID,\n \t.avg_max = 4096,\n };\n@@ -334,8 +378,13 @@ static int ad4062_setup(struct iio_dev *indio_dev, struct iio_chan_spec const *c\n \t\t\tconst bool *ref_sel)\n {\n \tstruct ad4062_state *st = iio_priv(indio_dev);\n+\tconst struct iio_scan_type *scan_type;\n \tint ret;\n \n+\tscan_type = iio_get_current_scan_type(indio_dev, chan);\n+\tif (IS_ERR(scan_type))\n+\t\treturn PTR_ERR(scan_type);\n+\n \tret = regmap_update_bits(st->regmap, AD4062_REG_GP_CONF,\n \t\t\t\t AD4062_REG_GP_CONF_MODE_MSK_1,\n \t\t\t\t FIELD_PREP(AD4062_REG_GP_CONF_MODE_MSK_1,\n@@ -372,7 +421,10 @@ static irqreturn_t ad4062_irq_handler_drdy(int irq, void *private)\n \tstruct iio_dev *indio_dev = private;\n \tstruct ad4062_state *st = iio_priv(indio_dev);\n \n-\tcomplete(&st->completion);\n+\tif (iio_buffer_enabled(indio_dev) && iio_trigger_using_own(indio_dev))\n+\t\tiio_trigger_poll(st->trigger);\n+\telse\n+\t\tcomplete(&st->completion);\n \n \treturn IRQ_HANDLED;\n }\n@@ -382,7 +434,55 @@ static void ad4062_ibi_handler(struct i3c_device *i3cdev,\n {\n \tstruct ad4062_state *st = i3cdev_get_drvdata(i3cdev);\n \n-\tcomplete(&st->completion);\n+\tif (iio_buffer_enabled(st->indio_dev))\n+\t\tiio_trigger_poll_nested(st->trigger);\n+\telse\n+\t\tcomplete(&st->completion);\n+}\n+\n+static void ad4062_trigger_work(struct work_struct *work)\n+{\n+\tstruct ad4062_state *st =\n+\t\tcontainer_of(work, struct ad4062_state, trig_conv);\n+\tint ret;\n+\n+\t/*\n+\t * Read current conversion, if at reg CONV_READ, stop bit triggers\n+\t * next sample and does not need writing the address.\n+\t */\n+\tstruct i3c_priv_xfer xfer_sample = {\n+\t\t.data.in = &st->buf.be32,\n+\t\t.len = st->conv_sizeof,\n+\t\t.rnw = true,\n+\t};\n+\tstruct i3c_priv_xfer xfer_trigger = {\n+\t\t.data.out = &st->conv_addr,\n+\t\t.len = sizeof(st->conv_addr),\n+\t\t.rnw = false,\n+\t};\n+\n+\tret = i3c_device_do_priv_xfers(st->i3cdev, &xfer_sample, 1);\n+\tif (ret)\n+\t\treturn;\n+\n+\tiio_push_to_buffers_with_ts(st->indio_dev, &st->buf.be32, st->conv_sizeof,\n+\t\t\t\t iio_get_time_ns(st->indio_dev));\n+\tif (st->gpo_irq[1])\n+\t\treturn;\n+\n+\ti3c_device_do_priv_xfers(st->i3cdev, &xfer_trigger, 1);\n+}\n+\n+static irqreturn_t ad4062_poll_handler(int irq, void *p)\n+{\n+\tstruct iio_poll_func *pf = p;\n+\tstruct iio_dev *indio_dev = pf->indio_dev;\n+\tstruct ad4062_state *st = iio_priv(indio_dev);\n+\n+\tiio_trigger_notify_done(indio_dev->trig);\n+\tschedule_work(&st->trig_conv);\n+\n+\treturn IRQ_HANDLED;\n }\n \n static void ad4062_disable_ibi(void *data)\n@@ -433,10 +533,13 @@ static int ad4062_request_irq(struct iio_dev *indio_dev)\n \tif (ret == -EPROBE_DEFER)\n \t\treturn ret;\n \n-\tif (ret < 0)\n+\tif (ret < 0) {\n+\t\tst->gpo_irq[1] = false;\n \t\treturn regmap_update_bits(st->regmap, AD4062_REG_ADC_IBI_EN,\n \t\t\t\t\t AD4062_REG_ADC_IBI_EN_CONV_TRIGGER,\n \t\t\t\t\t AD4062_REG_ADC_IBI_EN_CONV_TRIGGER);\n+\t}\n+\tst->gpo_irq[1] = true;\n \n \treturn devm_request_threaded_irq(dev, ret,\n \t\t\t\t\t ad4062_irq_handler_drdy,\n@@ -444,6 +547,34 @@ static int ad4062_request_irq(struct iio_dev *indio_dev)\n \t\t\t\t\t indio_dev);\n }\n \n+static const struct iio_trigger_ops ad4062_trigger_ops = {\n+\t.validate_device = &iio_trigger_validate_own_device,\n+};\n+\n+static int ad4062_request_trigger(struct iio_dev *indio_dev)\n+{\n+\tstruct ad4062_state *st = iio_priv(indio_dev);\n+\tstruct device *dev = &st->i3cdev->dev;\n+\tint ret;\n+\n+\tst->trigger = devm_iio_trigger_alloc(dev, \"%s-dev%d\",\n+\t\t\t\t\t indio_dev->name,\n+\t\t\t\t\t iio_device_id(indio_dev));\n+\tif (!st->trigger)\n+\t\treturn -ENOMEM;\n+\n+\tst->trigger->ops = &ad4062_trigger_ops;\n+\tiio_trigger_set_drvdata(st->trigger, indio_dev);\n+\n+\tret = devm_iio_trigger_register(dev, st->trigger);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tindio_dev->trig = iio_trigger_get(st->trigger);\n+\n+\treturn 0;\n+}\n+\n static const int ad4062_oversampling_avail[] = {\n \t1, 2, 4, 8, 16, 32, 64, 128,\t\t/* 0 - 7 */\n \t256, 512, 1024, 2048, 4096,\t\t/* 8 - 12 */\n@@ -478,6 +609,25 @@ static int ad4062_read_avail(struct iio_dev *indio_dev,\n \t}\n }\n \n+static int ad4062_get_chan_scale(struct iio_dev *indio_dev, int *val, int *val2)\n+{\n+\tstruct ad4062_state *st = iio_priv(indio_dev);\n+\tconst struct iio_scan_type *scan_type;\n+\n+\t/*\n+\t * In burst averaging mode the averaging filter accumulates resulting\n+\t * in a sample with increased precision.\n+\t */\n+\tscan_type = iio_get_current_scan_type(indio_dev, st->chip->channels);\n+\tif (IS_ERR(scan_type))\n+\t\treturn PTR_ERR(scan_type);\n+\n+\t*val = (st->vref_uV * 2) / (MICRO / MILLI); /* signed */\n+\t*val2 = scan_type->realbits - 1;\n+\n+\treturn IIO_VAL_FRACTIONAL_LOG2;\n+}\n+\n static int ad4062_get_chan_calibscale(struct ad4062_state *st, int *val, int *val2)\n {\n \tint ret;\n@@ -593,6 +743,9 @@ static int ad4062_read_raw(struct iio_dev *indio_dev,\n \tint ret;\n \n \tswitch (info) {\n+\tcase IIO_CHAN_INFO_SCALE:\n+\t\treturn ad4062_get_chan_scale(indio_dev, val, val2);\n+\n \tcase IIO_CHAN_INFO_SAMP_FREQ:\n \t\treturn ad4062_get_sampling_frequency(st, val);\n \t}\n@@ -641,6 +794,87 @@ static int ad4062_write_raw(struct iio_dev *indio_dev,\n \treturn ret;\n }\n \n+/*\n+ * The AD4062 in burst averaging mode increases realbits from 16-bits to\n+ * 20-bits, increasing the storagebits from 16-bits to 32-bits.\n+ */\n+static inline size_t ad4062_sizeof_storagebits(struct ad4062_state *st)\n+{\n+\tconst struct iio_scan_type *scan_type =\n+\t\tiio_get_current_scan_type(st->indio_dev, st->chip->channels);\n+\n+\treturn BITS_TO_BYTES(scan_type->storagebits);\n+}\n+\n+/* Read registers only with realbits (no sign extension bytes) */\n+static inline size_t ad4062_get_conv_addr(struct ad4062_state *st, size_t _sizeof)\n+{\n+\tif (st->gpo_irq[1])\n+\t\treturn _sizeof == sizeof(u32) ? AD4062_REG_CONV_READ_32BITS :\n+\t\t\t\t\t\tAD4062_REG_CONV_READ_16BITS;\n+\treturn _sizeof == sizeof(u32) ? AD4062_REG_CONV_TRIGGER_32BITS :\n+\t\t\t\t\tAD4062_REG_CONV_TRIGGER_16BITS;\n+}\n+\n+static int pm_ad4062_triggered_buffer_postenable(struct ad4062_state *st)\n+{\n+\tint ret;\n+\n+\tPM_RUNTIME_ACQUIRE(&st->i3cdev->dev, pm);\n+\tret = PM_RUNTIME_ACQUIRE_ERR(&pm);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = ad4062_set_operation_mode(st, st->mode);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tst->conv_sizeof = ad4062_sizeof_storagebits(st);\n+\tst->conv_addr = ad4062_get_conv_addr(st, st->conv_sizeof);\n+\t/* CONV_READ requires read to trigger first sample. */\n+\tstruct i3c_priv_xfer xfer_sample[2] = {\n+\t\t{\n+\t\t\t.data.out = &st->conv_addr,\n+\t\t\t.len = sizeof(st->conv_addr),\n+\t\t\t.rnw = false,\n+\t\t},\n+\t\t{\n+\t\t\t.data.in = &st->buf.be32,\n+\t\t\t.len = sizeof(st->buf.be32),\n+\t\t\t.rnw = true,\n+\t\t}\n+\t};\n+\n+\treturn i3c_device_do_priv_xfers(st->i3cdev, xfer_sample,\n+\t\t\t\t\tst->gpo_irq[1] ? 2 : 1);\n+}\n+\n+static int ad4062_triggered_buffer_postenable(struct iio_dev *indio_dev)\n+{\n+\tstruct ad4062_state *st = iio_priv(indio_dev);\n+\tint ret;\n+\n+\tret = pm_ad4062_triggered_buffer_postenable(st);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tpm_runtime_get_noresume(&st->i3cdev->dev);\n+\treturn 0;\n+}\n+\n+static int ad4062_triggered_buffer_predisable(struct iio_dev *indio_dev)\n+{\n+\tstruct ad4062_state *st = iio_priv(indio_dev);\n+\n+\tpm_runtime_put_autosuspend(&st->i3cdev->dev);\n+\treturn 0;\n+}\n+\n+static const struct iio_buffer_setup_ops ad4062_triggered_buffer_setup_ops = {\n+\t.postenable = &ad4062_triggered_buffer_postenable,\n+\t.predisable = &ad4062_triggered_buffer_predisable,\n+};\n+\n static int ad4062_debugfs_reg_access(struct iio_dev *indio_dev, unsigned int reg,\n \t\t\t\t unsigned int writeval, unsigned int *readval)\n {\n@@ -652,10 +886,21 @@ static int ad4062_debugfs_reg_access(struct iio_dev *indio_dev, unsigned int reg\n \t\treturn regmap_write(st->regmap, reg, writeval);\n }\n \n+static int ad4062_get_current_scan_type(const struct iio_dev *indio_dev,\n+\t\t\t\t\tconst struct iio_chan_spec *chan)\n+{\n+\tstruct ad4062_state *st = iio_priv(indio_dev);\n+\n+\treturn st->mode == AD4062_BURST_AVERAGING_MODE ?\n+\t\t\t AD4062_SCAN_TYPE_BURST_AVG :\n+\t\t\t AD4062_SCAN_TYPE_SAMPLE;\n+}\n+\n static const struct iio_info ad4062_info = {\n \t.read_raw = ad4062_read_raw,\n \t.write_raw = ad4062_write_raw,\n \t.read_avail = ad4062_read_avail,\n+\t.get_current_scan_type = ad4062_get_current_scan_type,\n \t.debugfs_reg_access = ad4062_debugfs_reg_access,\n };\n \n@@ -762,6 +1007,17 @@ static int ad4062_probe(struct i3c_device *i3cdev)\n \tif (ret)\n \t\treturn ret;\n \n+\tret = ad4062_request_trigger(indio_dev);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = devm_iio_triggered_buffer_setup(&i3cdev->dev, indio_dev,\n+\t\t\t\t\t iio_pollfunc_store_time,\n+\t\t\t\t\t ad4062_poll_handler,\n+\t\t\t\t\t &ad4062_triggered_buffer_setup_ops);\n+\tif (ret)\n+\t\treturn ret;\n+\n \tpm_runtime_set_active(dev);\n \tret = devm_pm_runtime_enable(dev);\n \tif (ret)\n@@ -774,6 +1030,10 @@ static int ad4062_probe(struct i3c_device *i3cdev)\n \tif (ret)\n \t\treturn dev_err_probe(dev, ret, \"Failed to request i3c ibi\\n\");\n \n+\tret = devm_work_autocancel(dev, &st->trig_conv, ad4062_trigger_work);\n+\tif (ret)\n+\t\treturn ret;\n+\n \treturn devm_iio_device_register(dev, indio_dev);\n }\n \n", "prefixes": [ "v4", "5/9" ] }