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GET /api/1.0/patches/2175115/?format=api
{ "id": 2175115, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2175115/?format=api", "project": { "id": 42, "url": "http://patchwork.ozlabs.org/api/1.0/projects/42/?format=api", "name": "Linux GPIO development", "link_name": "linux-gpio", "list_id": "linux-gpio.vger.kernel.org", "list_email": "linux-gpio@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20251217-staging-ad4062-v4-3-7890a2951a8f@analog.com>", "date": "2025-12-17T12:13:26", "name": "[v4,3/9] iio: adc: Add support for ad4062", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "e99f4da85d00da4b7e0b09c76c2b24b40593cefa", "submitter": { "id": 90425, "url": "http://patchwork.ozlabs.org/api/1.0/people/90425/?format=api", "name": "Jorge Marques", "email": "jorge.marques@analog.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20251217-staging-ad4062-v4-3-7890a2951a8f@analog.com/mbox/", "series": [ { "id": 485673, "url": "http://patchwork.ozlabs.org/api/1.0/series/485673/?format=api", "date": "2025-12-17T12:13:23", "name": "Add support for AD4062 device family", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/485673/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2175115/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-gpio+bounces-29682-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-gpio@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=analog.com header.i=@analog.com header.a=rsa-sha256\n header.s=DKIM header.b=LCN80RrK;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.105.105.114; helo=tor.lore.kernel.org;\n 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(2048-bit key) header.d=analog.com header.i=@analog.com\n header.b=LCN80RrK; arc=none smtp.client-ip=148.163.135.77", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=analog.com; h=cc\n\t:content-transfer-encoding:content-type:date:from:in-reply-to\n\t:message-id:mime-version:references:subject:to; s=DKIM; bh=wcP/k\n\tw40zLFnIUUIa2BpuSq1xwY/eJALWByii50H47I=; b=LCN80RrKAYuxxGrKHFgwF\n\t4mZsflAyawveklTpy9MS5DzTGJcj+a6zjy94p8zTYJ3/826qn0WJhOS636kLZu7B\n\tcZFJz7VcRskQMi9pnFOHCcL4GTfzdi9FkeKwCRRpjxmZXymmZtWUbFuQ5TBbxpTs\n\trx97YelOqPXIU+a/dp140d2uXjs5sBHhHkFbl09ZoN6dVQGFJ7q+fNLDYGzxENI5\n\t7xZRZyTNS16uXs+EOOeWeq5I2HiLr/adpeuF/xHxBUfR+gf9XnrGKei6Kb+9PEPA\n\tG2SKde/pPHMl/Odse8rAUtE3QcyrnV/D1i2WNvy8Ge+8GY3V4mTyfW2MBPT7VVUh\n\tw==", "From": "Jorge Marques <jorge.marques@analog.com>", "Date": "Wed, 17 Dec 2025 13:13:26 +0100", "Subject": "[PATCH v4 3/9] iio: adc: Add support for ad4062", "Precedence": "bulk", "X-Mailing-List": "linux-gpio@vger.kernel.org", "List-Id": "<linux-gpio.vger.kernel.org>", "List-Subscribe": "<mailto:linux-gpio+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-gpio+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "8bit", "Message-ID": "<20251217-staging-ad4062-v4-3-7890a2951a8f@analog.com>", "References": "<20251217-staging-ad4062-v4-0-7890a2951a8f@analog.com>", "In-Reply-To": "<20251217-staging-ad4062-v4-0-7890a2951a8f@analog.com>", "To": "Lars-Peter Clausen <lars@metafoo.de>,\n Michael Hennerich <Michael.Hennerich@analog.com>,\n Jonathan Cameron <jic23@kernel.org>, \"David Lechner\" <dlechner@baylibre.com>,\n\t=?utf-8?q?Nuno_S=C3=A1?= <nuno.sa@analog.com>,\n Andy Shevchenko <andy@kernel.org>, Rob Herring <robh@kernel.org>,\n Krzysztof Kozlowski <krzk+dt@kernel.org>, Conor Dooley <conor+dt@kernel.org>,\n Jonathan Corbet <corbet@lwn.net>, Linus Walleij <linus.walleij@linaro.org>,\n Bartosz Golaszewski <brgl@bgdev.pl>", "CC": "<linux-iio@vger.kernel.org>, <devicetree@vger.kernel.org>,\n <linux-kernel@vger.kernel.org>, <linux-doc@vger.kernel.org>,\n <linux-gpio@vger.kernel.org>, Jorge Marques <jorge.marques@analog.com>", "X-Mailer": "b4 0.14.3", "X-Developer-Signature": "v=1; a=ed25519-sha256; t=1765973610; l=25485;\n i=jorge.marques@analog.com; s=20250303; h=from:subject:message-id;\n bh=LWXQ4/4Li7osJ/KwR7gbjFgHvTSW4+Ar40cZGHR0InQ=;\n b=zIhOP8IoXiXl9OAPMi0PGIye1weo0Q8RUixWC8cg0avrO0GMm5TtkjIhRz7e+O33VEHy49aWg\n BOIOA/WFU5gA724cPM8ssHBTDYYjzF5pb2rUlAjWkqIv8+oPLD+fEKJ", "X-Developer-Key": "i=jorge.marques@analog.com; a=ed25519;\n pk=NUR1IZZMH0Da3QbJ2tBSznSPVfRpuoWdhBzKGSpAdbg=", "X-ADIRuleOP-NewSCL": "Rule Triggered", "X-Proofpoint-ORIG-GUID": "CvpnPnbeIdMjOqWwlryrk8vlavvYlocp", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjUxMjE3MDA5NSBTYWx0ZWRfX9JdG+e+fRxu5\n ++QqEq0tBAjY0AZnsOdMzNWpOtE4qZmlBn1ZqI0m3QLj/zx2BnwSlJBVbgCgznAiCJkmnSejH0y\n q6aI2nQ5uz8ZeEIUSQLqjOlfydCFJfCjMPI59R1oCToCjr8bIibJaL+1P+wHpcmD/+7nUiSD1la\n 7rDlMfXasXqnkQE+5SnV9SxRDS3OzG+FtPHReOJRZiWFPJ5iLNJFXZWIbNN4GU7/uZRyOzjJ1Jg\n 1woZ1ZfzRcL+1k1f20FtSAwlX9hTgQvrE22ZOneP+n3qVU23Axuxxtsw9AMSBJyeFv/OuuTqYxT\n 6DHmnr4mGUl2PZUCQ+rVBssFc/gOqtx6wylpSQvgfWRJ+la9871/Pap9AE+iSbT2xoelN8weXDh\n gJQ+xtvn+g24bp5Pr/rBRtmWj3Y4KQ==", "X-Authority-Analysis": "v=2.4 cv=YqsChoYX c=1 sm=1 tr=0 ts=69429e81 cx=c_pps\n a=3WNzaoukacrqR9RwcOSAdA==:117 a=3WNzaoukacrqR9RwcOSAdA==:17\n a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=VkNPw1HP01LnGYTKEx00:22\n a=gAnH3GRIAAAA:8 a=npeQ3yjGmb6k4UAFlcAA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10", "X-Proofpoint-GUID": "CvpnPnbeIdMjOqWwlryrk8vlavvYlocp", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49\n definitions=2025-12-17_01,2025-12-16_05,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n spamscore=0 malwarescore=0 bulkscore=0 suspectscore=0 lowpriorityscore=0\n phishscore=0 impostorscore=0 clxscore=1015 adultscore=0 priorityscore=1501\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2512170095" }, "content": "The AD4060/AD4062 are versatile, 16-bit/12-bit, successive approximation\nregister (SAR) analog-to-digital converter (ADC) with low-power and\nthreshold monitoring modes.\n\nSigned-off-by: Jorge Marques <jorge.marques@analog.com>\n---\n MAINTAINERS | 1 +\n drivers/iio/adc/Kconfig | 11 +\n drivers/iio/adc/Makefile | 1 +\n drivers/iio/adc/ad4062.c | 819 +++++++++++++++++++++++++++++++++++++++++++++++\n 4 files changed, 832 insertions(+)", "diff": "diff --git a/MAINTAINERS b/MAINTAINERS\nindex 0730b79c3dd0d..301318de29af7 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -1438,6 +1438,7 @@ S:\tSupported\n W:\thttps://ez.analog.com/linux-software-drivers\n F:\tDocumentation/devicetree/bindings/iio/adc/adi,ad4062.yaml\n F:\tDocumentation/iio/ad4062.rst\n+F:\tdrivers/iio/adc/ad4062.c\n \n ANALOG DEVICES INC AD4080 DRIVER\n M:\tAntoniu Miclaus <antoniu.miclaus@analog.com>\ndiff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig\nindex 576480e3ac4a4..fda0da422c675 100644\n--- a/drivers/iio/adc/Kconfig\n+++ b/drivers/iio/adc/Kconfig\n@@ -70,6 +70,17 @@ config AD4030\n \t To compile this driver as a module, choose M here: the module will be\n \t called ad4030.\n \n+config AD4062\n+\ttristate \"Analog Devices AD4062 Driver\"\n+\tdepends on I3C\n+\tselect REGMAP_I3C\n+\thelp\n+\t Say yes here to build support for Analog Devices AD4062 I3C analog\n+\t to digital converters (ADC).\n+\n+\t To compile this driver as a module, choose M here: the module will be\n+\t called ad4062.\n+\n config AD4080\n \ttristate \"Analog Devices AD4080 high speed ADC\"\n \tdepends on SPI\ndiff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile\nindex b1b1d5a2273f2..0a199630c0812 100644\n--- a/drivers/iio/adc/Makefile\n+++ b/drivers/iio/adc/Makefile\n@@ -11,6 +11,7 @@ obj-$(CONFIG_AB8500_GPADC) += ab8500-gpadc.o\n obj-$(CONFIG_AD_SIGMA_DELTA) += ad_sigma_delta.o\n obj-$(CONFIG_AD4000) += ad4000.o\n obj-$(CONFIG_AD4030) += ad4030.o\n+obj-$(CONFIG_AD4062) += ad4062.o\n obj-$(CONFIG_AD4080) += ad4080.o\n obj-$(CONFIG_AD4130) += ad4130.o\n obj-$(CONFIG_AD4170_4) += ad4170-4.o\ndiff --git a/drivers/iio/adc/ad4062.c b/drivers/iio/adc/ad4062.c\nnew file mode 100644\nindex 0000000000000..1a7829c507e53\n--- /dev/null\n+++ b/drivers/iio/adc/ad4062.c\n@@ -0,0 +1,819 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * Analog Devices AD4062 I3C ADC driver\n+ *\n+ * Copyright 2025 Analog Devices Inc.\n+ */\n+#include <linux/array_size.h>\n+#include <linux/bitfield.h>\n+#include <linux/bitops.h>\n+#include <linux/completion.h>\n+#include <linux/delay.h>\n+#include <linux/err.h>\n+#include <linux/i3c/device.h>\n+#include <linux/i3c/master.h>\n+#include <linux/iio/iio.h>\n+#include <linux/interrupt.h>\n+#include <linux/jiffies.h>\n+#include <linux/math.h>\n+#include <linux/minmax.h>\n+#include <linux/pm_runtime.h>\n+#include <linux/property.h>\n+#include <linux/regmap.h>\n+#include <linux/regulator/consumer.h>\n+#include <linux/string.h>\n+#include <linux/types.h>\n+#include <linux/units.h>\n+#include <linux/unaligned.h>\n+#include <linux/util_macros.h>\n+\n+#define AD4062_REG_INTERFACE_CONFIG_A\t\t\t0x00\n+#define AD4062_REG_DEVICE_CONFIG\t\t\t0x02\n+#define AD4062_REG_DEVICE_CONFIG_POWER_MODE_MSK\tGENMASK(1, 0)\n+#define AD4062_REG_DEVICE_CONFIG_LOW_POWER_MODE\t3\n+#define AD4062_REG_PROD_ID_1\t\t\t\t0x05\n+#define AD4062_REG_DEVICE_GRADE\t\t\t\t0x06\n+#define AD4062_REG_SCRATCH_PAD\t\t\t\t0x0A\n+#define AD4062_REG_VENDOR_H\t\t\t\t0x0D\n+#define AD4062_REG_STREAM_MODE\t\t\t\t0x0E\n+#define AD4062_REG_INTERFACE_STATUS\t\t\t0x11\n+#define AD4062_REG_MODE_SET\t\t\t\t0x20\n+#define AD4062_REG_MODE_SET_ENTER_ADC\t\tBIT(0)\n+#define AD4062_REG_ADC_MODES\t\t\t\t0x21\n+#define AD4062_REG_ADC_MODES_MODE_MSK\t\tGENMASK(1, 0)\n+#define AD4062_REG_ADC_CONFIG\t\t\t\t0x22\n+#define AD4062_REG_ADC_CONFIG_REF_EN_MSK\t\tBIT(5)\n+#define AD4062_REG_ADC_CONFIG_SCALE_EN_MSK\t\tBIT(4)\n+#define AD4062_REG_AVG_CONFIG\t\t\t\t0x23\n+#define AD4062_REG_GP_CONF\t\t\t\t0x24\n+#define AD4062_REG_GP_CONF_MODE_MSK_1\t\tGENMASK(6, 4)\n+#define AD4062_REG_INTR_CONF\t\t\t\t0x25\n+#define AD4062_REG_INTR_CONF_EN_MSK_1\t\tGENMASK(5, 4)\n+#define AD4062_REG_TIMER_CONFIG\t\t\t\t0x27\n+#define AD4062_REG_TIMER_CONFIG_FS_MASK\t\tGENMASK(7, 4)\n+#define AD4062_REG_MON_VAL\t\t\t\t0x2F\n+#define AD4062_REG_ADC_IBI_EN\t\t\t\t0x31\n+#define AD4062_REG_ADC_IBI_EN_CONV_TRIGGER\t\tBIT(2)\n+#define AD4062_REG_FUSE_CRC\t\t\t\t0x40\n+#define AD4062_REG_DEVICE_STATUS\t\t\t0x41\n+#define AD4062_REG_DEVICE_STATUS_DEVICE_RESET\tBIT(6)\n+#define AD4062_REG_IBI_STATUS\t\t\t\t0x48\n+#define AD4062_REG_CONV_READ_LSB\t\t\t0x50\n+#define AD4062_REG_CONV_TRIGGER_32BITS\t\t\t0x59\n+#define AD4062_REG_CONV_AUTO\t\t\t\t0x61\n+#define AD4062_MAX_REG\t\t\t\t\tAD4062_REG_CONV_AUTO\n+\n+#define AD4062_MON_VAL_MIDDLE_POINT\t0x8000\n+\n+#define AD4062_I3C_VENDOR\t0x0177\n+#define AD4062_SOFT_RESET\t0x81\n+#define AD4060_PROD_ID\t\t0x7A\n+#define AD4062_PROD_ID\t\t0x7C\n+\n+#define AD4062_GP_DRDY\t\t0x2\n+\n+#define AD4062_INTR_EN_NEITHER\t0x0\n+\n+#define AD4062_TCONV_NS\t\t270\n+\n+enum ad4062_operation_mode {\n+\tAD4062_SAMPLE_MODE = 0x0,\n+\tAD4062_BURST_AVERAGING_MODE = 0x1,\n+\tAD4062_MONITOR_MODE = 0x3,\n+};\n+\n+struct ad4062_chip_info {\n+\tconst struct iio_chan_spec channels[1];\n+\tconst char *name;\n+\tu16 prod_id;\n+\tu16 avg_max;\n+};\n+\n+enum {\n+\tAD4062_SCAN_TYPE_SAMPLE,\n+\tAD4062_SCAN_TYPE_BURST_AVG,\n+};\n+\n+static const unsigned int ad4062_conversion_freqs[] = {\n+\t2000000, 1000000, 300000, 100000,\t/* 0 - 3 */\n+\t33300, 10000, 3000, 500,\t\t/* 4 - 7 */\n+\t333, 250, 200, 166,\t\t\t/* 8 - 11 */\n+\t140, 124, 111,\t\t\t\t/* 12 - 15 */\n+};\n+\n+struct ad4062_state {\n+\tconst struct ad4062_chip_info *chip;\n+\tconst struct ad4062_bus_ops *ops;\n+\tenum ad4062_operation_mode mode;\n+\tstruct completion completion;\n+\tstruct iio_trigger *trigger;\n+\tstruct iio_dev *indio_dev;\n+\tstruct i3c_device *i3cdev;\n+\tstruct regmap *regmap;\n+\tint vref_uV;\n+\tunsigned int samp_freqs[ARRAY_SIZE(ad4062_conversion_freqs)];\n+\tu16 sampling_frequency;\n+\tu8 oversamp_ratio;\n+\tu8 conv_addr;\n+\tunion {\n+\t\t__be32 be32;\n+\t\t__be16 be16;\n+\t} buf __aligned(IIO_DMA_MINALIGN);\n+};\n+\n+static const struct regmap_range ad4062_regmap_rd_ranges[] = {\n+\tregmap_reg_range(AD4062_REG_INTERFACE_CONFIG_A, AD4062_REG_DEVICE_GRADE),\n+\tregmap_reg_range(AD4062_REG_SCRATCH_PAD, AD4062_REG_INTERFACE_STATUS),\n+\tregmap_reg_range(AD4062_REG_MODE_SET, AD4062_REG_ADC_IBI_EN),\n+\tregmap_reg_range(AD4062_REG_FUSE_CRC, AD4062_REG_IBI_STATUS),\n+\tregmap_reg_range(AD4062_REG_CONV_READ_LSB, AD4062_REG_CONV_AUTO),\n+};\n+\n+static const struct regmap_access_table ad4062_regmap_rd_table = {\n+\t.yes_ranges = ad4062_regmap_rd_ranges,\n+\t.n_yes_ranges = ARRAY_SIZE(ad4062_regmap_rd_ranges),\n+};\n+\n+static const struct regmap_range ad4062_regmap_wr_ranges[] = {\n+\tregmap_reg_range(AD4062_REG_INTERFACE_CONFIG_A, AD4062_REG_DEVICE_CONFIG),\n+\tregmap_reg_range(AD4062_REG_SCRATCH_PAD, AD4062_REG_SCRATCH_PAD),\n+\tregmap_reg_range(AD4062_REG_STREAM_MODE, AD4062_REG_INTERFACE_STATUS),\n+\tregmap_reg_range(AD4062_REG_MODE_SET, AD4062_REG_ADC_IBI_EN),\n+\tregmap_reg_range(AD4062_REG_FUSE_CRC, AD4062_REG_DEVICE_STATUS),\n+};\n+\n+static const struct regmap_access_table ad4062_regmap_wr_table = {\n+\t.yes_ranges = ad4062_regmap_wr_ranges,\n+\t.n_yes_ranges = ARRAY_SIZE(ad4062_regmap_wr_ranges),\n+};\n+\n+#define AD4062_CHAN {\t\t\t\t\t\t\t\t\t\\\n+\t.type = IIO_VOLTAGE,\t\t\t\t\t\t\t\t\\\n+\t.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_RAW) |\t\t\t\t\\\n+\t\t\t\t BIT(IIO_CHAN_INFO_SCALE) |\t\t\t\t\\\n+\t\t\t\t BIT(IIO_CHAN_INFO_CALIBSCALE) |\t\t\t\\\n+\t\t\t\t BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO),\t\t\\\n+\t.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),\t\t\t\\\n+\t.info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO),\t\\\n+\t.info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_SAMP_FREQ),\t\t\\\n+\t.indexed = 1,\t\t\t\t\t\t\t\t\t\\\n+\t.channel = 0,\t\t\t\t\t\t\t\t\t\\\n+}\n+\n+static const struct ad4062_chip_info ad4060_chip_info = {\n+\t.name = \"ad4060\",\n+\t.channels = { AD4062_CHAN },\n+\t.prod_id = AD4060_PROD_ID,\n+\t.avg_max = 256,\n+};\n+\n+static const struct ad4062_chip_info ad4062_chip_info = {\n+\t.name = \"ad4062\",\n+\t.channels = { AD4062_CHAN },\n+\t.prod_id = AD4062_PROD_ID,\n+\t.avg_max = 4096,\n+};\n+\n+static int ad4062_set_oversampling_ratio(struct ad4062_state *st, int val, int val2)\n+{\n+\tconst u32 _max = st->chip->avg_max;\n+\tconst u32 _min = 1;\n+\tint ret;\n+\n+\tif (!in_range(val, _min, _max) || val2 != 0)\n+\t\treturn -EINVAL;\n+\n+\t/* 1 disables oversampling */\n+\tval = ilog2(val);\n+\tif (val == 0) {\n+\t\tst->mode = AD4062_SAMPLE_MODE;\n+\t} else {\n+\t\tst->mode = AD4062_BURST_AVERAGING_MODE;\n+\t\tret = regmap_write(st->regmap, AD4062_REG_AVG_CONFIG, val - 1);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t}\n+\tst->oversamp_ratio = val;\n+\n+\treturn 0;\n+}\n+\n+static int ad4062_get_oversampling_ratio(struct ad4062_state *st, int *val)\n+{\n+\tint ret, buf;\n+\n+\tif (st->mode == AD4062_SAMPLE_MODE) {\n+\t\t*val = 1;\n+\t\treturn 0;\n+\t}\n+\n+\tret = regmap_read(st->regmap, AD4062_REG_AVG_CONFIG, &buf);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t*val = BIT(buf + 1);\n+\treturn 0;\n+}\n+\n+static int ad4062_calc_sampling_frequency(unsigned int fosc, unsigned int oversamp_ratio)\n+{\n+\t/* From datasheet p.31: (n_avg - 1)/fosc + tconv */\n+\tu32 n_avg = BIT(oversamp_ratio) - 1;\n+\tu32 period_ns = NSEC_PER_SEC / fosc;\n+\n+\t/* Result is less than 1 Hz */\n+\tif (n_avg >= fosc)\n+\t\treturn 1;\n+\n+\treturn NSEC_PER_SEC / (n_avg * period_ns + AD4062_TCONV_NS);\n+}\n+\n+static int ad4062_populate_sampling_frequency(struct ad4062_state *st)\n+{\n+\tfor (u8 i = 0; i < ARRAY_SIZE(ad4062_conversion_freqs); i++)\n+\t\tst->samp_freqs[i] =\n+\t\t\tad4062_calc_sampling_frequency(ad4062_conversion_freqs[i],\n+\t\t\t\t\t\t st->oversamp_ratio);\n+\treturn 0;\n+}\n+\n+static int ad4062_get_sampling_frequency(struct ad4062_state *st, int *val)\n+{\n+\tint freq = ad4062_conversion_freqs[st->sampling_frequency];\n+\n+\t*val = ad4062_calc_sampling_frequency(freq, st->oversamp_ratio);\n+\treturn IIO_VAL_INT;\n+}\n+\n+static int ad4062_set_sampling_frequency(struct ad4062_state *st, int val, int val2)\n+{\n+\tint ret;\n+\n+\tif (val2 != 0)\n+\t\treturn -EINVAL;\n+\n+\tret = ad4062_populate_sampling_frequency(st);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tst->sampling_frequency =\n+\t\tfind_closest_descending(val, st->samp_freqs,\n+\t\t\t\t\tARRAY_SIZE(ad4062_conversion_freqs));\n+\treturn 0;\n+}\n+\n+static int ad4062_check_ids(struct ad4062_state *st)\n+{\n+\tstruct device *dev = &st->i3cdev->dev;\n+\tint ret;\n+\tu16 val;\n+\n+\tret = regmap_bulk_read(st->regmap, AD4062_REG_PROD_ID_1,\n+\t\t\t &st->buf.be16, sizeof(st->buf.be16));\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tval = be16_to_cpu(st->buf.be16);\n+\tif (val != st->chip->prod_id)\n+\t\tdev_warn(dev, \"Production ID x%x does not match known values\", val);\n+\n+\tret = regmap_bulk_read(st->regmap, AD4062_REG_VENDOR_H,\n+\t\t\t &st->buf.be16, sizeof(st->buf.be16));\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tval = be16_to_cpu(st->buf.be16);\n+\tif (val != AD4062_I3C_VENDOR) {\n+\t\tdev_err(dev, \"Vendor ID x%x does not match expected value\\n\", val);\n+\t\treturn -ENODEV;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int ad4062_conversion_frequency_set(struct ad4062_state *st, u8 val)\n+{\n+\treturn regmap_write(st->regmap, AD4062_REG_TIMER_CONFIG,\n+\t\t\t FIELD_PREP(AD4062_REG_TIMER_CONFIG_FS_MASK, val));\n+}\n+\n+static int ad4062_set_operation_mode(struct ad4062_state *st,\n+\t\t\t\t enum ad4062_operation_mode mode)\n+{\n+\tint ret;\n+\n+\tret = ad4062_conversion_frequency_set(st, st->sampling_frequency);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = regmap_update_bits(st->regmap, AD4062_REG_ADC_MODES,\n+\t\t\t\t AD4062_REG_ADC_MODES_MODE_MSK, mode);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\treturn regmap_write(st->regmap, AD4062_REG_MODE_SET,\n+\t\t\t AD4062_REG_MODE_SET_ENTER_ADC);\n+}\n+\n+static int ad4062_soft_reset(struct ad4062_state *st)\n+{\n+\tu8 val = AD4062_SOFT_RESET;\n+\tint ret;\n+\n+\tret = regmap_write(st->regmap, AD4062_REG_INTERFACE_CONFIG_A, val);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/* Wait AD4062 treset time, datasheet p8 */\n+\tndelay(60);\n+\n+\treturn 0;\n+}\n+\n+static int ad4062_setup(struct iio_dev *indio_dev, struct iio_chan_spec const *chan,\n+\t\t\tconst bool *ref_sel)\n+{\n+\tstruct ad4062_state *st = iio_priv(indio_dev);\n+\tint ret;\n+\n+\tret = regmap_update_bits(st->regmap, AD4062_REG_GP_CONF,\n+\t\t\t\t AD4062_REG_GP_CONF_MODE_MSK_1,\n+\t\t\t\t FIELD_PREP(AD4062_REG_GP_CONF_MODE_MSK_1,\n+\t\t\t\t\t AD4062_GP_DRDY));\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = regmap_update_bits(st->regmap, AD4062_REG_ADC_CONFIG,\n+\t\t\t\t AD4062_REG_ADC_CONFIG_REF_EN_MSK,\n+\t\t\t\t FIELD_PREP(AD4062_REG_ADC_CONFIG_REF_EN_MSK,\n+\t\t\t\t\t *ref_sel));\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = regmap_write(st->regmap, AD4062_REG_DEVICE_STATUS,\n+\t\t\t AD4062_REG_DEVICE_STATUS_DEVICE_RESET);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = regmap_update_bits(st->regmap, AD4062_REG_INTR_CONF,\n+\t\t\t\t AD4062_REG_INTR_CONF_EN_MSK_1,\n+\t\t\t\t FIELD_PREP(AD4062_REG_INTR_CONF_EN_MSK_1,\n+\t\t\t\t\t AD4062_INTR_EN_NEITHER));\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tst->buf.be16 = cpu_to_be16(AD4062_MON_VAL_MIDDLE_POINT);\n+\treturn regmap_bulk_write(st->regmap, AD4062_REG_MON_VAL,\n+\t\t\t\t &st->buf.be16, sizeof(st->buf.be16));\n+}\n+\n+static irqreturn_t ad4062_irq_handler_drdy(int irq, void *private)\n+{\n+\tstruct iio_dev *indio_dev = private;\n+\tstruct ad4062_state *st = iio_priv(indio_dev);\n+\n+\tcomplete(&st->completion);\n+\n+\treturn IRQ_HANDLED;\n+}\n+\n+static void ad4062_ibi_handler(struct i3c_device *i3cdev,\n+\t\t\t const struct i3c_ibi_payload *payload)\n+{\n+\tstruct ad4062_state *st = i3cdev_get_drvdata(i3cdev);\n+\n+\tcomplete(&st->completion);\n+}\n+\n+static void ad4062_disable_ibi(void *data)\n+{\n+\tstruct i3c_device *i3cdev = data;\n+\n+\ti3c_device_disable_ibi(i3cdev);\n+}\n+\n+static void ad4062_free_ibi(void *data)\n+{\n+\tstruct i3c_device *i3cdev = data;\n+\n+\ti3c_device_free_ibi(i3cdev);\n+}\n+\n+static int ad4062_request_ibi(struct i3c_device *i3cdev)\n+{\n+\tconst struct i3c_ibi_setup ibireq = {\n+\t\t.max_payload_len = 1,\n+\t\t.num_slots = 1,\n+\t\t.handler = ad4062_ibi_handler,\n+\t};\n+\tint ret;\n+\n+\tret = i3c_device_request_ibi(i3cdev, &ibireq);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = devm_add_action_or_reset(&i3cdev->dev, ad4062_free_ibi, i3cdev);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = i3c_device_enable_ibi(i3cdev);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\treturn devm_add_action_or_reset(&i3cdev->dev, ad4062_disable_ibi, i3cdev);\n+}\n+\n+static int ad4062_request_irq(struct iio_dev *indio_dev)\n+{\n+\tstruct ad4062_state *st = iio_priv(indio_dev);\n+\tstruct device *dev = &st->i3cdev->dev;\n+\tint ret;\n+\n+\tret = fwnode_irq_get_byname(dev_fwnode(&st->i3cdev->dev), \"gp1\");\n+\tif (ret == -EPROBE_DEFER)\n+\t\treturn ret;\n+\n+\tif (ret < 0)\n+\t\treturn regmap_update_bits(st->regmap, AD4062_REG_ADC_IBI_EN,\n+\t\t\t\t\t AD4062_REG_ADC_IBI_EN_CONV_TRIGGER,\n+\t\t\t\t\t AD4062_REG_ADC_IBI_EN_CONV_TRIGGER);\n+\n+\treturn devm_request_threaded_irq(dev, ret,\n+\t\t\t\t\t ad4062_irq_handler_drdy,\n+\t\t\t\t\t NULL, IRQF_ONESHOT, indio_dev->name,\n+\t\t\t\t\t indio_dev);\n+}\n+\n+static const int ad4062_oversampling_avail[] = {\n+\t1, 2, 4, 8, 16, 32, 64, 128,\t\t/* 0 - 7 */\n+\t256, 512, 1024, 2048, 4096,\t\t/* 8 - 12 */\n+};\n+\n+static int ad4062_read_avail(struct iio_dev *indio_dev,\n+\t\t\t struct iio_chan_spec const *chan, const int **vals,\n+\t\t\t int *type, int *len, long mask)\n+{\n+\tstruct ad4062_state *st = iio_priv(indio_dev);\n+\tint ret;\n+\n+\tswitch (mask) {\n+\tcase IIO_CHAN_INFO_OVERSAMPLING_RATIO:\n+\t\t*vals = ad4062_oversampling_avail;\n+\t\t*len = ARRAY_SIZE(ad4062_oversampling_avail);\n+\t\t*len -= st->chip->avg_max == 256 ? 4 : 0;\n+\t\t*type = IIO_VAL_INT;\n+\n+\t\treturn IIO_AVAIL_LIST;\n+\tcase IIO_CHAN_INFO_SAMP_FREQ:\n+\t\tret = ad4062_populate_sampling_frequency(st);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t\t*vals = st->samp_freqs;\n+\t\t*len = st->oversamp_ratio ? ARRAY_SIZE(ad4062_conversion_freqs) : 1;\n+\t\t*type = IIO_VAL_INT;\n+\n+\t\treturn IIO_AVAIL_LIST;\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+}\n+\n+static int ad4062_get_chan_calibscale(struct ad4062_state *st, int *val, int *val2)\n+{\n+\tint ret;\n+\n+\tret = regmap_bulk_read(st->regmap, AD4062_REG_MON_VAL,\n+\t\t\t &st->buf.be16, sizeof(st->buf.be16));\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/* From datasheet: code out = code in × mon_val/0x8000 */\n+\t*val = be16_to_cpu(st->buf.be16) * 2;\n+\t*val2 = 16;\n+\n+\treturn IIO_VAL_FRACTIONAL_LOG2;\n+}\n+\n+static int ad4062_set_chan_calibscale(struct ad4062_state *st, int gain_int,\n+\t\t\t\t int gain_frac)\n+{\n+\t/* Divide numerator and denumerator by known great common divider */\n+\tconst u32 mon_val = AD4062_MON_VAL_MIDDLE_POINT / 64;\n+\tconst u32 micro = MICRO / 64;\n+\tconst u32 gain_fp = gain_int * MICRO + gain_frac;\n+\tconst u32 reg_val = DIV_ROUND_CLOSEST(gain_fp * mon_val, micro);\n+\tint ret;\n+\n+\t/* Checks if the gain is in range and the value fits the field */\n+\tif (gain_int < 0 || gain_int > 1 || reg_val > BIT(16) - 1)\n+\t\treturn -EINVAL;\n+\n+\tst->buf.be16 = cpu_to_be16(reg_val);\n+\tret = regmap_bulk_write(st->regmap, AD4062_REG_MON_VAL,\n+\t\t\t\t&st->buf.be16, sizeof(st->buf.be16));\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/* Enable scale if gain is not equal to one */\n+\treturn regmap_update_bits(st->regmap, AD4062_REG_ADC_CONFIG,\n+\t\t\t\t AD4062_REG_ADC_CONFIG_SCALE_EN_MSK,\n+\t\t\t\t FIELD_PREP(AD4062_REG_ADC_CONFIG_SCALE_EN_MSK,\n+\t\t\t\t\t !(gain_int == 1 && gain_frac == 0)));\n+}\n+\n+static int ad4062_read_chan_raw(struct ad4062_state *st, int *val)\n+{\n+\tstruct i3c_device *i3cdev = st->i3cdev;\n+\tstruct i3c_priv_xfer xfer_trigger = {\n+\t\t.data.out = &st->conv_addr,\n+\t\t.len = sizeof(st->conv_addr),\n+\t\t.rnw = false,\n+\t};\n+\tstruct i3c_priv_xfer xfer_sample = {\n+\t\t.data.in = &st->buf.be32,\n+\t\t.len = sizeof(st->buf.be32),\n+\t\t.rnw = true,\n+\t};\n+\tint ret;\n+\n+\tPM_RUNTIME_ACQUIRE(&st->i3cdev->dev, pm);\n+\tret = PM_RUNTIME_ACQUIRE_ERR(&pm);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = ad4062_set_operation_mode(st, st->mode);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\treinit_completion(&st->completion);\n+\t/* Change address pointer to trigger conversion */\n+\tst->conv_addr = AD4062_REG_CONV_TRIGGER_32BITS;\n+\tret = i3c_device_do_priv_xfers(i3cdev, &xfer_trigger, 1);\n+\tif (ret)\n+\t\treturn ret;\n+\t/*\n+\t * Single sample read should be used only for oversampling and\n+\t * sampling frequency pairs that take less than 1 sec.\n+\t */\n+\tret = wait_for_completion_timeout(&st->completion,\n+\t\t\t\t\t msecs_to_jiffies(1000));\n+\tif (!ret)\n+\t\treturn -ETIMEDOUT;\n+\n+\tret = i3c_device_do_priv_xfers(i3cdev, &xfer_sample, 1);\n+\tif (ret)\n+\t\treturn ret;\n+\t*val = be32_to_cpu(st->buf.be32);\n+\treturn 0;\n+}\n+\n+static int ad4062_read_raw_dispatch(struct ad4062_state *st,\n+\t\t\t\t int *val, int *val2, long info)\n+{\n+\tswitch (info) {\n+\tcase IIO_CHAN_INFO_RAW:\n+\t\treturn ad4062_read_chan_raw(st, val);\n+\n+\tcase IIO_CHAN_INFO_CALIBSCALE:\n+\t\treturn ad4062_get_chan_calibscale(st, val, val2);\n+\n+\tcase IIO_CHAN_INFO_OVERSAMPLING_RATIO:\n+\t\treturn ad4062_get_oversampling_ratio(st, val);\n+\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+}\n+\n+static int ad4062_read_raw(struct iio_dev *indio_dev,\n+\t\t\t struct iio_chan_spec const *chan,\n+\t\t\t int *val, int *val2, long info)\n+{\n+\tstruct ad4062_state *st = iio_priv(indio_dev);\n+\tint ret;\n+\n+\tswitch (info) {\n+\tcase IIO_CHAN_INFO_SAMP_FREQ:\n+\t\treturn ad4062_get_sampling_frequency(st, val);\n+\t}\n+\n+\tif (!iio_device_claim_direct(indio_dev))\n+\t\treturn -EBUSY;\n+\n+\tret = ad4062_read_raw_dispatch(st, val, val2, info);\n+\tiio_device_release_direct(indio_dev);\n+\treturn ret ?: IIO_VAL_INT;\n+}\n+\n+static int ad4062_write_raw_dispatch(struct ad4062_state *st, int val, int val2,\n+\t\t\t\t long info)\n+{\n+\tswitch (info) {\n+\tcase IIO_CHAN_INFO_OVERSAMPLING_RATIO:\n+\t\treturn ad4062_set_oversampling_ratio(st, val, val2);\n+\n+\tcase IIO_CHAN_INFO_CALIBSCALE:\n+\t\treturn ad4062_set_chan_calibscale(st, val, val2);\n+\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+};\n+\n+static int ad4062_write_raw(struct iio_dev *indio_dev,\n+\t\t\t struct iio_chan_spec const *chan, int val,\n+\t\t\t int val2, long info)\n+{\n+\tstruct ad4062_state *st = iio_priv(indio_dev);\n+\tint ret;\n+\n+\tswitch (info) {\n+\tcase IIO_CHAN_INFO_SAMP_FREQ:\n+\t\treturn ad4062_set_sampling_frequency(st, val, val2);\n+\t}\n+\n+\tif (!iio_device_claim_direct(indio_dev))\n+\t\treturn -EBUSY;\n+\n+\tret = ad4062_write_raw_dispatch(st, val, val2, info);\n+\n+\tiio_device_release_direct(indio_dev);\n+\treturn ret;\n+}\n+\n+static int ad4062_debugfs_reg_access(struct iio_dev *indio_dev, unsigned int reg,\n+\t\t\t\t unsigned int writeval, unsigned int *readval)\n+{\n+\tstruct ad4062_state *st = iio_priv(indio_dev);\n+\n+\tif (readval)\n+\t\treturn regmap_read(st->regmap, reg, readval);\n+\telse\n+\t\treturn regmap_write(st->regmap, reg, writeval);\n+}\n+\n+static const struct iio_info ad4062_info = {\n+\t.read_raw = ad4062_read_raw,\n+\t.write_raw = ad4062_write_raw,\n+\t.read_avail = ad4062_read_avail,\n+\t.debugfs_reg_access = ad4062_debugfs_reg_access,\n+};\n+\n+static const struct regmap_config ad4062_regmap_config = {\n+\t.name = \"ad4062\",\n+\t.reg_bits = 8,\n+\t.val_bits = 8,\n+\t.max_register = AD4062_MAX_REG,\n+\t.rd_table = &ad4062_regmap_rd_table,\n+\t.wr_table = &ad4062_regmap_wr_table,\n+\t.can_sleep = true,\n+};\n+\n+static int ad4062_regulators_get(struct ad4062_state *st, bool *ref_sel)\n+{\n+\tstruct device *dev = &st->i3cdev->dev;\n+\tint ret;\n+\n+\tret = devm_regulator_get_enable(dev, \"vio\");\n+\tif (ret)\n+\t\treturn dev_err_probe(dev, ret, \"Failed to enable vio voltage\\n\");\n+\n+\tst->vref_uV = devm_regulator_get_enable_read_voltage(dev, \"ref\");\n+\t*ref_sel = st->vref_uV == -ENODEV;\n+\tif (st->vref_uV < 0 && !*ref_sel)\n+\t\treturn dev_err_probe(dev, st->vref_uV,\n+\t\t\t\t \"Failed to enable and read ref voltage\\n\");\n+\n+\tif (*ref_sel) {\n+\t\tst->vref_uV = devm_regulator_get_enable_read_voltage(dev, \"vdd\");\n+\t\tif (st->vref_uV < 0)\n+\t\t\treturn dev_err_probe(dev, st->vref_uV,\n+\t\t\t\t\t \"Failed to enable and read vdd voltage\\n\");\n+\t} else {\n+\t\tret = devm_regulator_get_enable(dev, \"vdd\");\n+\t\tif (ret)\n+\t\t\treturn dev_err_probe(dev, ret,\n+\t\t\t\t\t \"Failed to enable vdd regulator\\n\");\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static const struct i3c_device_id ad4062_id_table[] = {\n+\tI3C_DEVICE(AD4062_I3C_VENDOR, AD4060_PROD_ID, &ad4060_chip_info),\n+\tI3C_DEVICE(AD4062_I3C_VENDOR, AD4062_PROD_ID, &ad4062_chip_info),\n+\t{ }\n+};\n+MODULE_DEVICE_TABLE(i3c, ad4062_id_table);\n+\n+static int ad4062_probe(struct i3c_device *i3cdev)\n+{\n+\tconst struct i3c_device_id *id = i3c_device_match_id(i3cdev, ad4062_id_table);\n+\tconst struct ad4062_chip_info *chip = id->data;\n+\tstruct device *dev = &i3cdev->dev;\n+\tstruct iio_dev *indio_dev;\n+\tstruct ad4062_state *st;\n+\tbool ref_sel;\n+\tint ret;\n+\n+\tindio_dev = devm_iio_device_alloc(dev, sizeof(*st));\n+\tif (!indio_dev)\n+\t\treturn -ENOMEM;\n+\n+\tst = iio_priv(indio_dev);\n+\tst->i3cdev = i3cdev;\n+\ti3cdev_set_drvdata(i3cdev, st);\n+\tinit_completion(&st->completion);\n+\n+\tret = ad4062_regulators_get(st, &ref_sel);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tst->regmap = devm_regmap_init_i3c(i3cdev, &ad4062_regmap_config);\n+\tif (IS_ERR(st->regmap))\n+\t\treturn dev_err_probe(dev, PTR_ERR(st->regmap),\n+\t\t\t\t \"Failed to initialize regmap\\n\");\n+\n+\tst->mode = AD4062_SAMPLE_MODE;\n+\tst->chip = chip;\n+\tst->sampling_frequency = 0;\n+\tst->oversamp_ratio = 0;\n+\tst->indio_dev = indio_dev;\n+\n+\tindio_dev->modes = INDIO_DIRECT_MODE;\n+\tindio_dev->num_channels = 1;\n+\tindio_dev->info = &ad4062_info;\n+\tindio_dev->name = chip->name;\n+\tindio_dev->channels = chip->channels;\n+\n+\tret = ad4062_soft_reset(st);\n+\tif (ret)\n+\t\treturn dev_err_probe(dev, ret, \"AD4062 failed to soft reset\\n\");\n+\n+\tret = ad4062_check_ids(st);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = ad4062_setup(indio_dev, indio_dev->channels, &ref_sel);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = ad4062_request_irq(indio_dev);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tpm_runtime_set_active(dev);\n+\tret = devm_pm_runtime_enable(dev);\n+\tif (ret)\n+\t\treturn dev_err_probe(dev, ret, \"Failed to enable pm_runtime\\n\");\n+\n+\tpm_runtime_set_autosuspend_delay(dev, 1000);\n+\tpm_runtime_use_autosuspend(dev);\n+\n+\tret = ad4062_request_ibi(i3cdev);\n+\tif (ret)\n+\t\treturn dev_err_probe(dev, ret, \"Failed to request i3c ibi\\n\");\n+\n+\treturn devm_iio_device_register(dev, indio_dev);\n+}\n+\n+static int ad4062_runtime_suspend(struct device *dev)\n+{\n+\tstruct ad4062_state *st = dev_get_drvdata(dev);\n+\n+\treturn regmap_write(st->regmap, AD4062_REG_DEVICE_CONFIG,\n+\t\t\t FIELD_PREP(AD4062_REG_DEVICE_CONFIG_POWER_MODE_MSK,\n+\t\t\t\t AD4062_REG_DEVICE_CONFIG_LOW_POWER_MODE));\n+}\n+\n+static int ad4062_runtime_resume(struct device *dev)\n+{\n+\tstruct ad4062_state *st = dev_get_drvdata(dev);\n+\tint ret;\n+\n+\tret = regmap_clear_bits(st->regmap, AD4062_REG_DEVICE_CONFIG,\n+\t\t\t\tAD4062_REG_DEVICE_CONFIG_POWER_MODE_MSK);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/* Wait device functional blocks to power up */\n+\tfsleep(3 * USEC_PER_MSEC);\n+\treturn 0;\n+}\n+\n+static DEFINE_RUNTIME_DEV_PM_OPS(ad4062_pm_ops,\n+\t\t\t\t ad4062_runtime_suspend, ad4062_runtime_resume, NULL);\n+\n+static struct i3c_driver ad4062_driver = {\n+\t.driver = {\n+\t\t.name = \"ad4062\",\n+\t\t.pm = pm_ptr(&ad4062_pm_ops),\n+\t},\n+\t.probe = ad4062_probe,\n+\t.id_table = ad4062_id_table,\n+};\n+module_i3c_driver(ad4062_driver);\n+\n+MODULE_AUTHOR(\"Jorge Marques <jorge.marques@analog.com>\");\n+MODULE_DESCRIPTION(\"Analog Devices AD4062\");\n+MODULE_LICENSE(\"GPL\");\n", "prefixes": [ "v4", "3/9" ] }