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GET /api/1.0/patches/2175102/?format=api
{ "id": 2175102, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2175102/?format=api", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/1.0/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20251217111510.138848-3-claudiu.beznea.uj@bp.renesas.com>", "date": "2025-12-17T11:15:10", "name": "[v2,2/2] PCI: rzg3s-host: Drop the lock on RZG3S_PCI_MSIRS and RZG3S_PCI_PINTRCVIS", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "5866feb1780fb28b51263e5b6cf23ebe9ee4610d", "submitter": { "id": 86830, "url": "http://patchwork.ozlabs.org/api/1.0/people/86830/?format=api", "name": "Claudiu Beznea", "email": "claudiu.beznea@tuxon.dev" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20251217111510.138848-3-claudiu.beznea.uj@bp.renesas.com/mbox/", "series": [ { "id": 485663, "url": "http://patchwork.ozlabs.org/api/1.0/series/485663/?format=api", "date": "2025-12-17T11:15:08", "name": "PCI: rzg3s-host: Cleanups", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/485663/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2175102/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-pci+bounces-43166-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n secure) header.d=tuxon.dev header.i=@tuxon.dev header.a=rsa-sha256\n header.s=google header.b=n3JLNqqS;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; helo=tor.lore.kernel.org;\n envelope-from=linux-pci+bounces-43166-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev\n header.b=\"n3JLNqqS\"", "smtp.subspace.kernel.org;\n arc=none smtp.client-ip=209.85.218.54", "smtp.subspace.kernel.org;\n dmarc=none (p=none dis=none) header.from=tuxon.dev", "smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=tuxon.dev" ], "Received": [ "from tor.lore.kernel.org (tor.lore.kernel.org\n [IPv6:2600:3c04:e001:36c::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4dWWSN5Wxtz1y0P\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 17 Dec 2025 22:15:48 +1100 (AEDT)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby tor.lore.kernel.org (Postfix) with ESMTP id C28A630329F1\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 17 Dec 2025 11:15:27 +0000 (UTC)", "from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 23FBD343D9D;\n\tWed, 17 Dec 2025 11:15:20 +0000 (UTC)", "from mail-ej1-f54.google.com (mail-ej1-f54.google.com\n [209.85.218.54])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id 2A6D033F8D6\n\tfor <linux-pci@vger.kernel.org>; Wed, 17 Dec 2025 11:15:17 +0000 (UTC)", "by mail-ej1-f54.google.com with SMTP id\n a640c23a62f3a-b73161849e1so1314925566b.2\n for <linux-pci@vger.kernel.org>; Wed, 17 Dec 2025 03:15:17 -0800 (PST)", "from claudiu-X670E-Pro-RS.. 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According to the RZ/G3S HW Manual, Rev. 1.10, chapter 34.2.1\nRegister Type, R/W1C register bits are cleared to 0b by writing 1b, while\nwriting 0b has no effect. Therefore, there is no need to take a lock\naround writes to these registers.\n\nDrop the locking.\n\nAlong with this, add a note about the R/W1C register type to the register\noffset definitions.\n\nSigned-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>\n---\n\nChanges in v2:\n- none\n\n drivers/pci/controller/pcie-rzg3s-host.c | 7 +++----\n 1 file changed, 3 insertions(+), 4 deletions(-)", "diff": "diff --git a/drivers/pci/controller/pcie-rzg3s-host.c b/drivers/pci/controller/pcie-rzg3s-host.c\nindex ae6d9c7dc2c1..5aa58638903f 100644\n--- a/drivers/pci/controller/pcie-rzg3s-host.c\n+++ b/drivers/pci/controller/pcie-rzg3s-host.c\n@@ -73,6 +73,7 @@\n #define RZG3S_PCI_PINTRCVIE_INTX(i)\t\tBIT(i)\n #define RZG3S_PCI_PINTRCVIE_MSI\t\t\tBIT(4)\n \n+/* Register is R/W1C, it doesn't require locking. */\n #define RZG3S_PCI_PINTRCVIS\t\t\t0x114\n #define RZG3S_PCI_PINTRCVIS_INTX(i)\t\tBIT(i)\n #define RZG3S_PCI_PINTRCVIS_MSI\t\t\tBIT(4)\n@@ -114,6 +115,8 @@\n #define RZG3S_PCI_MSIRE_ENA\t\t\tBIT(0)\n \n #define RZG3S_PCI_MSIRM(id)\t\t\t(0x608 + (id) * 0x10)\n+\n+/* Register is R/W1C, it doesn't require locking. */\n #define RZG3S_PCI_MSIRS(id)\t\t\t(0x60c + (id) * 0x10)\n \n #define RZG3S_PCI_AWBASEL(id)\t\t\t(0x1000 + (id) * 0x20)\n@@ -507,8 +510,6 @@ static void rzg3s_pcie_msi_irq_ack(struct irq_data *d)\n \tu8 reg_bit = d->hwirq % RZG3S_PCI_MSI_INT_PER_REG;\n \tu8 reg_id = d->hwirq / RZG3S_PCI_MSI_INT_PER_REG;\n \n-\tguard(raw_spinlock_irqsave)(&host->hw_lock);\n-\n \twritel_relaxed(BIT(reg_bit), host->axi + RZG3S_PCI_MSIRS(reg_id));\n }\n \n@@ -840,8 +841,6 @@ static void rzg3s_pcie_intx_irq_ack(struct irq_data *d)\n {\n \tstruct rzg3s_pcie_host *host = irq_data_get_irq_chip_data(d);\n \n-\tguard(raw_spinlock_irqsave)(&host->hw_lock);\n-\n \trzg3s_pcie_update_bits(host->axi, RZG3S_PCI_PINTRCVIS,\n \t\t\t RZG3S_PCI_PINTRCVIS_INTX(d->hwirq),\n \t\t\t RZG3S_PCI_PINTRCVIS_INTX(d->hwirq));\n", "prefixes": [ "v2", "2/2" ] }