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GET /api/1.0/patches/2175101/?format=api
{ "id": 2175101, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2175101/?format=api", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/1.0/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20251217111510.138848-2-claudiu.beznea.uj@bp.renesas.com>", "date": "2025-12-17T11:15:09", "name": "[v2,1/2] PCI: rzg3s-host: Use pci_generic_config_write() for the root bus", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "9c507fda179410e697e64c255d72fc17fbf457a7", "submitter": { "id": 86830, "url": "http://patchwork.ozlabs.org/api/1.0/people/86830/?format=api", "name": "Claudiu Beznea", "email": "claudiu.beznea@tuxon.dev" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20251217111510.138848-2-claudiu.beznea.uj@bp.renesas.com/mbox/", "series": [ { "id": 485663, "url": "http://patchwork.ozlabs.org/api/1.0/series/485663/?format=api", "date": "2025-12-17T11:15:08", "name": "PCI: rzg3s-host: Cleanups", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/485663/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2175101/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-pci+bounces-43165-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n secure) header.d=tuxon.dev header.i=@tuxon.dev header.a=rsa-sha256\n header.s=google header.b=l2bVoHxk;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c09:e001:a7::12fc:5321; helo=sto.lore.kernel.org;\n envelope-from=linux-pci+bounces-43165-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev\n header.b=\"l2bVoHxk\"", "smtp.subspace.kernel.org;\n arc=none smtp.client-ip=209.85.218.50", "smtp.subspace.kernel.org;\n dmarc=none (p=none dis=none) header.from=tuxon.dev", "smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=tuxon.dev" ], "Received": [ "from sto.lore.kernel.org (sto.lore.kernel.org\n [IPv6:2600:3c09:e001:a7::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4dWWRw58K1z1y3Z\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 17 Dec 2025 22:15:24 +1100 (AEDT)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sto.lore.kernel.org (Postfix) with ESMTP id 1CB543019E36\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 17 Dec 2025 11:15:22 +0000 (UTC)", "from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id DD55D33D6CE;\n\tWed, 17 Dec 2025 11:15:18 +0000 (UTC)", "from mail-ej1-f50.google.com (mail-ej1-f50.google.com\n [209.85.218.50])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id C4EDD33B955\n\tfor <linux-pci@vger.kernel.org>; Wed, 17 Dec 2025 11:15:16 +0000 (UTC)", "by mail-ej1-f50.google.com with SMTP id\n a640c23a62f3a-b79e7112398so1101919366b.3\n for <linux-pci@vger.kernel.org>; Wed, 17 Dec 2025 03:15:16 -0800 (PST)", "from claudiu-X670E-Pro-RS.. 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However, callers of struct pci_ops::write\nexpect the semantics defined by the PCIe specification, meaning that writes\nto read-only registers must not be allowed.\n\nThe previous custom struct pci_ops::write implementation for the root bus\ntemporarily enabled write access before calling pci_generic_config_write().\nThis breaks the expected semantics.\n\nRemove the custom implementation and simply use pci_generic_config_write().\n\nAlong with this change, the updates of the PCI_PRIMARY_BUS,\nPCI_SECONDARY_BUS, and PCI_SUBORDINATE_BUS registers were moved so that\nthey no longer depends on the RZG3S_PCI_PERM_CFG_HWINIT_EN bit in the\nRZG3S_PCI_PERM_CFG register, since these registers are R/W.\n\nFixes: 7ef502fb35b2 (\"PCI: Add Renesas RZ/G3S host controller driver\")\nSuggested-by: Bjorn Helgaas <helgaas@kernel.org>\nSigned-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>\n---\n\nChanges in v2:\n- added fixes tag\n\n drivers/pci/controller/pcie-rzg3s-host.c | 27 ++++--------------------\n 1 file changed, 4 insertions(+), 23 deletions(-)", "diff": "diff --git a/drivers/pci/controller/pcie-rzg3s-host.c b/drivers/pci/controller/pcie-rzg3s-host.c\nindex 83ec66a70823..ae6d9c7dc2c1 100644\n--- a/drivers/pci/controller/pcie-rzg3s-host.c\n+++ b/drivers/pci/controller/pcie-rzg3s-host.c\n@@ -439,28 +439,9 @@ static void __iomem *rzg3s_pcie_root_map_bus(struct pci_bus *bus,\n \treturn host->pcie + where;\n }\n \n-/* Serialized by 'pci_lock' */\n-static int rzg3s_pcie_root_write(struct pci_bus *bus, unsigned int devfn,\n-\t\t\t\t int where, int size, u32 val)\n-{\n-\tstruct rzg3s_pcie_host *host = bus->sysdata;\n-\tint ret;\n-\n-\t/* Enable access control to the CFGU */\n-\twritel_relaxed(RZG3S_PCI_PERM_CFG_HWINIT_EN,\n-\t\t host->axi + RZG3S_PCI_PERM);\n-\n-\tret = pci_generic_config_write(bus, devfn, where, size, val);\n-\n-\t/* Disable access control to the CFGU */\n-\twritel_relaxed(0, host->axi + RZG3S_PCI_PERM);\n-\n-\treturn ret;\n-}\n-\n static struct pci_ops rzg3s_pcie_root_ops = {\n \t.read\t\t= pci_generic_config_read,\n-\t.write\t\t= rzg3s_pcie_root_write,\n+\t.write\t\t= pci_generic_config_write,\n \t.map_bus\t= rzg3s_pcie_root_map_bus,\n };\n \n@@ -1065,14 +1046,14 @@ static int rzg3s_pcie_config_init(struct rzg3s_pcie_host *host)\n \twritel_relaxed(0xffffffff, host->pcie + RZG3S_PCI_CFG_BARMSK00L);\n \twritel_relaxed(0xffffffff, host->pcie + RZG3S_PCI_CFG_BARMSK00U);\n \n+\t/* Disable access control to the CFGU */\n+\twritel_relaxed(0, host->axi + RZG3S_PCI_PERM);\n+\n \t/* Update bus info */\n \twriteb_relaxed(primary_bus, host->pcie + PCI_PRIMARY_BUS);\n \twriteb_relaxed(secondary_bus, host->pcie + PCI_SECONDARY_BUS);\n \twriteb_relaxed(subordinate_bus, host->pcie + PCI_SUBORDINATE_BUS);\n \n-\t/* Disable access control to the CFGU */\n-\twritel_relaxed(0, host->axi + RZG3S_PCI_PERM);\n-\n \treturn 0;\n }\n \n", "prefixes": [ "v2", "1/2" ] }