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GET /api/1.0/patches/2175095/?format=api
{ "id": 2175095, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2175095/?format=api", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/1.0/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20251217-firmware_managed_ep-v3-2-ff871ba688fb@oss.qualcomm.com>", "date": "2025-12-17T10:12:46", "name": "[v3,2/2] PCI: qcom-ep: Add support for firmware-managed PCIe Endpoint", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "9de679acb3cebe212c3b571151ed1e0eef918755", "submitter": { "id": 90723, "url": "http://patchwork.ozlabs.org/api/1.0/people/90723/?format=api", "name": "Mrinmay Sarkar", "email": "mrinmay.sarkar@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20251217-firmware_managed_ep-v3-2-ff871ba688fb@oss.qualcomm.com/mbox/", "series": [ { "id": 485659, "url": "http://patchwork.ozlabs.org/api/1.0/series/485659/?format=api", "date": "2025-12-17T10:12:45", "name": "Add firmware-managed PCIe Endpoint support for SA8255P", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/485659/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2175095/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-pci+bounces-43161-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=igW2HQdU;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=Vy4u+CHy;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; 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charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20251217-firmware_managed_ep-v3-2-ff871ba688fb@oss.qualcomm.com>", "References": "<20251217-firmware_managed_ep-v3-0-ff871ba688fb@oss.qualcomm.com>", "In-Reply-To": "<20251217-firmware_managed_ep-v3-0-ff871ba688fb@oss.qualcomm.com>", "To": "Bjorn Helgaas <bhelgaas@google.com>,\n Lorenzo Pieralisi <lpieralisi@kernel.org>, =?utf-8?q?Krzysztof_Wilczy=C5=84?=\n\t=?utf-8?q?ski?= <kwilczynski@kernel.org>,\n Manivannan Sadhasivam <mani@kernel.org>, Rob Herring <robh@kernel.org>,\n Krzysztof Kozlowski <krzk+dt@kernel.org>, Conor Dooley <conor+dt@kernel.org>,\n Philipp Zabel <p.zabel@pengutronix.de>,\n Bjorn Andersson <andersson@kernel.org>", "Cc": "linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org,\n devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>,\n Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>,\n quic_vbadigan@quicinc.com, quic_shazhuss@quicinc.com,\n konrad.dybcio@oss.qualcomm.com,\n Mrinmay sarkar <mrinmay.sarkar@oss.qualcomm.com>,\n Rama Krishna <quic_ramkri@quicinc.com>,\n Ayiluri Naga Rashmi <quic_nayiluri@quicinc.com>,\n Nitesh Gupta <quic_nitegupt@quicinc.com>", "X-Mailer": "b4 0.14.2", "X-Developer-Signature": "v=1; a=ed25519-sha256; t=1765966367; l=5973;\n i=mrinmay.sarkar@oss.qualcomm.com; s=20250423; h=from:subject:message-id;\n bh=Fyphgpm9oWKQhl4y6fHTvk81D6ocscTgp2cQazg94DE=;\n b=OFGYAIvri6Zs4REOgRs745u+v9BLBtpIFNaodmrNm3Q3TuXb6/VrXfkrW+4awv5TnQRnnsxdt\n LH06T9egqRnAmWxHOTOnM+jFO/fVLssAJzodkUMjjyLl7MFVuB7pql+", "X-Developer-Key": "i=mrinmay.sarkar@oss.qualcomm.com; a=ed25519;\n pk=5D8s0BEkJAotPyAnJ6/qmJBFhCjti/zUi2OMYoferv4=", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjUxMjE3MDA4MSBTYWx0ZWRfX5i+4FleWLUO2\n GdVsSu7FA+dOx/HK+cRzf5umVQLglMBWERLmKErKWpaW0CayEBXIMAr84/wX3RtpQgS+Rs0VbSU\n zxD29lTGvPEVm0CMiVFlm3Ep/O6sxmBDbhvGVNNufoQ24cXben0ClVPAon0+tuFsfN4OzPU2PA5\n WR+2OiJYr/nEy36qZw6xxoQFAxjXPf1bR0M2d6/0FxQJdVWPeVy4N2h04Oc8IU/fTVAoG45f+Qo\n 7Ql+L3p+OICxHlIqK3ACN2OYS1LxGUVsELIRQfg/SNChc+/Srzbd0QkngJdTqyBFzhRaqJD2UPg\n U8EE/0fpKgqc1C+qKWFeGtyLvFrXLNq+T3A5oH9P/EXb1ycnfvfAmcoO4UVxYDMMYoTr/CQSYSz\n Q6mMTKNyMYcWyFHQQgMg/GAyBDHphw==", "X-Proofpoint-GUID": "GqWcDZylrCJ6hNBfdDftmD93v-4DVJ3o", "X-Authority-Analysis": "v=2.4 cv=Fcw6BZ+6 c=1 sm=1 tr=0 ts=69428233 cx=c_pps\n a=rEQLjTOiSrHUhVqRoksmgQ==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17\n a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10\n a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=2tdM-IJ1x2Ue4swjlzoA:9\n a=QEXdDO2ut3YA:10 a=2VI0MkxyNR6bbpdq8BZq:22", "X-Proofpoint-ORIG-GUID": "GqWcDZylrCJ6hNBfdDftmD93v-4DVJ3o", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49\n definitions=2025-12-17_01,2025-12-16_05,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n lowpriorityscore=0 clxscore=1015 malwarescore=0 spamscore=0 suspectscore=0\n impostorscore=0 priorityscore=1501 phishscore=0 bulkscore=0 adultscore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2512170081" }, "content": "Some Qualcomm platforms use firmware to manage PCIe resources such as\nclocks, resets, and PHY through the SCMI interface. In these cases,\nthe Linux driver should not perform resource enable or disable\noperations directly. Additionally, runtime PM support has been enabled\nto ensure proper power state transitions.\n\nThis commit introduces a `firmware_managed` flag in the Endpoint\nconfiguration structure. When set, the driver skips resource handling\nand uses generic runtime PM calls to let firmware do resource management.\n\nA new compatible string is added for SA8255P platforms where firmware\nmanages resources.\n\nSigned-off-by: Mrinmay Sarkar <mrinmay.sarkar@oss.qualcomm.com>\n---\n drivers/pci/controller/dwc/pcie-qcom-ep.c | 82 +++++++++++++++++++++++--------\n 1 file changed, 62 insertions(+), 20 deletions(-)", "diff": "diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c\nindex f1bc0ac81a928b928ab3f8cc7bf82558fc430474..2de8b48511169a9c836828c22860dba45f6c9db8 100644\n--- a/drivers/pci/controller/dwc/pcie-qcom-ep.c\n+++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c\n@@ -168,11 +168,13 @@ enum qcom_pcie_ep_link_status {\n * @hdma_support: HDMA support on this SoC\n * @override_no_snoop: Override NO_SNOOP attribute in TLP to enable cache snooping\n * @disable_mhi_ram_parity_check: Disable MHI RAM data parity error check\n+ * @firmware_managed: Set if the Endpoint controller is firmware managed\n */\n struct qcom_pcie_ep_cfg {\n \tbool hdma_support;\n \tbool override_no_snoop;\n \tbool disable_mhi_ram_parity_check;\n+\tbool firmware_managed;\n };\n \n /**\n@@ -377,10 +379,17 @@ static int qcom_pcie_enable_resources(struct qcom_pcie_ep *pcie_ep)\n \n static void qcom_pcie_disable_resources(struct qcom_pcie_ep *pcie_ep)\n {\n-\ticc_set_bw(pcie_ep->icc_mem, 0, 0);\n-\tphy_power_off(pcie_ep->phy);\n-\tphy_exit(pcie_ep->phy);\n-\tclk_bulk_disable_unprepare(pcie_ep->num_clks, pcie_ep->clks);\n+\tstruct device *dev = pcie_ep->pci.dev;\n+\tint ret;\n+\n+\tpm_runtime_put(dev);\n+\n+\tif (!(pcie_ep->cfg && pcie_ep->cfg->firmware_managed)) {\n+\t\ticc_set_bw(pcie_ep->icc_mem, 0, 0);\n+\t\tphy_power_off(pcie_ep->phy);\n+\t\tphy_exit(pcie_ep->phy);\n+\t\tclk_bulk_disable_unprepare(pcie_ep->num_clks, pcie_ep->clks);\n+\t}\n }\n \n static int qcom_pcie_perst_deassert(struct dw_pcie *pci)\n@@ -390,12 +399,22 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *pci)\n \tu32 val, offset;\n \tint ret;\n \n-\tret = qcom_pcie_enable_resources(pcie_ep);\n-\tif (ret) {\n-\t\tdev_err(dev, \"Failed to enable resources: %d\\n\", ret);\n+\tret = pm_runtime_resume_and_get(dev);\n+\tif (ret < 0) {\n+\t\tdev_err(dev, \"Failed to enable endpoint device: %d\\n\", ret);\n \t\treturn ret;\n \t}\n \n+\t/* Enable resources if Endpoint controller is not firmware-managed */\n+\tif (!(pcie_ep->cfg && pcie_ep->cfg->firmware_managed)) {\n+\t\tret = qcom_pcie_enable_resources(pcie_ep);\n+\t\tif (ret) {\n+\t\t\tdev_err(dev, \"Failed to enable resources: %d\\n\", ret);\n+\t\t\tpm_runtime_put(dev);\n+\t\t\treturn ret;\n+\t\t}\n+\t}\n+\n \t/* Perform cleanup that requires refclk */\n \tpci_epc_deinit_notify(pci->ep.epc);\n \tdw_pcie_ep_cleanup(&pci->ep);\n@@ -630,16 +649,6 @@ static int qcom_pcie_ep_get_resources(struct platform_device *pdev,\n \t\treturn ret;\n \t}\n \n-\tpcie_ep->num_clks = devm_clk_bulk_get_all(dev, &pcie_ep->clks);\n-\tif (pcie_ep->num_clks < 0) {\n-\t\tdev_err(dev, \"Failed to get clocks\\n\");\n-\t\treturn pcie_ep->num_clks;\n-\t}\n-\n-\tpcie_ep->core_reset = devm_reset_control_get_exclusive(dev, \"core\");\n-\tif (IS_ERR(pcie_ep->core_reset))\n-\t\treturn PTR_ERR(pcie_ep->core_reset);\n-\n \tpcie_ep->reset = devm_gpiod_get(dev, \"reset\", GPIOD_IN);\n \tif (IS_ERR(pcie_ep->reset))\n \t\treturn PTR_ERR(pcie_ep->reset);\n@@ -652,9 +661,22 @@ static int qcom_pcie_ep_get_resources(struct platform_device *pdev,\n \tif (IS_ERR(pcie_ep->phy))\n \t\tret = PTR_ERR(pcie_ep->phy);\n \n-\tpcie_ep->icc_mem = devm_of_icc_get(dev, \"pcie-mem\");\n-\tif (IS_ERR(pcie_ep->icc_mem))\n-\t\tret = PTR_ERR(pcie_ep->icc_mem);\n+\t/* Populate resources if Endpoint controller is not firmware-managed */\n+\tif (!(pcie_ep->cfg && pcie_ep->cfg->firmware_managed)) {\n+\t\tpcie_ep->num_clks = devm_clk_bulk_get_all(dev, &pcie_ep->clks);\n+\t\tif (pcie_ep->num_clks < 0) {\n+\t\t\tdev_err(dev, \"Failed to get clocks\\n\");\n+\t\t\treturn pcie_ep->num_clks;\n+\t\t}\n+\n+\t\tpcie_ep->core_reset = devm_reset_control_get_exclusive(dev, \"core\");\n+\t\tif (IS_ERR(pcie_ep->core_reset))\n+\t\t\treturn PTR_ERR(pcie_ep->core_reset);\n+\n+\t\tpcie_ep->icc_mem = devm_of_icc_get(dev, \"pcie-mem\");\n+\t\tif (IS_ERR(pcie_ep->icc_mem))\n+\t\t\tret = PTR_ERR(pcie_ep->icc_mem);\n+\t}\n \n \treturn ret;\n }\n@@ -874,6 +896,12 @@ static int qcom_pcie_ep_probe(struct platform_device *pdev)\n \n \tplatform_set_drvdata(pdev, pcie_ep);\n \n+\tpm_runtime_get_noresume(dev);\n+\tpm_runtime_set_active(dev);\n+\tret = devm_pm_runtime_enable(dev);\n+\tif (ret)\n+\t\treturn ret;\n+\n \tret = qcom_pcie_ep_get_resources(pdev, pcie_ep);\n \tif (ret)\n \t\treturn ret;\n@@ -894,6 +922,12 @@ static int qcom_pcie_ep_probe(struct platform_device *pdev)\n \t\tgoto err_disable_irqs;\n \t}\n \n+\tret = pm_runtime_put_sync(dev);\n+\tif (ret < 0) {\n+\t\tdev_err(dev, \"Failed to disable endpoint device: %d\\n\", ret);\n+\t\tgoto err_disable_irqs;\n+\t}\n+\n \tpcie_ep->debugfs = debugfs_create_dir(name, NULL);\n \tqcom_pcie_ep_init_debugfs(pcie_ep);\n \n@@ -930,7 +964,15 @@ static const struct qcom_pcie_ep_cfg cfg_1_34_0 = {\n \t.disable_mhi_ram_parity_check = true,\n };\n \n+static const struct qcom_pcie_ep_cfg cfg_1_34_0_fw_managed = {\n+\t.hdma_support = true,\n+\t.override_no_snoop = true,\n+\t.disable_mhi_ram_parity_check = true,\n+\t.firmware_managed = true,\n+};\n+\n static const struct of_device_id qcom_pcie_ep_match[] = {\n+\t{ .compatible = \"qcom,pcie-ep-sa8255p\", .data = &cfg_1_34_0_fw_managed},\n \t{ .compatible = \"qcom,sa8775p-pcie-ep\", .data = &cfg_1_34_0},\n \t{ .compatible = \"qcom,sdx55-pcie-ep\", },\n \t{ .compatible = \"qcom,sm8450-pcie-ep\", },\n", "prefixes": [ "v3", "2/2" ] }