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GET /api/1.0/patches/2175093/?format=api
{ "id": 2175093, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2175093/?format=api", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/1.0/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20251217-firmware_managed_ep-v3-1-ff871ba688fb@oss.qualcomm.com>", "date": "2025-12-17T10:12:45", "name": "[v3,1/2] dt-bindings: PCI: qcom,pcie-ep-sa8255p: Document firmware managed PCIe endpoint", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "f66a456f0f27494aec5135c193189c895d5c4871", "submitter": { "id": 90723, "url": "http://patchwork.ozlabs.org/api/1.0/people/90723/?format=api", "name": "Mrinmay Sarkar", "email": "mrinmay.sarkar@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20251217-firmware_managed_ep-v3-1-ff871ba688fb@oss.qualcomm.com/mbox/", "series": [ { "id": 485659, "url": "http://patchwork.ozlabs.org/api/1.0/series/485659/?format=api", "date": "2025-12-17T10:12:45", "name": "Add firmware-managed PCIe Endpoint support for SA8255P", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/485659/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2175093/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-pci+bounces-43160-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=OSWqEKgK;\n\tdkim=pass (2048-bit key;\n unprotected) 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1/2] dt-bindings: PCI: qcom,pcie-ep-sa8255p: Document\n firmware managed PCIe endpoint", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20251217-firmware_managed_ep-v3-1-ff871ba688fb@oss.qualcomm.com>", "References": "<20251217-firmware_managed_ep-v3-0-ff871ba688fb@oss.qualcomm.com>", "In-Reply-To": "<20251217-firmware_managed_ep-v3-0-ff871ba688fb@oss.qualcomm.com>", "To": "Bjorn Helgaas <bhelgaas@google.com>,\n Lorenzo Pieralisi <lpieralisi@kernel.org>, =?utf-8?q?Krzysztof_Wilczy=C5=84?=\n\t=?utf-8?q?ski?= <kwilczynski@kernel.org>,\n Manivannan Sadhasivam <mani@kernel.org>, Rob Herring <robh@kernel.org>,\n Krzysztof Kozlowski <krzk+dt@kernel.org>, Conor Dooley <conor+dt@kernel.org>,\n Philipp Zabel <p.zabel@pengutronix.de>,\n Bjorn Andersson <andersson@kernel.org>", "Cc": "linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org,\n devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>,\n Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>,\n quic_vbadigan@quicinc.com, quic_shazhuss@quicinc.com,\n konrad.dybcio@oss.qualcomm.com,\n Mrinmay sarkar <mrinmay.sarkar@oss.qualcomm.com>,\n Rama Krishna <quic_ramkri@quicinc.com>,\n Ayiluri Naga Rashmi <quic_nayiluri@quicinc.com>,\n Nitesh Gupta <quic_nitegupt@quicinc.com>", "X-Mailer": "b4 0.14.2", "X-Developer-Signature": "v=1; a=ed25519-sha256; t=1765966367; l=3868;\n i=mrinmay.sarkar@oss.qualcomm.com; s=20250423; h=from:subject:message-id;\n bh=Gd8++hP+sEHWvYF85wgfzJz3jZqyJIvpMUapV4m5Pxo=;\n b=16hMd/OgLFc5yC/RDd40+Kanmwb7nY0dMrvfkKkHnIa3sa0fbZqjWPRYMqCq60yhc9r6aAch/\n PDcC3wol11vDPpq2pd58hbeI8lPfYOTvxCLiyTC6YKsJ/9Bu3ZkaTJx", "X-Developer-Key": "i=mrinmay.sarkar@oss.qualcomm.com; a=ed25519;\n pk=5D8s0BEkJAotPyAnJ6/qmJBFhCjti/zUi2OMYoferv4=", "X-Proofpoint-ORIG-GUID": "7Ly5RBhNUTnapLqCgw1JesHSX7mKF33V", "X-Authority-Analysis": "v=2.4 cv=ALq93nRn c=1 sm=1 tr=0 ts=6942822d cx=c_pps\n a=WW5sKcV1LcKqjgzy2JUPuA==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17\n a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10\n a=VkNPw1HP01LnGYTKEx00:22 a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=VwQbUJbxAAAA:8\n a=avnAaoOVoNrTWVjlPhgA:9 a=QEXdDO2ut3YA:10 a=OpyuDcXvxspvyRM73sMx:22\n a=sptkURWiP4Gy88Gu7hUp:22", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjUxMjE3MDA4MSBTYWx0ZWRfX/cEAT2UD7+H7\n nExS5I6Sbxk8dpkfocl/PCBcdpH4u3yIJUMpzDpxvUopT9nZVzy9o75XcBqQVm2tPicktGcgPV1\n EAyO/JorJopv9HFM8/lFGZEU+g0x64UBXjZGsgpAmaIjCz2JSnXrDvdTlYIu7pimPgxr1XsiIoS\n 5z/uhMgyr/Lc+fZ5LC4pGJ/mtJmkv+YnzMe6dUe2uODYfi64DRtYDQYblAxEzb/+fBDyd5+9VFl\n 5pOKgyo9DPlPX+3z5U3fyJrjbGyzZHuy3w/DGXdeUV3Z4qsxzhA6KA09ih98mdpnMRFj1anWAWJ\n nNFi9IcAazGXO315VnNBiqJjM7eCWYueURjyQ6aYLmoVnh3fa0VWohEc0VjA9To72/jGEQlrX1w\n 65gL5agxjHD6im+iO2hRJjB5nQAX8Q==", "X-Proofpoint-GUID": "7Ly5RBhNUTnapLqCgw1JesHSX7mKF33V", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49\n definitions=2025-12-17_01,2025-12-16_05,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n lowpriorityscore=0 clxscore=1015 priorityscore=1501 malwarescore=0\n suspectscore=0 phishscore=0 impostorscore=0 spamscore=0 adultscore=0\n bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound\n adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001\n definitions=main-2512170081" }, "content": "Document the required configuration to enable the PCIe Endpoint controller\non SA8255p which is managed by firmware using power-domain based handling.\n\nSigned-off-by: Mrinmay Sarkar <mrinmay.sarkar@oss.qualcomm.com>\n---\n .../bindings/pci/qcom,pcie-ep-sa8255p.yaml | 110 +++++++++++++++++++++\n 1 file changed, 110 insertions(+)", "diff": "diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep-sa8255p.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep-sa8255p.yaml\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..395cd23861ec26c00d51299829f1c60116293cae\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep-sa8255p.yaml\n@@ -0,0 +1,110 @@\n+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/pci/qcom,pcie-ep-sa8255p.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: Qualcomm firmware managed PCIe Endpoint Controller\n+\n+description:\n+ Qualcomm SA8255p SoC PCIe endpoint controller is based on the Synopsys\n+ DesignWare PCIe IP which is managed by firmware.\n+\n+maintainers:\n+ - Manivannan Sadhasivam <mani@kernel.org>\n+\n+properties:\n+ compatible:\n+ const: qcom,pcie-ep-sa8255p\n+\n+ reg:\n+ items:\n+ - description: Qualcomm-specific PARF configuration registers\n+ - description: DesignWare PCIe registers\n+ - description: External local bus interface registers\n+ - description: Address Translation Unit (ATU) registers\n+ - description: Memory region used to map remote RC address space\n+ - description: BAR memory region\n+ - description: DMA register space\n+\n+ reg-names:\n+ items:\n+ - const: parf\n+ - const: dbi\n+ - const: elbi\n+ - const: atu\n+ - const: addr_space\n+ - const: mmio\n+ - const: dma\n+\n+ interrupts:\n+ items:\n+ - description: PCIe Global interrupt\n+ - description: PCIe Doorbell interrupt\n+ - description: DMA interrupt\n+\n+ interrupt-names:\n+ items:\n+ - const: global\n+ - const: doorbell\n+ - const: dma\n+\n+ iommus:\n+ maxItems: 1\n+\n+ reset-gpios:\n+ description: GPIO used as PERST# input signal\n+ maxItems: 1\n+\n+ wake-gpios:\n+ description: GPIO used as WAKE# output signal\n+ maxItems: 1\n+\n+ power-domains:\n+ maxItems: 1\n+\n+ dma-coherent: true\n+\n+ num-lanes:\n+ default: 2\n+\n+required:\n+ - compatible\n+ - reg\n+ - reg-names\n+ - interrupts\n+ - interrupt-names\n+ - reset-gpios\n+ - power-domains\n+\n+additionalProperties: false\n+\n+examples:\n+ - |\n+ #include <dt-bindings/gpio/gpio.h>\n+ #include <dt-bindings/interrupt-controller/arm-gic.h>\n+ soc {\n+ #address-cells = <2>;\n+ #size-cells = <2>;\n+ pcie1_ep: pcie-ep@1c10000 {\n+ compatible = \"qcom,pcie-ep-sa8255p\";\n+ reg = <0x0 0x01c10000 0x0 0x3000>,\n+ <0x0 0x60000000 0x0 0xf20>,\n+ <0x0 0x60000f20 0x0 0xa8>,\n+ <0x0 0x60001000 0x0 0x4000>,\n+ <0x0 0x60200000 0x0 0x100000>,\n+ <0x0 0x01c13000 0x0 0x1000>,\n+ <0x0 0x60005000 0x0 0x2000>;\n+ reg-names = \"parf\", \"dbi\", \"elbi\", \"atu\", \"addr_space\", \"mmio\", \"dma\";\n+ interrupts = <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>,\n+ <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,\n+ <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;\n+ interrupt-names = \"global\", \"doorbell\", \"dma\";\n+ reset-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>;\n+ wake-gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;\n+ dma-coherent;\n+ iommus = <&pcie_smmu 0x80 0x7f>;\n+ power-domains = <&scmi6_pd 1>;\n+ num-lanes = <4>;\n+ };\n+ };\n", "prefixes": [ "v3", "1/2" ] }