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{ "id": 2218694, "url": "http://patchwork.ozlabs.org/api/1.0/covers/2218694/?format=api", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.0/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260401170454.32045-1-yodel.eldar@yodel.dev>", "date": "2026-04-01T17:04:50", "name": "[RFC,0/4] alpha: Decouple the CPU and Typhoon", "submitter": { "id": 92094, "url": "http://patchwork.ozlabs.org/api/1.0/people/92094/?format=api", "name": "Yodel Eldar", "email": "yodel.eldar@yodel.dev" }, "series": [ { "id": 498370, "url": "http://patchwork.ozlabs.org/api/1.0/series/498370/?format=api", "date": "2026-04-01T17:04:50", "name": "alpha: Decouple the CPU and Typhoon", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/498370/mbox/" } ], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n secure) header.d=yodel.dev header.i=@yodel.dev header.a=rsa-sha256\n header.s=rsa2048 header.b=rLN1OckE;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fmBFj5LKdz1yCp\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 02 Apr 2026 04:05:45 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w7z0K-0000st-2V; Wed, 01 Apr 2026 13:05:20 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1)\n (envelope-from <bounce+0e9322.97607e-qemu-devel=nongnu.org@yodel.dev>)\n id 1w7z0B-0000qJ-Mj\n for qemu-devel@nongnu.org; Wed, 01 Apr 2026 13:05:13 -0400", "from v58.v5f06b487.use4.send.mailgun.net ([143.55.232.8])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1)\n (envelope-from <bounce+0e9322.97607e-qemu-devel=nongnu.org@yodel.dev>)\n id 1w7z07-0007sn-A5\n for qemu-devel@nongnu.org; Wed, 01 Apr 2026 13:05:09 -0400", "from mail.yodel.dev (mail.yodel.dev [35.209.39.246]) by\n 5d20a6721737762833a40a9df825c1bee86552a784de2890dbfe1bc9d278649b with SMTP id\n 69cd50393b2d605dcd0588d7; Wed, 01 Apr 2026 17:04:57 GMT" ], "X-Mailgun-Sid": "WyI4ZDFlNiIsInFlbXUtZGV2ZWxAbm9uZ251Lm9yZyIsIjk3NjA3ZSJd", "X-Mailgun-Sending-Ip": "143.55.232.8", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=yodel.dev;\n s=rsa2048; t=1775063097;\n bh=OeuhLFtteNMRcBIXpROU188ni1FerINUPvDH+maOmp0=;\n h=X-Mailgun-Dkim:From:To:Cc:Subject:Date:Message-ID:MIME-Version:\n Content-Type:Content-Transfer-Encoding:From:Reply-to:Subject:Date:\n Message-id:To:Cc:Mime-version:Content-type:\n Content-transfer-encoding:In-reply-to:References;\n b=rLN1OckE8WB22RFntKqJYqwXfHWamXOoxG9VQD730JAZAIv55zIKTC2VzFv9NZHgu\n KzHM+YmNd/uoFhyX4BJ3pf6reaNZslZLE6hEj3WAmI7VcI9qDvNUI38H4zCnguXX85\n QIJdr1EeqxCJQNlZacuub735yPvwagkd4F3OMmpBaj+SPtibUmaCrYCF8u/Egpzdo6\n 4cHcnEcaoFB18mJ+GG26NlpbWsD1jFNhr319kD3zNwnneS7Aa7xrjdfJGD8iQa0Ozk\n ZmsA+ibn6xj2NuKDtbkeD3pE/vNLvs6LuxnYedNYid0iMHXWRirQIwPhM7SVfW0RYN\n 4COKiKKqqnScQ==", "X-Mailgun-Dkim": [ "no", "no" ], "From": "\"Yodel Eldar\" <yodel.eldar@yodel.dev>", "To": "qemu-devel@nongnu.org", "Cc": "Richard Henderson <richard.henderson@linaro.org>, =?utf-8?q?Philippe_Mat?=\n\t=?utf-8?q?hieu-Daud=C3=A9?= <philmd@linaro.org>,\n Yodel Eldar <yodel.eldar@yodel.dev>", "Subject": "[RFC PATCH 0/4] alpha: Decouple the CPU and Typhoon", "Date": "Wed, 1 Apr 2026 12:04:50 -0500", "Message-ID": "<20260401170454.32045-1-yodel.eldar@yodel.dev>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=143.55.232.8;\n envelope-from=bounce+0e9322.97607e-qemu-devel=nongnu.org@yodel.dev;\n helo=v58.v5f06b487.use4.send.mailgun.net", "X-Spam_score_int": "0", "X-Spam_score": "-0.1", "X-Spam_bar": "/", "X-Spam_report": "(-0.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n HELO_STATIC_HOST=-0.001, RCVD_IN_DNSWL_NONE=-0.0001,\n RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=1, RCVD_IN_VALIDITY_RPBL_BLOCKED=1,\n SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Yodel Eldar <yodel.eldar@yodel.dev>\n\nHi,\n\nThis series is intended as a leg of a re-spin of the\n\"QOMify Clipper and Typhoon\" series [1]. There, thanks to\na suggestion by Philippe, we decided to decouple the Alpha\nCPU from the Typhoon chipset to improve the machine model.\n\nCurrently, the CPU owns a QEMUTimer and its state owns the\nalarm expiration of that alarm timer. Modification of the\ntimer is triggered via a QEMU-specific synthetic processor\nregister in PALcode by changing the expiration value through\nthe side effect invocation of a TCG helper function,\nhelper_set_alarm(). Meanwhile, the timer alarm callback is\ndefined in the Typhoon chipset, so the creation of the timer\noccurs during the realization of the chipset; thus, the\ntyphoon must have access to CPU internals in violation of\nencapsulation and architectural accuracy. Instead, as\nPhilippe pointed out, the chipset should just communicate\nwith the CPU through an IRQ line wired by the board.\n\nThis series does that by removing the timer out of the CPU\nand into the chipset. The alarm expiration now resides in\nan QEMU-specific (non-standard) Cchip MMIO register at\noffset 0x7c0 as implemented in the PALcode binary. The\nlogic as to what happens when alarm expiration is modified\nremains the same as before, but now we don't need the TCG\nhelper function or the magic process register that triggers\nits invocation.\n\nI'm submitting this series primarily to get feedback on\nthe third and fourth patches, because it blurs the line\nof a refactor and a functional change; moreover, it\nnecessitates a change in an external dependency\n(qemu-palcode), so I'm particularly interested in Richard's\n(its owner) opinion on the shift from a synthetic processor\nregister to a vendor-specific MMIO register.\n\nIf we agree to take this route, as mentioned earlier, this\nseries will be folded into the QOMification series that\nmotivated it.\n\nPatch 4 contains the modified palcode-clipper binary so\nthat testers would not need to build it themselves, but\nmy intent is to submit a PR to the qemu-palcode repo. The\ndiff of the source changes to palcode-clipper are in the\nnotes of Patch 4.\n\nPatch 3 depends on Patch 4, so they'd need to be squashed\ntogether to avoid breaking bisect.\n\nPatch 2 is much more straightforward: the Typhoon needs\naccess to the CPU index for its read of the Cchip's MISC\nregister; right now, we use current_cpu to get the index,\nbut this is an antipattern, because it violates\nencapsulation. Instead, we designate the requester_id\nattribute in MemTxAttrs for the CPU index.\n\nPatch 1 defines the instance_init for the Typhoon, so that\nwe can instantiate the Typhoon in clipper_init() and\nconnect the IRQ lines between the CPU and Typhoon there in\nPatch 3.\n\nI look forward to your feedback.\n\nThanks,\nYodel\n\n[1] https://lore.kernel.org/qemu-devel/20260310-qomify-alpha-v1-0-4375b00a85ff@yodel.dev/\n\nYodel Eldar (4):\n alpha: Define Typhoon instance_init\n alpha: Propagate CPU index via MemTxAttrs\n alpha: Replace helper_set_alarm with Typhoon Cchip MMIO register\n pc-bios/palcode-clipper: Replace qemu_alarm with Cchip register\n\n hw/alpha/alpha_sys.h | 4 ++-\n hw/alpha/dp264.c | 12 ++++++-\n hw/alpha/typhoon.c | 69 ++++++++++++++++++++++++++------------\n pc-bios/palcode-clipper | Bin 153728 -> 154432 bytes\n target/alpha/cpu.c | 17 ++++++++++\n target/alpha/cpu.h | 6 ----\n target/alpha/helper.c | 15 +++++++--\n target/alpha/helper.h | 1 -\n target/alpha/sys_helper.c | 12 -------\n target/alpha/translate.c | 11 ------\n 10 files changed, 91 insertions(+), 56 deletions(-)" }