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pr=C", "From": "Akhil R <akhilrajeev@nvidia.com>", "To": "<dmaengine@vger.kernel.org>, <linux-tegra@vger.kernel.org>", "CC": "<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,\n\t<vkoul@kernel.org>, <Frank.Li@kernel.org>, <robh@kernel.org>,\n\t<krzk+dt@kernel.org>, <conor+dt@kernel.org>, <thierry.reding@gmail.com>,\n\t<jonathanh@nvidia.com>, <p.zabel@pengutronix.de>, Akhil R\n\t<akhilrajeev@nvidia.com>", "Subject": "[PATCH 0/8] Add GPCDMA support in Tegra264", "Date": "Tue, 17 Feb 2026 23:04:49 +0530", "Message-ID": "<20260217173457.18628-1-akhilrajeev@nvidia.com>", "X-Mailer": "git-send-email 2.50.1", "Precedence": "bulk", "X-Mailing-List": "linux-tegra@vger.kernel.org", "List-Id": "<linux-tegra.vger.kernel.org>", "List-Subscribe": "<mailto:linux-tegra+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-tegra+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "X-NVConfidentiality": "public", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-NV-OnPremToCloud": "ExternallySecured", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BL02EPF0001A0FD:EE_|MW4PR12MB6804:EE_", "X-MS-Office365-Filtering-Correlation-Id": "9ae839b9-cebc-4f67-fa17-08de6e4b0022", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "\n\tBCL:0;ARA:13230040|82310400026|1800799024|376014|7416014|36860700013;", "X-Microsoft-Antispam-Message-Info": "\n Cv/sShP+yER3a68OGpWmtbsc7dbfbZrsu1QDy6lZh9m9OAeWTGuuYiW8sgd/8lZbWthdCCzW/S0dxQ8zBPEIhkRq4ZuQxe18h0yYM9opBg42f1nUHTAI+aWEbmcnGKprYSBFFBKK4g091sk0xAHi2uFzD/Ez4R+MdfnuS05Ivc0esUnn5RUjdwaxWAhP/YMYBkr1BIwYjEZK9aakUXrFlTpzdqoJtoImCuA0wCeU5zt7ikD/Fq8f3YpIbWBHMUlbqxpq8Lp7PRG7v6Ge5mLJJboC9MQzlk8JHP35f5o77KEug5ik/KyKfpNZBb4CUzN2kAKNvLONSWWK4KqzIGVIX7YM7HD7iq+rm0rmgznxMYEz3hgaaA1DOrPU/bfJbOStneM2Dq/cotR0t+7k6KNXqUMyLIwJjxBBFPimixVe0HYIDHayD+N6/IWFLF0Fd354cOI7PFH2Kg5oeswqnfeTvCjfUiVn2J5ZwfFDoCUYH5gSo9+tL0mrihjvvMNjnWgVxNzzSlwz4qS5M8Vh1vJZmbbK0GXHdXe1wFnQH7MhcA+fDL2nVgSNUUbT+4Xz7ZUXKHmCiHa7D4iM5RC4wXTpieKnD5XqoYNC+s31VHxtMH0LwJf6gvzC0zYHmx0zruH2JJg0vwDMbACaWRjuOZOpWmGwG3u4LIMKifCv+B/0qY+f44D/JqGdrxkzSyN0fb9s3ZVIbpUbwQo3jBSgaRjSMOGPBztZJyahncUmPK1T65ZWHITsXa5/q8a8TbbV0k3wZuhxOxxBm88oY4p8ZD255sDJVFcaIQwFGXZZhJp2sqTdp4VCDhXfenBfpkERTuqb8s0IgAKimt782Gi5bVj62KUYMbrv05mtyUk+jEfMexYiXkHY63r9qysDKfKzP971JqJrUc88NaZQDQ5JT7lIP7O+TMyDobzX/h80PIHEmS6gV0ZOzeoxRfIYWMVPcWCy6RzKz5+2Z4TKunluljAtBUeLb+xIJEepb92lCg+W5mJCq0B1DxHzQKP+ypgpsn9uXw8fNbwTr/atCckDleL5Kxi4X6214BwPN7M3sYNr4kBGfnmVm5qdA7khqPnYP+/+yKoheZFCBv9MnDCejiWvr84NHNVvPI8TOPtMT8+nqRmHG1udkRAvB+er4apCr4AqrDRmeiVcKWuVRe5lllySfXDwQHBn1j1QTm0G7tlF06Q5CwTZLb3nVNTAb2jQI1/2LHZG8u4u258qkXq+qV9k3Z3c288tU+lUHKsPzkWtBMaVRMGoa28T2Cnfhk4eaB1TUnsoEffvE3Um1M8JME8pqAGWN3ZgnxiOd7ZxTW+SgQHlwwXQ2As5e0PF/7UdctGnCm7irARGfzBQ/66vQx1Kq/SAgszIMM3nPzYbdt7PikxJmjKgBu9prxAmaY2SCy40Kt1xWJSkI4dXkG3bCbuh5shE4tH/8KLonfgWry6nS0qVk6SoKTebjNyQBo3oleTGOEM+P0rDkCeeCGM3CDuy/J9XBDTO4f2r0JbkR9INVCi2Yg/rr/Ez72H3lHc1OxCSEiUwBvNH6aPkvHvQRJu9Qg2n/L5wXALYwpVn+AhHXmmIs72wdLBEtrOxKtmPvspgzVfWOukXQ5nIQJZVQZ6b46hmE2rvGdtx6QuwN5XVDV/6+gD8bv+zRG7hFq72MP1ZNa/N1Kp+Ocs8o8WvHtEPxQ==", "X-Forefront-Antispam-Report": "\n\tCIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(376014)(7416014)(36860700013);DIR:OUT;SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n\t/5kKESJaR9hrSsxjodkjGkr370Nrvcw9cp1bC90hxFGgDNYd+emOq6OH5Ce04Ruj4EbmDCSGDXi0pPdnXvbrMInZLzJtYQWO3zYbVbjPQuvXxnGfqWmV/ySOw811cOp0AOLkKHVS/yvITDTbpceDph7rrK0OsEYsrEGrH5jZKmvXc2bIheRVVB03PxPqrgWqq9BFwKdh+9SZZj5vv66eTbd3+xNPnkeVTE05aP67RulH792so8fIbiVraw8XZiyE1vaquHmpOYd55YcuGfhD2GSUAy5v83cY6GG3pu8GW+mZwQ7Q8hgESRtaT/ORL5dTCAAT+IgePitNccB8XX3x4yppkAJFy3Gtsom6qQrgPWRDyCwrSgaksEGImrM+XOz4u3nrE/qlD4ZoZAWTqZTtapF244EvY/0pntMjpsGcRxcolXDMBo6KWfIrhWhTa1td", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "17 Feb 2026 17:35:53.5805\n (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 9ae839b9-cebc-4f67-fa17-08de6e4b0022", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tBL02EPF0001A0FD.namprd03.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MW4PR12MB6804" }, "content": "This series adds support for GPCDMA in Tegra264 with an additional\nsupport for separate stream ID for each channel. Tegra264 GPCDMA\ncontroller has changes in the register offset and uses 41 bit\naddressing for memory. Add changes in the tegra186-gpc-dma driver\nto support these.\n\nAkhil R (8):\n dt-bindings: dma: nvidia,tegra186-gpc-dma: Add iommu-map property\n dt-bindings: dma: nvidia,tegra186-gpc-dma: Make reset optional\n dmaengine: tegra: Make reset control optional\n dmaengine: tegra: Use struct for register offsets\n dmaengine: tegra: Support address width > 40 bits\n dmaengine: tegra: Use iommu-map for stream ID\n dmaengine: tegra: Add Tegra264 support\n arm64: tegra: Add iommu-map and enable GPCDMA in Tegra264\n\n .../bindings/dma/nvidia,tegra186-gpc-dma.yaml | 27 +-\n .../arm64/boot/dts/nvidia/tegra264-p3834.dtsi | 4 +\n arch/arm64/boot/dts/nvidia/tegra264.dtsi | 33 +-\n drivers/dma/tegra186-gpc-dma.c | 441 +++++++++++-------\n 4 files changed, 337 insertions(+), 168 deletions(-)" }