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{ "id": 2175694, "url": "http://patchwork.ozlabs.org/api/1.0/covers/2175694/?format=api", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.0/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20251218183122.408690-1-sergeev0xef@gmail.com>", "date": "2025-12-18T18:31:15", "name": "[RFC,0/6] More extendable PMU subsystem.", "submitter": { "id": 92294, "url": "http://patchwork.ozlabs.org/api/1.0/people/92294/?format=api", "name": "Aleksandr Sergeev", "email": "sergeev0xef@gmail.com" }, "series": [ { "id": 485896, "url": "http://patchwork.ozlabs.org/api/1.0/series/485896/?format=api", "date": "2025-12-18T18:31:20", "name": "More extendable PMU subsystem.", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/485896/mbox/" } ], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20230601 header.b=CL6nTjha;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-lf1-x12c.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-Mailman-Approved-At": "Thu, 18 Dec 2025 13:32:42 -0500", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Currently, the pmu implementation consists of two parts:\nthe first part is mcycle & minstret registers (let's call them \"builtin events\")\nand the second part is mhpmcounters.\n\nThe builtin events are supported well,\nincluding implementation of inhibiting, filtering, etc.\n\nBut the implementation of mhpmcounters has few problems:\n1. Non-builtin events are vendor-specific.\n The vendor, who wants to implement them (including filtering, interrupts, etc),\n has to write exactly the same code\n as which is already written for mcycle & minstret events.\n2. To implement custom events vendor must\n hardcode it right inside the general methods.\n So if there are two different vendors with\n their own events, they would write their code\n right beside each other, making the code\n harder to support.\n Also some collisions may occur in event indexes,\n as it is a global enum.\n3. SBI events hardcoded right inside the general code.\n As they are not a part of RISCV specification,\n it should be up to vendor to implement them or not.\n\nTo solve these problems, let's:\n1. Generalize code, handling builtin events & mhpmcounters the same way.\n So if some vendors want to get logic of builtin events,\n it would take minimum affort.\n2. Add special callbacks for custom events. So when vendors want\n custom events for their machine, they would not have to\n change the common code.\n3. SBI events are now implemented for virt machine only as a demo\n of how a new pmu subsystem works.\n\nAleksandr Sergeev (6):\n target/riscv: Refactor counter index calculation.\n target/riscv: Reimplement Smcdeleg/Ssccfg via read_*, write_* methods\n target/riscv: Get rid of hardcoded SBI events.\n target/riscv: Rearrange custom hpm counter api\n target/riscv: Add PMU events implementation for `virt`\n target/riscv/machine: Add smcntrpmf registers to VMStateDescription\n\n hw/misc/Kconfig | 3 +\n hw/misc/meson.build | 1 +\n hw/misc/virt_pmu.c | 142 ++++++++\n hw/riscv/Kconfig | 1 +\n hw/riscv/virt.c | 4 +-\n include/hw/misc/virt_pmu.h | 91 +++++\n target/riscv/cpu.c | 8 +\n target/riscv/cpu.h | 96 +++--\n target/riscv/cpu_bits.h | 4 +\n target/riscv/cpu_helper.c | 34 +-\n target/riscv/csr.c | 470 ++++++++----------------\n target/riscv/machine.c | 11 +-\n target/riscv/pmu.c | 708 ++++++++++++++-----------------------\n target/riscv/pmu.h | 26 +-\n 14 files changed, 769 insertions(+), 830 deletions(-)\n create mode 100644 hw/misc/virt_pmu.c\n create mode 100644 include/hw/misc/virt_pmu.h" }