Cover Letter Detail
Show a cover letter.
GET /api/1.0/covers/2175652/?format=api
{ "id": 2175652, "url": "http://patchwork.ozlabs.org/api/1.0/covers/2175652/?format=api", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/1.0/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20251218171459.75831-1-claudio.bantaloukas@arm.com>", "date": "2025-12-18T17:14:50", "name": "[v5,0/9] aarch64: Add fp8 sme 2.1 features per ACLE 2024Q4", "submitter": { "id": 88972, "url": "http://patchwork.ozlabs.org/api/1.0/people/88972/?format=api", "name": "Claudio Bantaloukas", "email": "claudio.bantaloukas@arm.com" }, "series": [ { "id": 485887, "url": "http://patchwork.ozlabs.org/api/1.0/series/485887/?format=api", "date": "2025-12-18T17:14:53", "name": "aarch64: Add fp8 sme 2.1 features per ACLE 2024Q4", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/485887/mbox/" } ], "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=arm.com header.i=@arm.com header.a=rsa-sha256\n header.s=selector1 header.b=V0AJDIlV;\n\tdkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com\n header.a=rsa-sha256 header.s=selector1 header.b=V0AJDIlV;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=38.145.34.32; helo=vm01.sourceware.org;\n envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org;\n receiver=patchwork.ozlabs.org)", "sourceware.org;\n\tdkim=pass (1024-bit key,\n unprotected) header.d=arm.com header.i=@arm.com header.a=rsa-sha256\n header.s=selector1 header.b=V0AJDIlV;\n\tdkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com\n header.a=rsa-sha256 header.s=selector1 header.b=V0AJDIlV", "sourceware.org;\n dmarc=pass (p=none dis=none) header.from=arm.com", "sourceware.org; spf=pass smtp.mailfrom=arm.com", "server2.sourceware.org;\n arc=pass smtp.remote-ip=40.107.130.26" ], "Received": [ "from vm01.sourceware.org (vm01.sourceware.org [38.145.34.32])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4dXHRR0Hwjz1y2f\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 19 Dec 2025 04:17:39 +1100 (AEDT)", "from vm01.sourceware.org (localhost [127.0.0.1])\n\tby sourceware.org (Postfix) with ESMTP id E8DE84BA23CA\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 18 Dec 2025 17:17:36 +0000 (GMT)", "from MRWPR03CU001.outbound.protection.outlook.com\n (mail-francesouthazon11011026.outbound.protection.outlook.com\n [40.107.130.26])\n by sourceware.org (Postfix) with ESMTPS id 599904BA2E23\n for <gcc-patches@gcc.gnu.org>; Thu, 18 Dec 2025 17:16:47 +0000 (GMT)", "from AM8P190CA0004.EURP190.PROD.OUTLOOK.COM (2603:10a6:20b:219::9)\n by GV1PR08MB7827.eurprd08.prod.outlook.com (2603:10a6:150:5b::10) with\n Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9434.6; Thu, 18 Dec\n 2025 17:16:40 +0000", "from AM1PEPF000252DB.eurprd07.prod.outlook.com\n (2603:10a6:20b:219:cafe::87) by AM8P190CA0004.outlook.office365.com\n (2603:10a6:20b:219::9) with Microsoft SMTP Server (version=TLS1_3,\n cipher=TLS_AES_256_GCM_SHA384) id 15.20.9434.6 via Frontend Transport; Thu,\n 18 Dec 2025 17:16:34 +0000", "from outbound-uk1.az.dlp.m.darktrace.com (4.158.2.129) by\n AM1PEPF000252DB.mail.protection.outlook.com (10.167.16.53) with Microsoft\n SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9434.6\n via Frontend Transport; Thu, 18 Dec 2025 17:16:39 +0000", "from DU7P194CA0024.EURP194.PROD.OUTLOOK.COM (2603:10a6:10:553::28)\n by PAXPR08MB6496.eurprd08.prod.outlook.com (2603:10a6:102:df::7) with\n Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9434.8; Thu, 18 Dec\n 2025 17:15:16 +0000", "from DB1PEPF000509F7.eurprd02.prod.outlook.com\n (2603:10a6:10:553:cafe::28) by DU7P194CA0024.outlook.office365.com\n (2603:10a6:10:553::28) with Microsoft SMTP Server (version=TLS1_3,\n cipher=TLS_AES_256_GCM_SHA384) id 15.20.9434.7 via Frontend Transport; Thu,\n 18 Dec 2025 17:15:14 +0000", "from nebula.arm.com (172.205.89.229) by\n DB1PEPF000509F7.mail.protection.outlook.com (10.167.242.153) with Microsoft\n SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.20.9434.6 via Frontend Transport; Thu, 18 Dec 2025 17:15:15 +0000", "from AZ-NEU-EX04.Arm.com (10.240.25.138) by AZ-NEU-EX03.Arm.com\n (10.240.25.137) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.29; Thu, 18 Dec\n 2025 17:15:07 +0000", "from e72c20ac6da1.eu-west-1.compute.internal (10.249.56.29) by\n mail.arm.com (10.240.25.138) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.29 via Frontend\n Transport; Thu, 18 Dec 2025 17:15:07 +0000" ], "DKIM-Filter": [ "OpenDKIM Filter v2.11.0 sourceware.org E8DE84BA23CA", "OpenDKIM Filter v2.11.0 sourceware.org 599904BA2E23" ], "DMARC-Filter": "OpenDMARC Filter v1.4.2 sourceware.org 599904BA2E23", "ARC-Filter": "OpenARC Filter v1.0.0 sourceware.org 599904BA2E23", "ARC-Seal": [ "i=3; a=rsa-sha256; d=sourceware.org; s=key; t=1766078207; cv=pass;\n b=SSEOpJPN18k6FQpI0Is5/ExKVt7wRqL6l7gZu1R7UMmmMrKnTK/jKldCenk0yFOT0HfvCE/7Rabo+vwJ4HyqkEHffqPFFpQmGzUjlz9wRt4JSU+V8VptI9kYI2TTjGpNjnT97rR+qntotZ2C5lqfeASKdQGkqxNi0alI0mN3jlA=", "i=2; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=pass;\n b=XH2C3OPTvaBYLH62ccfquNk5NAvagB0fpmfgDyCV6shpg9VCcwyVooMHeeRtCK8B+pu1rM7FOZDkRDzD0xp/O0RutBHnbcUowXXpcL5O+WTROXrud1sli9s4z02IWF/IRFXg1Gl/ry7iWzHImvJYmpLm1F/xZyaahFWzILVmDO6VQn5nWQuKeHx0ILbcyGc59vZaByJAzjm/s4Z1cPx8unJHgzWFdJaz0elcN8KF+Hyr7NoVDOuGbDTfMXyjFKkHbSY71zii9QIb7j/VAn5S9EgDXhGYTwPpwR4pkHFcgdmiXhtl47EHMn4v9I5MCnh+nQvoNQYTDodJBOXCTCeRsA==", "i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none;\n b=j6n76ms1pOinw5lf1VRipib2C2eVdrNeRTuQYeCios98LVpt40FijnisbjzPZAGv3kCdsc7yQ3M4hscX6hQHapH5gBBvD670cBJJj5xeMDvlIaJTYP3CmnoUG/78gHOJ9UfJA330JKRU4pdJiteXUc6RgCKOYUa4ZqzRx5KXIhuLrb/KiKkHTUmyhjoyw5W1eh0BmjWI+hh7wSXDY1SI9NusNWBWZmQD96ATKXjmT0V/WR9wzpXlYQGdgJUkmBTjq8O+06YQ/xDI0rLx9zGtNr0nHf/kzhIwy6dMFVDCl2CIhls3TgGI4+opHj1yOF9sonEkUxoQ6fgq87gTF+eucQ==" ], "ARC-Message-Signature": [ "i=3; a=rsa-sha256; d=sourceware.org; s=key;\n t=1766078207; c=relaxed/simple;\n bh=JA+FP8OjtqkXBPCbSuGQsRtFgPNudXdFcp7D9Dm36PQ=;\n h=DKIM-Signature:DKIM-Signature:From:To:Subject:Date:Message-ID:\n MIME-Version;\n b=qAtge0RWFp7gpNbf+WlsBSVrGAhXkYalGw+w03y9/vCAEJXIRHG8eTIe+IAp988Fan00B0nPG814+xhkrobl8TEOX/JnRKANrlS0oItvpT9E0RrVkKj7cLnb4JePYN/k1WDVpYxYJKipDj3wsXZIe6e+/Bp33QS+TJ6eX7SPNWo=", "i=2; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector10001;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=FwzlSXGhnGtjErlK0b41Roacim+nMzWhXeOfB/dODpI=;\n b=PgDiwsHUBoZdV9uGtlku+58cU110MKg29gkaXeeQGqAfOZWfl7Hs3EE1V/ENQbLX41O8QRAwJVWgxhVf5xYUm6Zo9ldmuLtLirabqtCaCdHUkMcJxyBeq6wPIyAujoyyzRqcCQjkl+w9TBK5ExEMsw/md407M0GI/gcIZQ0cN7dtZmSaxCSTObrof/vUHZCpLd5s4oeS/jwGVfc52WKG6EXL+EA4uaMp/Vo7fhtOKOqJsGummbgHvmlppuujy9HtbGcPn/tkf2uWlyI8LuIMIOFFdcHqcPquXaPjVrmEqQqp0abx20iKExUXKPzgicRXq3Ixm39jrIOzKdjUalatLw==", "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector10001;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=FwzlSXGhnGtjErlK0b41Roacim+nMzWhXeOfB/dODpI=;\n b=N4vHY/fz6aqOw9jEUKRD7lQz4mEldJz6FW3ehoWKrTZIsEDmKwMuLdpK0YbljLG35G9iFmNVssB+MZDYi4wfocPJK0rbtKj5q3aH3Xgqymc9+RCEK6Zfl/iahVmsFfczbTN8TtF0KU0i2UxNbM9nxGI/8goRCrt6jqyvkH8ZHVryTXSMWn6/cBomm65MlxCPRi37FWPcR4RuBDIL4GfIaS8/IIp2XaGIjB9Vl2SV0jmrabJlTawcRqwW2EYQ/Lc5SYWc+xqZfwLT7W3PNd8swuwYaFnn6BmGrGZbfdZAr+7z8QsBsPrH/RYN0HFgcFuklTykx5CnME7gugt97Y2y1g==" ], "ARC-Authentication-Results": [ "i=3; server2.sourceware.org", "i=2; mx.microsoft.com 1; spf=pass (sender ip is\n 4.158.2.129) smtp.rcpttodomain=oss.qualcomm.com smtp.mailfrom=arm.com;\n dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com;\n dkim=pass (signature was verified) header.d=arm.com; arc=pass (0 oda=1 ltdi=1\n spf=[1,1,smtp.mailfrom=arm.com] dmarc=[1,1,header.from=arm.com])", "i=1; mx.microsoft.com 1; spf=pass (sender ip is\n 172.205.89.229) smtp.rcpttodomain=gcc.gnu.org smtp.mailfrom=arm.com;\n dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com;\n dkim=none (message not signed); arc=none (0)" ], "DKIM-Signature": [ "v=1; a=rsa-sha256; c=relaxed/relaxed; d=arm.com; s=selector1;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=FwzlSXGhnGtjErlK0b41Roacim+nMzWhXeOfB/dODpI=;\n b=V0AJDIlVpt5b+GuYh5ENmCJuekup1j7iOHnomrNNTFqCmslqLQEZz18AMHiLzrKAzw9YiW8amyod53ZwwMfaAe9+G0A6ybN16h0chjtnhCKYfjgVi6v+LPbm613huNZ2ymLW3Dkac7Su49CTU0nq0pDRInWlUGVIIwZ5sYmWJKc=", "v=1; a=rsa-sha256; c=relaxed/relaxed; d=arm.com; s=selector1;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=FwzlSXGhnGtjErlK0b41Roacim+nMzWhXeOfB/dODpI=;\n b=V0AJDIlVpt5b+GuYh5ENmCJuekup1j7iOHnomrNNTFqCmslqLQEZz18AMHiLzrKAzw9YiW8amyod53ZwwMfaAe9+G0A6ybN16h0chjtnhCKYfjgVi6v+LPbm613huNZ2ymLW3Dkac7Su49CTU0nq0pDRInWlUGVIIwZ5sYmWJKc=" ], "X-MS-Exchange-Authentication-Results": [ "spf=pass (sender IP is 4.158.2.129)\n smtp.mailfrom=arm.com; dkim=pass (signature was verified)\n header.d=arm.com;dmarc=pass action=none header.from=arm.com;", "spf=pass (sender IP is 172.205.89.229)\n smtp.mailfrom=arm.com; dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=arm.com;" ], "Received-SPF": [ "Pass (protection.outlook.com: domain of arm.com designates\n 4.158.2.129 as permitted sender) receiver=protection.outlook.com;\n client-ip=4.158.2.129; helo=outbound-uk1.az.dlp.m.darktrace.com; pr=C", "Pass (protection.outlook.com: domain of arm.com designates\n 172.205.89.229 as permitted sender) receiver=protection.outlook.com;\n client-ip=172.205.89.229; helo=nebula.arm.com; pr=C" ], "From": "Claudio Bantaloukas <claudio.bantaloukas@arm.com>", "To": "Gcc Patches ML <gcc-patches@gcc.gnu.org>", "CC": "Alex Coplan <alex.coplan@arm.com>, Alice Carlotti\n <alice.carlotti@arm.com>, Andrew Pinski <andrew.pinski@oss.qualcomm.com>,\n Kyrylo Tkachov <ktkachov@nvidia.com>, Richard Earnshaw\n <richard.earnshaw@arm.com>, Tamar Christina <tamar.christina@arm.com>, \"Wilco\n Dijkstra\" <wilco.dijkstra@arm.com>, Claudio Bantaloukas\n <claudio.bantaloukas@arm.com>", "Subject": "[PATCH v5 0/9] aarch64: Add fp8 sme 2.1 features per ACLE 2024Q4", "Date": "Thu, 18 Dec 2025 17:14:50 +0000", "Message-ID": "<20251218171459.75831-1-claudio.bantaloukas@arm.com>", "X-Mailer": "git-send-email 2.51.0", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-EOPAttributedMessage": "1", "X-MS-TrafficTypeDiagnostic": "\n DB1PEPF000509F7:EE_|PAXPR08MB6496:EE_|AM1PEPF000252DB:EE_|GV1PR08MB7827:EE_", "X-MS-Office365-Filtering-Correlation-Id": "1b8afad9-d67a-4c81-2fa4-08de3e5934fd", "x-checkrecipientrouted": "true", "NoDisclaimer": "true", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam-Untrusted": "BCL:0;\n ARA:13230040|36860700013|82310400026|1800799024|376014;", "X-Microsoft-Antispam-Message-Info-Original": "\n +saTlCihF3olTFKm/ys3mYOHx1x6ovZgfYRrwCVUZRLDhkF8micVRjz30mvqjmOvgSnov+HAPGhFeCIDhAGgBzEIkFyMlTZytOzPpjz5Sd4HsqyTt14mdgLMQulGFQPq63j+SPhf9Qql0HyhqZPvnnYOJJe64Rb15V4OmuexbP33cp6LvgK3f1Xslr0sqT6RVaW7TmHTLyVAyy1DuaZm0C0qujMsUUJBURUD/j43vwdZjCkGMzaJE0c5y5wqyqmxrApMzsUMb8CNBz1fV7NPOdXARmlku0+JxieCkN4zONSPvM7jeRuB5DkoeQjpzadC389WrLktxj1cN+/WHBFXC9dBIjVeeTN+cNVaqj/B5g65NyW17hVNY44H3Inqqdw7WnRBWZxc7b8E+z/LtrwdJs8jNwcCWQm2abnv10IqrHRcR5NtGCBU9jLO9WQndyEqMR1igH/7YDvT4NFQ8BF8oVZihoh+4Xh1lNXwkgrd1hr36YFlyIIlK2Rk5HqO28+TmE8dGLa3k5ZZUs9Q6S/VLooD6CCkMZJmhNJ9fdCfci/3KdkXo4BcbY8L25H8dnJyv9Lpn4A4Cbnq3W4q9kD9/hCB+dP2sY/DZn3ZnkjMKD2fYXLGRiAy+iDktR5/qBInmM1lDqfBImNAEZT31p22R6nPk0FAEOYNJtEbUJVSnIEu7DSaVL4YoKXu78f5rkXybxcl2g5y2LP9Pw74IKfyRQbuY0+/IDIFwMtfGfXpY3mNZq6JwXkKnZuWghSbYUpaItDg5Lk5FMCiRXNMfxHpe24D3rPEAi2YmrKxMANlfdjHVbPDTKj/dTMtozLKqcjx/LzlMy0Ze+RZUXJCTG51dPe5M9lQ7Y4ChDHgMheESpKBTqCMCoG7lVQouwm4YAlnJ8yGopL66jbST7ZMCe+5E82yYQK7lQefNMXyyPzj942m8x/r98x5JuV/5O5UVtK9aO11ZxtXo/fkZHByYAO6Ew/HZ36BoP3asel/gfKD3N9HoKKsuoM/YcwT6danG/25Zqi07lTsNfl3RfLdE1bbjV6R3YI+5cWuKDidkzX5DQkQm+FOOmvLhe65r7j1iS+782U7Nh2O+kj6MAU1IugD7VShEzPvR72KUo5tEAnmEIsIGAsSc44OAgp3ith4DiLpCZqImhs/QFgIVwNO96fxgXjhZPkaVkG8GPqXFoqy727Inx7ASDYqvYPjJSCMGrgV5nxbaljy40nP50M8YstsSlPKkG3uAQQYFYkDyiMTnEStb1R+3OD0tis8yZrEc49VyMYuoimmhCLOUDgW3em57eSZ4Hy2wXvLmIlWmCxuXN5GJR8FKFtFuSikhmZ0DuP9qvY/4+bZ3C+sUkNGn9HXV4RLnDzQzUVg23kAnyDt141ASJquK2EYasuaG81JKWUIZs1X9yh94fAkJp58+vTjIAIJrB6QviRh1g5LSzB5WU+gjuxW+mQg/tZxPHQsEmLvqGNbISmT8jHswAvv/saRhH8RT+kPM/y6O2YFlp0ojeUmf++/LCUkAJZUBMNb9kjXy5J5HgwJckasvmFxIC5rNcKwdiPB3XC1ubR5Yk9TZU8=", "X-Forefront-Antispam-Report-Untrusted": "CIP:172.205.89.229; CTRY:IE; LANG:en;\n SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:nebula.arm.com; PTR:InfoDomainNonexistent;\n CAT:NONE; SFS:(13230040)(36860700013)(82310400026)(1800799024)(376014);\n DIR:OUT; SFP:1101;", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": [ "PAXPR08MB6496", "GV1PR08MB7827" ], "X-MS-Exchange-Transport-CrossTenantHeadersStripped": "\n AM1PEPF000252DB.eurprd07.prod.outlook.com", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id-Prvs": "\n 40157441-261a-4b00-e0e3-08de3e5902bd", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230040|14060799003|36860700013|82310400026|376014|35042699022|1800799024;", "X-Microsoft-Antispam-Message-Info": "\n SnwawuCSNwkYRkgp/4GdSGaZVu3kipckFabe4ORX2ujWhY58i8ZuTNjqv+5Xjy1eeAGeVJAAV795YbLp9rd1+ChBm2+jdbtn6XTrbYW8ZYQx/3+/Hsrnzk7HLLNzmviJPB1oeKhQw3gE/c44cx2a+YWsr29cUpb+oqIP4WkdaLETy3sHfqRHUY3PSM9L1cneWUHZMmmv+Q2jVC5UIlosxlvy7OZaw4AIit/VOEJThbwTcqXAMkj7ZvcSQfN8xIFxMGESqGYKbfYaSHxY25EFBhdD7fa/JjNGKZLL/jDx8FuQZ2AS3Vowxu1c9DDckH4QmeqW0zzKLjzh4Y8iCDMn1pEN6E1haVhlYJ8SBINzENuK4fEh7DX0jlMyZeA9LFTcAWFSgiPa6AbNkARM7dO2Ow/XT4yLYCAMCchkUABl8x2KixnqIlBAokPEtEgajKO2H09tAHhPxrjn+4Qqz5nJPYUZ3BpPncbKka+x7C7dn+1/qyDszzy2XffSZGPQSck8Fc/1L5+7sEUl1Q/ncIvUkFn1xHz6O9quDpPuxYfU/K1KzosDIyUiFQKrCbjyHRCrx4g+1RsYdZpWOAGTHfAs0HICtJ/Mlt+plsSP1nRZhWNSaoj03DFnGS6WnjyIsI25l3/DrZ2pCAKmKMVX/iyeXr/l1zZzqKFq6deVB3n3tWPiWVaH1doq5xwlNv1ol+EabXTjUW52vvdCvnEG7uonEt+1axYHbRJAJ13jkJ5jDgGvdzb3rzB00cOdtd2QxgCG18EOKhjsRabSBKj39940Zjg+3OZbj0l6cFm5Z1nKTo8b4aVrfKsIWcT2FZmjiWUTrMOoVcqhNakSqrWxvmRUTs//y55YJzr8BScWM+hg90xal8eLG5n2hbZzoeJsq4MEYTRNgdDDllLIQ516CMXuKNiWA5sbJn7Nt3GZBKB89IxAceFMKGRAzwqv+331Wa/LbOfD5lhC2xR7oMF5iLYh8nZ78rmGttvvzWmEb3PltmTKdia1URdYcYz+BhexHU+l6Iqy+XDHQKibiE2XFN0x9Kg0BIctxS7Ygp3P/2N4Ai3UpaSz0Ku0nylU0jjZ07P3WyJol6Q9ZcJ9/puAN6LHaXzZBHiMErelqYMeWuSqbNPt7pAyqt9tMspNgBEZcil4yJV0ijYCvug1u7FP+GMxKXKYUNxm1RihGqOHbMbuA9ngVHnZK6GhL+Pud1x9VZJqcio3nNrqX6VSklXW8FEaT68tOHEqlfxg4mFWTs7A/NsMJoktI/1vC721AoEKQfetpaBIW8otWKdziDeE6eWIiuqbU4Yt0IIEtVV5ypRHlPpsbzaTgiktpzFXVholyKHBR33g1wkQgN9MwIPj9PAuHjhJdD/iaIYyfdhIgH9j8CxN+wyPT/hH/4VVguKN421h4vlGbj8sf0Bd95jYabfx8HY9piSJMws8u77xkxZnIn4DUbCg9++OORlJB2Nv/I0706ZpI3INo+fHhgZTNUUFgCY/Wz+Oz32wgk2V5dYvgeSM6OChTwC+Xti0zfZdnAcJP5PQaM5iCWKdpiwj/QLJDaEp8MCGk0nAiZwCVyat3L4=", "X-Forefront-Antispam-Report": "CIP:4.158.2.129; CTRY:GB; LANG:en; SCL:1; SRV:;\n IPV:NLI; SFV:NSPM; H:outbound-uk1.az.dlp.m.darktrace.com;\n PTR:InfoDomainNonexistent; CAT:NONE;\n SFS:(13230040)(14060799003)(36860700013)(82310400026)(376014)(35042699022)(1800799024);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "arm.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "18 Dec 2025 17:16:39.4193 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 1b8afad9-d67a-4c81-2fa4-08de3e5934fd", "X-MS-Exchange-CrossTenant-Id": "f34e5979-57d9-4aaa-ad4d-b122a662184d", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[4.158.2.129];\n Helo=[outbound-uk1.az.dlp.m.darktrace.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n AM1PEPF000252DB.eurprd07.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "This patch series completes support for SME2 and SME2p1 intrinsics relative to\nmodal 8bit floating point types.\n\n- The first patch in the series introduces tests for using luti intrinsics with\n mf8 that was already working since their introduction, now that their use is\n documented in ACLE.\n- The second patch extends the definitions of existing non-interpreting sve2/sme\n intrinsics to support mfloat8 types.\n- The third and fourth patches add widening and narrowing sme2 fp8 conversions\n respectively (svcvt).\n- The fifth patch adds multi-vector floating-point adjust exponent intrinsics\n (svscale).\n- The sixth patch adds support for the sme-f8f16 and sme-f8f32 arch features\n and related defines.\n- Patch 7 adds Multi-vector 8-bit floating-point multiply-add long intrinsics.\n- Patch 8 adds 8-bit floating-point sum of outer products and accumulate\n intrinsics.\n- Patch 9 adds 8-bit floating point dot product intrinsics.\n\nCompared to version 1 of this patch series:\n- updated commit messages per requests.\n- fixed gating of intrinsics in patch four (narrowing sme2 conversions to fp8).\n- introduced aarch64_output_asm_with_extra_operand function and updated insns in\n aarch64-sme.md to no longer use out of bounds operands.\n\nCompared to version 2 of this patch series:\n- replaced aarch64_output_asm_with_extra_operand with\n aarch64_output_asm_with_offset which does not require allocating space for\n operands on the stack in patch 7.\n\nCompared to version 3 of this patch series:\n- Entirely removed functions using snprintf and returned to existing use of\n operands array as the array is long enough for this use.\n- Addressed Richard Ball's feedback (renamed test files, improved readability in\n exp file, formatting).\n\nCompared to version 4 of this patch series:\n- Reposting patches inline rather than as attachments.\n- Accidentally posted the last 8 rather than 9 patches. Thanks to Artemiy who\n spotted this.\n\nRegression tested on aarch64-unknown-linux-gnu.\n\nOK to merge?\n\nThanks,\nClaudio Bantaloukas\n\n\nClaudio Bantaloukas (8):\n aarch64: add tests for sme mfloat8 luti functions\n aarch64: extend sme intrinsics to mfp8\n aarch64: add widening sme2 fp8 conversions\n aarch64: add narrowing sme2 conversions to fp8\n aarch64: add multi-vector floating-point adjust exponent intrinsics\n aarch64: add basic support for sme-f8f16 and sme-f8f32\n aarch64: add Multi-vector 8-bit floating-point multiply-add long\n aarch64: add 8-bit floating-point sum of outer products and accumulate\n\nKarl Meakin (1):\n aarch64: add 8-bit floating point dot product\n\n gcc/config/aarch64/aarch64-c.cc | 4 +\n .../aarch64/aarch64-option-extensions.def | 4 +\n gcc/config/aarch64/aarch64-sme.md | 571 ++++++++++++++++++\n .../aarch64/aarch64-sve-builtins-base.cc | 47 +-\n .../aarch64/aarch64-sve-builtins-functions.h | 23 +-\n .../aarch64/aarch64-sve-builtins-shapes.cc | 43 +-\n .../aarch64/aarch64-sve-builtins-shapes.h | 1 +\n .../aarch64/aarch64-sve-builtins-sme.cc | 20 +-\n .../aarch64/aarch64-sve-builtins-sme.def | 55 +-\n gcc/config/aarch64/aarch64-sve-builtins-sme.h | 2 +\n .../aarch64/aarch64-sve-builtins-sve2.cc | 2 +\n .../aarch64/aarch64-sve-builtins-sve2.def | 12 +\n .../aarch64/aarch64-sve-builtins-sve2.h | 2 +\n gcc/config/aarch64/aarch64-sve-builtins.cc | 34 +-\n gcc/config/aarch64/aarch64-sve2.md | 52 +-\n gcc/config/aarch64/aarch64.h | 10 +\n gcc/config/aarch64/iterators.md | 73 ++-\n gcc/doc/invoke.texi | 6 +\n .../aarch64/sme2/aarch64-sme2-acle-asm.exp | 3 +-\n .../gcc.target/aarch64/pragma_cpp_predefs_4.c | 34 ++\n .../aarch64/sme/acle-asm/read_hor_za128.c | 31 +\n .../aarch64/sme/acle-asm/read_hor_za8.c | 31 +\n .../aarch64/sme/acle-asm/read_ver_za128.c | 31 +\n .../aarch64/sme/acle-asm/read_ver_za8.c | 31 +\n .../aarch64/sme/acle-asm/revd_mf8.c | 76 +++\n .../aarch64/sme/acle-asm/test_sme_acle.h | 2 +-\n .../aarch64/sme/acle-asm/write_hor_za128.c | 10 +\n .../aarch64/sme/acle-asm/write_hor_za8.c | 10 +\n .../aarch64/sme/acle-asm/write_ver_za128.c | 10 +\n .../aarch64/sme/acle-asm/write_ver_za8.c | 10 +\n .../aarch64/sme2/aarch64-sme2-acle-asm.exp | 3 +-\n .../aarch64/sme2/acle-asm/cvt_mf8_bf16_x2.c | 56 ++\n .../aarch64/sme2/acle-asm/cvt_mf8_f16_x2.c | 56 ++\n .../aarch64/sme2/acle-asm/cvt_mf8_f32_x4.c | 72 +++\n .../aarch64/sme2/acle-asm/cvt_mf8_x2.c | 47 ++\n .../aarch64/sme2/acle-asm/cvtl_mf8_x2.c | 47 ++\n .../aarch64/sme2/acle-asm/cvtn_mf8_f32_x4.c | 72 +++\n .../sme2/acle-asm/dot_lane_za16_mf8_vg1x2.c | 119 ++++\n .../sme2/acle-asm/dot_lane_za16_mf8_vg1x4.c | 125 ++++\n .../sme2/acle-asm/dot_lane_za32_mf8_vg1x2.c | 119 ++++\n .../sme2/acle-asm/dot_lane_za32_mf8_vg1x4.c | 125 ++++\n .../sme2/acle-asm/dot_single_za16_mf8_vg1x2.c | 126 ++++\n .../sme2/acle-asm/dot_single_za16_mf8_vg1x4.c | 126 ++++\n .../sme2/acle-asm/dot_single_za32_mf8_vg1x2.c | 126 ++++\n .../sme2/acle-asm/dot_single_za32_mf8_vg1x4.c | 126 ++++\n .../sme2/acle-asm/dot_za16_mf8_vg1x2.c | 150 +++++\n .../sme2/acle-asm/dot_za16_mf8_vg1x4.c | 166 +++++\n .../sme2/acle-asm/dot_za32_mf8_vg1x2.c | 150 +++++\n .../sme2/acle-asm/dot_za32_mf8_vg1x4.c | 166 +++++\n .../aarch64/sme2/acle-asm/ld1_mf8_x2.c | 262 ++++++++\n .../aarch64/sme2/acle-asm/ld1_mf8_x4.c | 354 +++++++++++\n .../aarch64/sme2/acle-asm/ldnt1_mf8_x2.c | 262 ++++++++\n .../aarch64/sme2/acle-asm/ldnt1_mf8_x4.c | 354 +++++++++++\n .../aarch64/sme2/acle-asm/luti2_mf8.c | 48 ++\n .../aarch64/sme2/acle-asm/luti2_mf8_x2.c | 50 ++\n .../aarch64/sme2/acle-asm/luti2_mf8_x4.c | 56 ++\n .../aarch64/sme2/acle-asm/luti4_mf8.c | 48 ++\n .../aarch64/sme2/acle-asm/luti4_mf8_x2.c | 50 ++\n .../sme2/acle-asm/mla_lane_za16_mf8_vg2x1.c | 167 +++++\n .../sme2/acle-asm/mla_lane_za16_mf8_vg2x2.c | 136 +++++\n .../sme2/acle-asm/mla_lane_za16_mf8_vg2x4.c | 142 +++++\n .../sme2/acle-asm/mla_lane_za32_mf8_vg4x1.c | 169 ++++++\n .../sme2/acle-asm/mla_lane_za32_mf8_vg4x2.c | 137 +++++\n .../sme2/acle-asm/mla_lane_za32_mf8_vg4x4.c | 143 +++++\n .../sme2/acle-asm/mla_za16_mf8_vg2x1.c | 167 +++++\n .../sme2/acle-asm/mla_za16_mf8_vg2x2.c | 285 +++++++++\n .../sme2/acle-asm/mla_za16_mf8_vg2x4.c | 287 +++++++++\n .../sme2/acle-asm/mla_za32_mf8_vg4x1.c | 167 +++++\n .../sme2/acle-asm/mla_za32_mf8_vg4x2.c | 277 +++++++++\n .../sme2/acle-asm/mla_za32_mf8_vg4x4.c | 289 +++++++++\n .../aarch64/sme2/acle-asm/mopa_za16_mf8.c | 36 ++\n .../aarch64/sme2/acle-asm/mopa_za32_mf8.c | 36 ++\n .../aarch64/sme2/acle-asm/read_hor_za8_vg2.c | 78 +++\n .../aarch64/sme2/acle-asm/read_hor_za8_vg4.c | 91 +++\n .../aarch64/sme2/acle-asm/read_ver_za8_vg2.c | 78 +++\n .../aarch64/sme2/acle-asm/read_ver_za8_vg4.c | 91 +++\n .../aarch64/sme2/acle-asm/read_za8_vg1x2.c | 48 ++\n .../aarch64/sme2/acle-asm/read_za8_vg1x4.c | 54 ++\n .../aarch64/sme2/acle-asm/readz_hor_za128.c | 10 +\n .../aarch64/sme2/acle-asm/readz_hor_za8.c | 10 +\n .../aarch64/sme2/acle-asm/readz_hor_za8_vg2.c | 78 +++\n .../aarch64/sme2/acle-asm/readz_hor_za8_vg4.c | 91 +++\n .../aarch64/sme2/acle-asm/readz_ver_za128.c | 197 ++++++\n .../aarch64/sme2/acle-asm/readz_ver_za8.c | 10 +\n .../aarch64/sme2/acle-asm/readz_ver_za8_vg2.c | 77 +++\n .../aarch64/sme2/acle-asm/readz_ver_za8_vg4.c | 90 +++\n .../aarch64/sme2/acle-asm/readz_za8_vg1x2.c | 48 ++\n .../aarch64/sme2/acle-asm/readz_za8_vg1x4.c | 56 ++\n .../aarch64/sme2/acle-asm/scale_f16_x2.c | 192 ++++++\n .../aarch64/sme2/acle-asm/scale_f16_x4.c | 229 +++++++\n .../aarch64/sme2/acle-asm/scale_f32_x2.c | 208 +++++++\n .../aarch64/sme2/acle-asm/scale_f32_x4.c | 229 +++++++\n .../aarch64/sme2/acle-asm/scale_f64_x2.c | 208 +++++++\n .../aarch64/sme2/acle-asm/scale_f64_x4.c | 229 +++++++\n .../aarch64/sme2/acle-asm/sel_mf8_x2.c | 92 +++\n .../aarch64/sme2/acle-asm/sel_mf8_x4.c | 92 +++\n .../aarch64/sme2/acle-asm/st1_mf8_x2.c | 262 ++++++++\n .../aarch64/sme2/acle-asm/st1_mf8_x4.c | 354 +++++++++++\n .../aarch64/sme2/acle-asm/stnt1_mf8_x2.c | 262 ++++++++\n .../aarch64/sme2/acle-asm/stnt1_mf8_x4.c | 354 +++++++++++\n .../aarch64/sme2/acle-asm/test_sme2_acle.h | 12 +-\n .../aarch64/sme2/acle-asm/uzp_mf8_x2.c | 77 +++\n .../aarch64/sme2/acle-asm/uzp_mf8_x4.c | 73 +++\n .../aarch64/sme2/acle-asm/uzpq_mf8_x2.c | 77 +++\n .../aarch64/sme2/acle-asm/uzpq_mf8_x4.c | 73 +++\n .../sme2/acle-asm/vdot_lane_za16_mf8_vg1x2.c | 119 ++++\n .../sme2/acle-asm/vdotb_lane_za32_mf8_vg1x4.c | 119 ++++\n .../sme2/acle-asm/vdott_lane_za32_mf8_vg1x4.c | 119 ++++\n .../aarch64/sme2/acle-asm/write_hor_za8_vg2.c | 78 +++\n .../aarch64/sme2/acle-asm/write_hor_za8_vg4.c | 91 +++\n .../aarch64/sme2/acle-asm/write_ver_za8_vg2.c | 78 +++\n .../aarch64/sme2/acle-asm/write_ver_za8_vg4.c | 91 +++\n .../aarch64/sme2/acle-asm/write_za8_vg1x2.c | 48 ++\n .../aarch64/sme2/acle-asm/write_za8_vg1x4.c | 54 ++\n .../aarch64/sme2/acle-asm/zip_mf8_x2.c | 77 +++\n .../aarch64/sme2/acle-asm/zip_mf8_x4.c | 73 +++\n .../aarch64/sme2/acle-asm/zipq_mf8_x2.c | 77 +++\n .../aarch64/sme2/acle-asm/zipq_mf8_x4.c | 73 +++\n .../aarch64/sve/acle/asm/test_sve_acle.h | 3 +\n .../sve/acle/general-c/binary_za_m_1.c | 14 +\n .../acle/general-c/binary_za_slice_lane_1.c | 14 +\n .../general-c/binary_za_slice_opt_single_1.c | 16 +\n .../general-c/dot_half_za_slice_lane_fpm.c | 106 ++++\n .../aarch64/sve2/acle/asm/ld1_mf8_x2.c | 269 +++++++++\n .../aarch64/sve2/acle/asm/ld1_mf8_x4.c | 361 +++++++++++\n .../aarch64/sve2/acle/asm/ldnt1_mf8_x2.c | 269 +++++++++\n .../aarch64/sve2/acle/asm/ldnt1_mf8_x4.c | 361 +++++++++++\n .../aarch64/sve2/acle/asm/revd_mf8.c | 80 +++\n .../aarch64/sve2/acle/asm/stnt1_mf8_x2.c | 269 +++++++++\n .../aarch64/sve2/acle/asm/stnt1_mf8_x4.c | 361 +++++++++++\n gcc/testsuite/lib/target-supports.exp | 1 +\n 131 files changed, 14445 insertions(+), 45 deletions(-)\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_mf8.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvt_mf8_bf16_x2.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvt_mf8_f16_x2.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvt_mf8_f32_x4.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvt_mf8_x2.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtl_mf8_x2.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtn_mf8_f32_x4.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/dot_lane_za16_mf8_vg1x2.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/dot_lane_za16_mf8_vg1x4.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/dot_lane_za32_mf8_vg1x2.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/dot_lane_za32_mf8_vg1x4.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/dot_single_za16_mf8_vg1x2.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/dot_single_za16_mf8_vg1x4.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/dot_single_za32_mf8_vg1x2.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/dot_single_za32_mf8_vg1x4.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/dot_za16_mf8_vg1x2.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/dot_za16_mf8_vg1x4.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/dot_za32_mf8_vg1x2.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/dot_za32_mf8_vg1x4.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/ld1_mf8_x2.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/ld1_mf8_x4.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/ldnt1_mf8_x2.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/ldnt1_mf8_x4.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/luti2_mf8.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/luti2_mf8_x2.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/luti2_mf8_x4.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/luti4_mf8.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/luti4_mf8_x2.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mla_lane_za16_mf8_vg2x1.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mla_lane_za16_mf8_vg2x2.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mla_lane_za16_mf8_vg2x4.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mla_lane_za32_mf8_vg4x1.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mla_lane_za32_mf8_vg4x2.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mla_lane_za32_mf8_vg4x4.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mla_za16_mf8_vg2x1.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mla_za16_mf8_vg2x2.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mla_za16_mf8_vg2x4.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mla_za32_mf8_vg4x1.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mla_za32_mf8_vg4x2.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mla_za32_mf8_vg4x4.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mopa_za16_mf8.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mopa_za32_mf8.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/readz_ver_za128.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/scale_f16_x2.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/scale_f16_x4.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/scale_f32_x2.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/scale_f32_x4.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/scale_f64_x2.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/scale_f64_x4.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/sel_mf8_x2.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/sel_mf8_x4.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/st1_mf8_x2.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/st1_mf8_x4.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/stnt1_mf8_x2.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/stnt1_mf8_x4.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/uzp_mf8_x2.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/uzp_mf8_x4.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/uzpq_mf8_x2.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/uzpq_mf8_x4.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/vdot_lane_za16_mf8_vg1x2.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/vdotb_lane_za32_mf8_vg1x4.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/vdott_lane_za32_mf8_vg1x4.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/zip_mf8_x2.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/zip_mf8_x4.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/zipq_mf8_x2.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/zipq_mf8_x4.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/dot_half_za_slice_lane_fpm.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/ld1_mf8_x2.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/ld1_mf8_x4.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/ldnt1_mf8_x2.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/ldnt1_mf8_x4.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/revd_mf8.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/stnt1_mf8_x2.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/stnt1_mf8_x4.c" }