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{ "id": 2175486, "url": "http://patchwork.ozlabs.org/api/1.0/covers/2175486/?format=api", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/1.0/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20251218-gicv5-host-acpi-v2-0-eec76cd1d40b@kernel.org>", "date": "2025-12-18T10:14:26", "name": "[v2,0/7] irqchip/gic-v5: Code first ACPI boot support", "submitter": { "id": 84664, "url": "http://patchwork.ozlabs.org/api/1.0/people/84664/?format=api", "name": "Lorenzo Pieralisi", "email": "lpieralisi@kernel.org" }, "series": [ { "id": 485814, "url": "http://patchwork.ozlabs.org/api/1.0/series/485814/?format=api", "date": "2025-12-18T10:14:26", "name": "irqchip/gic-v5: Code first ACPI boot support", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/485814/mbox/" } ], "headers": { "Return-Path": "\n <linux-pci+bounces-43273-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=Rg678wxJ;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; 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a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1766052905; cv=none;\n b=oi3nGtbblx/hCVCDpV46No6nTyy6BPavNyueQghwwmBCkH5/9bG1iHtPZqyvSKx6GY7VnlW0jUkU6Do86jbJrgQkN0nh5tTvmgKOaFotPUmwwGlSKXGT7e4ec6cXj2KzxWJumUKsUPAK6QLwbctfSK/pifUZ89DRH+t8mW8+plU=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1766052905; c=relaxed/simple;\n\tbh=bUrOudaBNEyNMrDDCs/9pJg9ZvlHYmUGDr+eXIjrMyo=;\n\th=From:Subject:Date:Message-Id:MIME-Version:Content-Type:To:Cc;\n b=Au+jorhSbfUBydshPTuT9Mdo1MzdlrVEs57O1Ak9pnjeDYPSB9PiXmJp7fvzVjxfj4NPL7cTCfenNr3pJVNBO6E3JaMy54Hd+0hY7RetiDq+/kI8BAId/+P/ClXceqG46njGkGq8YnLVdSd2I5Tk7NnCpNVyXNiJDo+qrt+62VY=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=Rg678wxJ; arc=none smtp.client-ip=10.30.226.201", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org;\n\ts=k20201202; t=1766052904;\n\tbh=bUrOudaBNEyNMrDDCs/9pJg9ZvlHYmUGDr+eXIjrMyo=;\n\th=From:Subject:Date:To:Cc:From;\n\tb=Rg678wxJlwP2XtXO1kbmDVfmPFRvx3qUSeWXchI0F55x5wmP53dUVUIXohf5Zbu+n\n\t ZfIsju8wp3+Y4bDyqpgBhNRR0H8cIkzilNOtzeh9QI4DMxbEFMCeZDHDAp5wyYjl+n\n\t xNrZp+D0ETul3gohzeUtwdl+celqsdWG7rEEBX8Ak4+rlZdcCLLeBK6+eV5mQWV0oE\n\t A1F+SaXu5/TZhB9hSM+K0GOhqkK6BsEKaajGX4B9jqGPx6ZwoBKKo1Vp+cwSObHrby\n\t 1aHe8SRtbr7EAFu8WLs/oHY8uCBUKdAzqD9nbVB/0J9A8fXZD29doqSZb+l0G9ADeu\n\t 7w8nMhIlAva+w==", "From": "Lorenzo Pieralisi <lpieralisi@kernel.org>", "Subject": "[PATCH v2 0/7] irqchip/gic-v5: Code first ACPI boot support", "Date": "Thu, 18 Dec 2025 11:14:26 +0100", "Message-Id": "<20251218-gicv5-host-acpi-v2-0-eec76cd1d40b@kernel.org>", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "X-B4-Tracking": "v=1; b=H4sIAALUQ2kC/2WNQQrCMBBFr1Jm7UgSSa2ueg/pIibTZlCSkpSgl\n N7dWHDl8j3476+QKTFluDYrJCqcOYYK6tCA9SZMhOwqgxJKS6EUTmyLRh/zgsbOjE5fXGulOzl\n xhrqaE4382ou3obLnvMT03g+K/Npfq/trFYkChTRdq0a6a2v6B6VAz2NMEwzbtn0AzUKfja8AA\n AA=", "X-Change-ID": "20251022-gicv5-host-acpi-d59d6c1d3d07", "To": "\"Rafael J. Wysocki\" <rafael@kernel.org>, Len Brown <lenb@kernel.org>,\n Robert Moore <robert.moore@intel.com>, Thomas Gleixner <tglx@linutronix.de>,\n Hanjun Guo <guohanjun@huawei.com>, Sudeep Holla <sudeep.holla@arm.com>,\n Marc Zyngier <maz@kernel.org>, Bjorn Helgaas <bhelgaas@google.com>", "Cc": "linux-acpi@vger.kernel.org, acpica-devel@lists.linux.dev,\n linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org,\n linux-pci@vger.kernel.org, Lorenzo Pieralisi <lpieralisi@kernel.org>,\n Jose Marinho <jose.marinho@arm.com>", "X-Mailer": "b4 0.14.3" }, "content": "The ACPI and ACPI IORT specifications were updated to support bindings\nrequired to describe GICv5 based systems.\n\nThe ACPI specification GICv5 bindings ECR [1] were approved and the\nrequired changes merged in the ACPICA upstream repository[5].\n\nThe Arm IORT specification [2] has been updated to include GICv5 IWB\nspecific bindings in revision E.g.\n\nImplement kernel code that - based on the aforementioned bindings - adds\nsupport for GICv5 ACPI probing.\n\nACPICA changes supporting the bindings are posted with the series; they\nwere cherry-picked from the upcoming ACPICA Linuxised release patches\nand they should _not_ be merged in any upstream branch because the\nfull set of Linuxised ACPICA changes will be subsequently posted in\norder to be merged, I added the two ACPICA patches to make the series\nself-contained.\n\nThe ACPI bindings were prototyped in edk2 - code available in these\nbranches [3][4].\n\n===========================\nKernel implementation notes\n===========================\n\nIRS and ITS probing is triggered using the standard irqchip ACPI probing\nmechanism - there is no significant difference compared to previous GIC\nversions other.\n\nThe only difference that is worth noting is that GICv3/4 systems include a\nsingle MADT component describing the interrupt controller (ie GIC distributor)\nwhereas GICv5 systems include one or more IRSes. The probing code is\nimplemented so that an MADT IRS detection triggers probing for all IRSes\nin one go.\n\nThe IWB driver probes like any other ACPI device. IORT code is updated so\nthat a deviceID for the IWB can be detected.\n\nThe only major change compared to GICv3/4 systems is the GSI namespace that\nis split between PPI/SPI IRQs and IWB backed IRQs.\n\nThe main GSI handle - to map an IRQ - has to detect whether to look-up\nusing the top level GSI domain or an IWB domain in that the two IRQ\nnamespaces are decoupled.\n\nIORT code implements the logic to retrieve an IWB domain by looking up its\nIWB frame id, as described in [1].\n\nMost important implementation detail worth noting is that - at this stage -\nACPI code is not capable of handling devices probe order IRQ dependency on\nthe interrupt controller driver their IRQ is routed to.\n\nThis is not an issue on GICv3/4 systems in that the full GIC hierarchy\nprobes earlier than any other device, so by the time IRQs mappings have to\nbe carried out (ie acpi_register_gsi()) the GIC drivers have already\nprobed.\n\nOn GICv5 systems, the IWB is modelled as a device and its device driver\nprobes at device_initcall time. That's when the IWB IRQ domain is actually\nregistered - which poses problems for devices whose IRQs are IWB routed and\nrequire to resolve the IRQ mapping before the IWB driver has a chance to\nprobe.\n\nWork on resolving devices<->IWB probe order dependency has started in\nparallel with this series and will be posted shortly.\n\nFor PPI/SPI/LPI backed IRQs the probe dependency is not a problem because\nin GICv5 systems the IRSes and ITSes probe early so their IRQ domain are\nset in place before devices require IRQ mappings.\n\nACPICA patches are a Linuxised version of ACPICA GICv5 upstream changes\n[5] and should not be considered for merging because they would conflict\nwith the full ACPICA release changes patchset that will be posted later\nin this dev cycle (owing to patch dependencies in the ACPICA commit\nhistory) they are there so that the patch series is self-contained.\n\n[1] https://github.com/tianocore/edk2/issues/11148\n[2] https://developer.arm.com/documentation/den0049/eg\n[3] https://github.com/LeviYeoReum/edk2/tree/levi/gicv5_patch\n[4] https://github.com/LeviYeoReum/edk2-platforms/tree/levi/gicv5_patch\n[5] https://github.com/acpica/acpica/commits/master/\n\nSigned-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>\n---\nChanges in v2:\n- Cherry-picked ACPICA upstream changes\n- Minor editorial changes\n- Removed the \"not for merging\" tag because now ACPI specs are approved\n- Rebased against v6.19-rc1\n- Link to v1: https://lore.kernel.org/r/20251028-gicv5-host-acpi-v1-0-01a862feb5ca@kernel.org\n\n---\nJose Marinho (2):\n ACPICA: Add GICv5 MADT structures\n ACPICA: Add Arm IORT IWB node definitions\n\nLorenzo Pieralisi (5):\n irqdomain: Add parent field to struct irqchip_fwid\n PCI/MSI: Make the pci_msi_map_rid_ctlr_node() interface firmware agnostic\n irqchip/gic-v5: Add ACPI IRS probing\n irqchip/gic-v5: Add ACPI ITS probing\n irqchip/gic-v5: Add ACPI IWB probing\n\n drivers/acpi/arm64/iort.c | 190 +++++++++++++++++++-----\n drivers/acpi/bus.c | 3 +\n drivers/irqchip/irq-gic-its-msi-parent.c | 43 +++---\n drivers/irqchip/irq-gic-v5-irs.c | 246 ++++++++++++++++++++++++-------\n drivers/irqchip/irq-gic-v5-its.c | 132 ++++++++++++++++-\n drivers/irqchip/irq-gic-v5-iwb.c | 42 ++++--\n drivers/irqchip/irq-gic-v5.c | 138 ++++++++++++++---\n drivers/pci/msi/irqdomain.c | 24 ++-\n include/acpi/actbl2.h | 56 ++++++-\n include/linux/acpi.h | 1 +\n include/linux/acpi_iort.h | 11 +-\n include/linux/irqchip/arm-gic-v5.h | 8 +\n include/linux/irqdomain.h | 30 +++-\n include/linux/msi.h | 3 +-\n kernel/irq/irqdomain.c | 14 +-\n 15 files changed, 784 insertions(+), 157 deletions(-)\n---\nbase-commit: 8f0b4cce4481fb22653697cced8d0d04027cb1e8\nchange-id: 20251022-gicv5-host-acpi-d59d6c1d3d07\n\nBest regards," }