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{ "id": 2175318, "url": "http://patchwork.ozlabs.org/api/1.0/covers/2175318/?format=api", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/1.0/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20251217190018.487429-1-rdapp@ventanamicro.com>", "date": "2025-12-17T19:00:14", "name": "[v3,0/4] VLS-related stuff.", "submitter": { "id": 86205, "url": "http://patchwork.ozlabs.org/api/1.0/people/86205/?format=api", "name": "Robin Dapp", "email": "rdapp.gcc@gmail.com" }, "series": [ { "id": 485748, "url": "http://patchwork.ozlabs.org/api/1.0/series/485748/?format=api", "date": "2025-12-17T19:00:18", "name": "VLS-related stuff.", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/485748/mbox/" } ], "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20230601 header.b=DcTNEjNl;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=38.145.34.32; helo=vm01.sourceware.org;\n envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org;\n receiver=patchwork.ozlabs.org)", "sourceware.org;\n\tdkim=pass (2048-bit key,\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20230601 header.b=DcTNEjNl", "sourceware.org;\n dmarc=pass (p=none dis=none) header.from=gmail.com", "sourceware.org; spf=pass smtp.mailfrom=gmail.com", "server2.sourceware.org;\n arc=none smtp.remote-ip=209.85.218.44" ], "Received": [ "from vm01.sourceware.org (vm01.sourceware.org [38.145.34.32])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4dWjp75bgkz1xty\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 18 Dec 2025 06:01:51 +1100 (AEDT)", "from vm01.sourceware.org (localhost [127.0.0.1])\n\tby sourceware.org (Postfix) with ESMTP id 9D64D4BA2E3D\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 17 Dec 2025 19:01:40 +0000 (GMT)", "from mail-ej1-f44.google.com (mail-ej1-f44.google.com\n [209.85.218.44])\n by sourceware.org (Postfix) with ESMTPS id 8E9714BA2E05\n for <gcc-patches@gcc.gnu.org>; Wed, 17 Dec 2025 19:00:22 +0000 (GMT)", "by mail-ej1-f44.google.com with SMTP id\n a640c23a62f3a-b736ffc531fso1179670566b.1\n for <gcc-patches@gcc.gnu.org>; Wed, 17 Dec 2025 11:00:22 -0800 (PST)", "from x1c10.dc1.ventanamicro.com\n (ip-149-172-150-237.um42.pools.vodafone-ip.de. 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The select_vl patch didn't show the intended\ncodegen improvements and the benefits of a length-controlled loop are\nalready available through the added VLS modes in patch 3.\n\nIt might be useful to have an additional control flag that enables or disables \nlength control for VLS modes but that's not part of this series. I guess we \nshould talk about that in the patchwork sync meeting.\n\nMost changes from v2 address reviewer comments, i.e. adding tests as well as \nclarifying comments.\n\nI regtested the series on rv64gcv_zvl512b with a bit of fallout. As noted \nbefore all of it is harmless and doesn't constitute code-gen degradation so\nI'm inclined to go ahead with it.\n\nRobin Dapp (4):\n RISC-V: Change gather/scatter iterators.\n RISC-V: Rename vector-mode related functions.\n RISC-V: Add VLS modes to autovec iterators.\n RISC-V: Generic vec_extract via subreg.\n\n gcc/config/riscv/autovec-opt.md | 22 +-\n gcc/config/riscv/autovec.md | 310 ++--\n gcc/config/riscv/riscv-avlprop.cc | 2 +-\n gcc/config/riscv/riscv-protos.h | 6 +-\n gcc/config/riscv/riscv-selftests.cc | 8 +-\n gcc/config/riscv/riscv-v.cc | 250 ++-\n .../riscv/riscv-vector-builtins-bases.cc | 66 +-\n gcc/config/riscv/riscv-vector-builtins.cc | 4 +-\n gcc/config/riscv/riscv-vector-costs.cc | 22 +-\n gcc/config/riscv/riscv.cc | 104 +-\n gcc/config/riscv/vector-crypto.md | 172 +-\n gcc/config/riscv/vector-iterators.md | 1519 ++++++++++++++++-\n gcc/config/riscv/vector.md | 186 +-\n .../autovec/gather-scatter/strided_store-2.c | 3 +-\n .../riscv/rvv/autovec/param-autovec-mode.c | 2 +-\n .../riscv/rvv/autovec/partial/select_vl-2.c | 4 +-\n .../riscv/rvv/autovec/subreg-extract.c | 19 +\n .../gcc.target/riscv/rvv/autovec/zve64d-1.c | 5 +-\n .../gcc.target/riscv/rvv/autovec/zve64f-1.c | 5 +-\n 19 files changed, 2133 insertions(+), 576 deletions(-)\n create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/subreg-extract.c" }