From patchwork Mon Mar 18 07:41:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anson Huang X-Patchwork-Id: 1057709 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=nxp.com header.i=@nxp.com header.b="wARcDY5q"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44N7RV2yjCz9sBF for ; Mon, 18 Mar 2019 18:41:42 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727471AbfCRHlg (ORCPT ); Mon, 18 Mar 2019 03:41:36 -0400 Received: from mail-eopbgr00044.outbound.protection.outlook.com ([40.107.0.44]:57158 "EHLO EUR02-AM5-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727086AbfCRHlg (ORCPT ); Mon, 18 Mar 2019 03:41:36 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=IKZbQGKmXMprG/U6J+8vXsk40x3k1U4ZvFk+bQ3EPQY=; b=wARcDY5qk47L24PLNDoy8C7DnriXLRqVCOr8dafWJ0iHU93DFZOrZE7nLzFC0WpyIfOBZMPDXa+fxV1ZiMGyddPxg6s+DJKbkrvB9FwAZ9gE3WUefYTCseOM1FOJMJrQa2WctZp8mu7j1+xRkUdtEkG3folsAY7l5y817XG1Ank= Received: from DB3PR0402MB3916.eurprd04.prod.outlook.com (52.134.72.18) by DB3PR0402MB3868.eurprd04.prod.outlook.com (52.134.71.147) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1709.14; Mon, 18 Mar 2019 07:41:33 +0000 Received: from DB3PR0402MB3916.eurprd04.prod.outlook.com ([fe80::f1b4:a1fb:cfd1:3f08]) by DB3PR0402MB3916.eurprd04.prod.outlook.com ([fe80::f1b4:a1fb:cfd1:3f08%6]) with mapi id 15.20.1709.015; Mon, 18 Mar 2019 07:41:33 +0000 From: Anson Huang To: "thierry.reding@gmail.com" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "shawnguo@kernel.org" , "s.hauer@pengutronix.de" , "kernel@pengutronix.de" , "festevam@gmail.com" , "linux@armlinux.org.uk" , "otavio@ossystems.com.br" , "stefan@agner.ch" , Leonard Crestez , Robin Gong , "jan.tuerk@emtrion.com" , "linux-pwm@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "u.kleine-koenig@pengutronix.de" CC: dl-linux-imx Subject: [PATCH V5 1/5] dt-bindings: pwm: Add i.MX TPM PWM binding Thread-Topic: [PATCH V5 1/5] dt-bindings: pwm: Add i.MX TPM PWM binding Thread-Index: AQHU3V4B0+Op6lebhUq7cDF33YTb6g== Date: Mon, 18 Mar 2019 07:41:32 +0000 Message-ID: <1552894581-3391-2-git-send-email-Anson.Huang@nxp.com> References: <1552894581-3391-1-git-send-email-Anson.Huang@nxp.com> In-Reply-To: <1552894581-3391-1-git-send-email-Anson.Huang@nxp.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.7.4 x-clientproxiedby: HK2PR0401CA0011.apcprd04.prod.outlook.com (2603:1096:202:2::21) To DB3PR0402MB3916.eurprd04.prod.outlook.com (2603:10a6:8:10::18) authentication-results: spf=none (sender IP is ) smtp.mailfrom=anson.huang@nxp.com; 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DIR:OUT; SFP:1101; SCL:1; SRVR:DB3PR0402MB3868; H:DB3PR0402MB3916.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: qNn/ZSc50jUrx5xMUwGJhYoShz0dFvMKj2rH5n5Kv+qUppjb4jWH/PpKiHlj74Ppq4K2lolYvjFgFnigAgpsZaOLfUp+38WtGVFUtfS1U6vNQHzsG8ghF/LnhcJ/kd80yUL/aAHX+6wQAcH3uK2QF6jzD0v9HtmbWkrzRh8FDgwnA7zmKLDImbaBk4m5NJl77YTXvm9bPTLZV2m1Bc1+1VXywL3hAc+XWeJxQuDUklyb68H0WOwlR59mjIETO2Gh71FajLWbQXFSZR4fZqc65iXe6AN4XDz67vVzFU36x/HqnvKurm5is/bkzg4ibDkp5BEfs8HdGuJOO/mbkzTdGnnL3Ya7cZEp9Snp5b0J+18oslW1lr6HiqoCQJ/I75m1recZG83gWkm+QBBHe/rjj9jZ8oZ6t2Nx5ptgzIjimdw= MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: a776c782-b22e-4459-ae6f-08d6ab75241d X-MS-Exchange-CrossTenant-originalarrivaltime: 18 Mar 2019 07:41:33.0195 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB3PR0402MB3868 Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org Add i.MX TPM(Low Power Timer/Pulse Width Modulation Module) PWM binding. Signed-off-by: Anson Huang --- No changes. --- Documentation/devicetree/bindings/pwm/imx-tpm-pwm.txt | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/imx-tpm-pwm.txt diff --git a/Documentation/devicetree/bindings/pwm/imx-tpm-pwm.txt b/Documentation/devicetree/bindings/pwm/imx-tpm-pwm.txt new file mode 100644 index 0000000..d47b8fb --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/imx-tpm-pwm.txt @@ -0,0 +1,19 @@ +Freescale i.MX TPM PWM controller + +Required properties: +- compatible : Should be "fsl,imx-tpm-pwm". +- reg: Physical base address and length of the controller's registers. +- #pwm-cells: Should be 2. See pwm.txt in this directory for a description of the cells format. +- clocks : The clock provided by the SoC to drive the PWM. +- interrupts: The interrupt for the pwm controller. + +Example: + +pwm0: tpm@40250000 { + compatible = "fsl,imx-tpm-pwm"; + reg = <0x40250000 0x1000>; + assigned-clocks = <&clks IMX7ULP_CLK_LPTPM4>; + assigned-clock-parents = <&clks IMX7ULP_CLK_SOSC_BUS_CLK>; + clocks = <&clks IMX7ULP_CLK_LPTPM4>; + #pwm-cells = <2>; +}; From patchwork Mon Mar 18 07:41:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anson Huang X-Patchwork-Id: 1057711 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: ozlabs.org; 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Mon, 18 Mar 2019 07:41:43 +0000 Received: from DB3PR0402MB3916.eurprd04.prod.outlook.com ([fe80::f1b4:a1fb:cfd1:3f08]) by DB3PR0402MB3916.eurprd04.prod.outlook.com ([fe80::f1b4:a1fb:cfd1:3f08%6]) with mapi id 15.20.1709.015; Mon, 18 Mar 2019 07:41:43 +0000 From: Anson Huang To: "thierry.reding@gmail.com" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "shawnguo@kernel.org" , "s.hauer@pengutronix.de" , "kernel@pengutronix.de" , "festevam@gmail.com" , "linux@armlinux.org.uk" , "otavio@ossystems.com.br" , "stefan@agner.ch" , Leonard Crestez , Robin Gong , "jan.tuerk@emtrion.com" , "linux-pwm@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "u.kleine-koenig@pengutronix.de" CC: dl-linux-imx Subject: [PATCH V5 2/5] pwm: Add i.MX TPM PWM driver support Thread-Topic: [PATCH V5 2/5] pwm: Add i.MX TPM PWM driver support Thread-Index: AQHU3V4HX7PmOfUc/UqPD4q30kCHQw== Date: Mon, 18 Mar 2019 07:41:42 +0000 Message-ID: <1552894581-3391-3-git-send-email-Anson.Huang@nxp.com> References: <1552894581-3391-1-git-send-email-Anson.Huang@nxp.com> In-Reply-To: <1552894581-3391-1-git-send-email-Anson.Huang@nxp.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.7.4 x-clientproxiedby: HK2PR0401CA0011.apcprd04.prod.outlook.com (2603:1096:202:2::21) To DB3PR0402MB3916.eurprd04.prod.outlook.com (2603:10a6:8:10::18) authentication-results: spf=none (sender IP is ) smtp.mailfrom=anson.huang@nxp.com; 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DIR:OUT; SFP:1101; SCL:1; SRVR:DB3PR0402MB3868; H:DB3PR0402MB3916.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: RVJPMPL3RYTJGwF3pIMG5F/yX++aV/7nDl4eBek1QnG77YNGSHioY69m08Dw1SSWBG8VSx2NRP0aHbxaaBkkUfWTVi+3JhGVz/eF+D3ukilyS36VLsGvbjnKFON4vd2GY+1LluevsOnjTRqVHsX39edrm5Ylt+hY1scmZDEXpTfz0VR3y0uesBe5TYEpnYTRqwwDUhXlmMYIEQOWDITDWA5pP3xHLn4l7SYpGptBu2jW2Iixrpd/Tc9fLHR4y2PLh7F84QD7mxQuqpDm3xERQ9Q0FvQ0x1vyQga43g/zOZpHGE+WuUVi7eUS5IOHm86pEKPKyhJUBQI+BoIFBdvrHZSGDlCqttziH2HLKpAJDN5LifYZfw5A0oFrkek7YtQFowm8O2OnCgLrN3zyozoRQhvVEFHVx9+UxstnjbUk2qM= MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 8c5ac754-4e85-4f0e-37be-08d6ab7529fc X-MS-Exchange-CrossTenant-originalarrivaltime: 18 Mar 2019 07:41:42.8355 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB3PR0402MB3868 Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org i.MX7ULP has TPM(Low Power Timer/Pulse Width Modulation Module) inside, add TPM PWM driver support. Signed-off-by: Anson Huang --- Changes since V4: - improve register read/write using bit field operations; - correct some logic issue; - ONLY disable clock when PWM is NOT in use during suspend; - add some comments for PWM mode settings; - fix some spelling errors; - reading channel number from register instead of using fix value. --- drivers/pwm/Kconfig | 11 ++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-imx-tpm.c | 436 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 448 insertions(+) create mode 100644 drivers/pwm/pwm-imx-tpm.c diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 54f8238..3ea0391 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -210,6 +210,17 @@ config PWM_IMX27 To compile this driver as a module, choose M here: the module will be called pwm-imx27. +config PWM_IMX_TPM + tristate "i.MX TPM PWM support" + depends on ARCH_MXC || COMPILE_TEST + depends on HAVE_CLK && HAS_IOMEM + help + Generic PWM framework driver for i.MX7ULP TPM module, TPM's full + name is Low Power Timer/Pulse Width Modulation Module. + + To compile this driver as a module, choose M here: the module + will be called pwm-imx-tpm. + config PWM_JZ4740 tristate "Ingenic JZ47xx PWM support" depends on MACH_INGENIC diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 448825e..c368599 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -19,6 +19,7 @@ obj-$(CONFIG_PWM_HIBVT) += pwm-hibvt.o obj-$(CONFIG_PWM_IMG) += pwm-img.o obj-$(CONFIG_PWM_IMX1) += pwm-imx1.o obj-$(CONFIG_PWM_IMX27) += pwm-imx27.o +obj-$(CONFIG_PWM_IMX_TPM) += pwm-imx-tpm.o obj-$(CONFIG_PWM_JZ4740) += pwm-jz4740.o obj-$(CONFIG_PWM_LP3943) += pwm-lp3943.o obj-$(CONFIG_PWM_LPC18XX_SCT) += pwm-lpc18xx-sct.o diff --git a/drivers/pwm/pwm-imx-tpm.c b/drivers/pwm/pwm-imx-tpm.c new file mode 100644 index 0000000..12cb16c --- /dev/null +++ b/drivers/pwm/pwm-imx-tpm.c @@ -0,0 +1,436 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2018-2019 NXP. + * + * Limitations: + * - The TPM counter and period counter are shared between + * multiple channels, so all channels should use same period + * settings. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PWM_IMX_TPM_PARAM 0x4 +#define PWM_IMX_TPM_GLOBAL 0x8 +#define PWM_IMX_TPM_SC 0x10 +#define PWM_IMX_TPM_CNT 0x14 +#define PWM_IMX_TPM_MOD 0x18 +#define PWM_IMX_TPM_C0SC 0x20 +#define PWM_IMX_TPM_C0V 0x24 + +#define PWM_IMX_TPM_PARAM_CHAN GENMASK(7, 0) + +#define PWM_IMX_TPM_SC_PS GENMASK(2, 0) +#define PWM_IMX_TPM_SC_CMOD GENMASK(4, 3) +#define PWM_IMX_TPM_SC_CMOD_INC_EVERY_CLK BIT(3) +#define PWM_IMX_TPM_SC_CPWMS BIT(5) + +#define PWM_IMX_TPM_CnSC_CHF BIT(7) +#define PWM_IMX_TPM_CnSC_MSB BIT(5) +#define PWM_IMX_TPM_CnSC_MSA BIT(4) +#define PWM_IMX_TPM_CnSC_ELSB BIT(3) +#define PWM_IMX_TPM_CnSC_ELSA BIT(2) + +#define PWM_IMX_TPM_MOD_MOD GENMASK(15, 0) + +#define PWM_IMX_TPM_MAX_COUNT 0xffff + +#define PWM_IMX_TPM_MAX_CHANNEL_NUM 6 + +#define PWM_IMX_TPM_CnSC(n) (PWM_IMX_TPM_C0SC + (n) * 0x8) +#define PWM_IMX_TPM_CnV(n) (PWM_IMX_TPM_C0V + (n) * 0x8) + +struct imx_tpm_pwm_chip { + struct pwm_chip chip; + struct clk *clk; + void __iomem *base; + struct mutex lock; + u32 user_count; + u32 enable_count; + u32 chn_config[PWM_IMX_TPM_MAX_CHANNEL_NUM]; + bool chn_status[PWM_IMX_TPM_MAX_CHANNEL_NUM]; +}; + +#define to_imx_tpm_pwm_chip(_chip) \ + container_of(_chip, struct imx_tpm_pwm_chip, chip) + +static int pwm_imx_tpm_config_counter(struct pwm_chip *chip, u32 period) +{ + struct imx_tpm_pwm_chip *tpm = to_imx_tpm_pwm_chip(chip); + u32 period_cnt, val, div, saved_cmod; + u64 tmp; + + tmp = clk_get_rate(tpm->clk); + tmp *= period; + val = DIV_ROUND_CLOSEST_ULL(tmp, NSEC_PER_SEC); + if (val <= PWM_IMX_TPM_MAX_COUNT) + div = 0; + else + div = ilog2(roundup_pow_of_two(val / + (PWM_IMX_TPM_MAX_COUNT + 1))); + if ((!FIELD_FIT(PWM_IMX_TPM_SC_PS, div))) { + dev_err(chip->dev, + "failed to find valid prescale value!\n"); + return -EINVAL; + } + + /* make sure counter is disabled for programming prescale */ + val = readl(tpm->base + PWM_IMX_TPM_SC); + saved_cmod = FIELD_GET(PWM_IMX_TPM_SC_CMOD, val); + if (saved_cmod) { + val &= ~PWM_IMX_TPM_SC_CMOD; + writel(val, tpm->base + PWM_IMX_TPM_SC); + } + + /* set TPM counter prescale */ + val = readl(tpm->base + PWM_IMX_TPM_SC); + val &= ~PWM_IMX_TPM_SC_PS; + val |= FIELD_PREP(PWM_IMX_TPM_SC_PS, div); + writel(val, tpm->base + PWM_IMX_TPM_SC); + + /* + * set period counter: according to RM, the MOD register is + * updated immediately after CMOD[1:0] = 2b'00 above + */ + do_div(tmp, NSEC_PER_SEC); + period_cnt = (tmp + ((1 << div) >> 1)) >> div; + if (period_cnt > PWM_IMX_TPM_MOD_MOD) { + dev_err(chip->dev, + "failed to find valid period count!\n"); + return -EINVAL; + } + writel(period_cnt, tpm->base + PWM_IMX_TPM_MOD); + + /* restore the clock mode if necessary */ + if (saved_cmod) { + val = readl(tpm->base + PWM_IMX_TPM_SC); + val |= FIELD_PREP(PWM_IMX_TPM_SC_CMOD, saved_cmod); + writel(val, tpm->base + PWM_IMX_TPM_SC); + } + + return 0; +} + +static void pwm_imx_tpm_config(struct pwm_chip *chip, + struct pwm_device *pwm, + u32 period, + u32 duty_cycle, + enum pwm_polarity polarity) +{ + struct imx_tpm_pwm_chip *tpm = to_imx_tpm_pwm_chip(chip); + u32 duty_cnt, val; + u64 tmp; + + /* set duty counter */ + tmp = readl(tpm->base + PWM_IMX_TPM_MOD) & PWM_IMX_TPM_MOD_MOD; + tmp *= duty_cycle; + duty_cnt = DIV_ROUND_CLOSEST_ULL(tmp, period); + writel(duty_cnt & PWM_IMX_TPM_MOD_MOD, + tpm->base + PWM_IMX_TPM_CnV(pwm->hwpwm)); + + /* + * set polarity (for edge-aligned PWM modes) + * + * CPWMS MSB:MSA ELSB:ELSA Mode Configuration + * 0 10 10 PWM High-true pulse + * 0 10 00 PWM Reserved + * 0 10 01 PWM Low-true pulse + * 0 10 11 PWM Reserved + * + * High-true pulse: clear output on counter match, set output on + * counter reload, set output when counter first enabled or paused. + * + * Low-true pulse: set output on counter match, clear output on + * counter reload, clear output when counter first enabled or paused. + */ + + val = readl(tpm->base + PWM_IMX_TPM_CnSC(pwm->hwpwm)); + val &= ~(PWM_IMX_TPM_CnSC_ELSB | PWM_IMX_TPM_CnSC_ELSA | + PWM_IMX_TPM_CnSC_MSA); + val |= PWM_IMX_TPM_CnSC_MSB; + val |= (polarity == PWM_POLARITY_NORMAL) ? + PWM_IMX_TPM_CnSC_ELSB : PWM_IMX_TPM_CnSC_ELSA; + /* + * polarity settings will enabled/disable output status + * immediately, so here ONLY save the config and write + * it into register when channel is enabled/disabled. + */ + tpm->chn_config[pwm->hwpwm] = val; +} + +/* + * When a channel's polarity is configured, the polarity settings + * will be saved and ONLY write into the register when the channel + * is enabled. + * + * When a channel is disabled, its polarity settings will be saved + * and its output will be disabled by clearing polarity settings. + * + * when a channel is enabled, its polarity settings will be restored + * and output will be enabled again. + */ +static void pwm_imx_tpm_enable(struct pwm_chip *chip, + struct pwm_device *pwm, + bool enable) +{ + struct imx_tpm_pwm_chip *tpm = to_imx_tpm_pwm_chip(chip); + u32 val; + + val = readl(tpm->base + PWM_IMX_TPM_SC); + if (enable) { + /* restore channel config */ + writel(tpm->chn_config[pwm->hwpwm], + tpm->base + PWM_IMX_TPM_CnSC(pwm->hwpwm)); + + if (++tpm->enable_count == 1) { + /* start TPM counter */ + val |= PWM_IMX_TPM_SC_CMOD_INC_EVERY_CLK; + writel(val, tpm->base + PWM_IMX_TPM_SC); + } + } else { + /* disable channel */ + val = readl(tpm->base + PWM_IMX_TPM_CnSC(pwm->hwpwm)); + val &= ~(PWM_IMX_TPM_CnSC_MSA | PWM_IMX_TPM_CnSC_MSB | + PWM_IMX_TPM_CnSC_ELSB | PWM_IMX_TPM_CnSC_ELSA); + writel(val, tpm->base + PWM_IMX_TPM_CnSC(pwm->hwpwm)); + + if (--tpm->enable_count == 0) { + /* stop TPM counter since all channels are disabled */ + val &= ~PWM_IMX_TPM_SC_CMOD; + writel(val, tpm->base + PWM_IMX_TPM_SC); + } + } + + /* update channel status */ + tpm->chn_status[pwm->hwpwm] = enable; +} + +static void pwm_imx_tpm_get_state(struct pwm_chip *chip, + struct pwm_device *pwm, + struct pwm_state *state) +{ + struct imx_tpm_pwm_chip *tpm = to_imx_tpm_pwm_chip(chip); + u64 tmp; + u32 val, rate; + + /* get period */ + rate = clk_get_rate(tpm->clk); + tmp = readl(tpm->base + PWM_IMX_TPM_MOD); + val = readl(tpm->base + PWM_IMX_TPM_SC); + val &= PWM_IMX_TPM_SC_PS; + tmp *= (1 << val) * NSEC_PER_SEC; + state->period = DIV_ROUND_CLOSEST_ULL(tmp, rate); + + /* get duty cycle */ + tmp = readl(tpm->base + PWM_IMX_TPM_CnV(pwm->hwpwm)); + tmp *= (1 << val) * NSEC_PER_SEC; + state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, rate); + + /* get polarity */ + val = readl(tpm->base + PWM_IMX_TPM_CnSC(pwm->hwpwm)); + if (val & PWM_IMX_TPM_CnSC_ELSA) + state->polarity = PWM_POLARITY_INVERSED; + else + state->polarity = PWM_POLARITY_NORMAL; + + /* get channel status */ + state->enabled = tpm->chn_status[pwm->hwpwm] ? true : false; +} + +static int pwm_imx_tpm_apply(struct pwm_chip *chip, struct pwm_device *pwm, + struct pwm_state *state) +{ + struct imx_tpm_pwm_chip *tpm = to_imx_tpm_pwm_chip(chip); + struct pwm_state curstate; + int ret; + + mutex_lock(&tpm->lock); + + pwm_imx_tpm_get_state(chip, pwm, &curstate); + + if (state->period != curstate.period) { + /* + * TPM counter is shared by multiple channels, so + * prescale and period can NOT be modified when + * there are multiple channels in use. + */ + if (tpm->user_count != 1) + return -EBUSY; + ret = pwm_imx_tpm_config_counter(chip, state->period); + if (ret) + return ret; + } + + if (state->enabled == false) { + /* + * if eventually the PWM output is LOW, either + * duty cycle is 0 or status is disabled, need + * to make sure the output pin is LOW. + */ + pwm_imx_tpm_config(chip, pwm, state->period, + 0, state->polarity); + if (curstate.enabled) + pwm_imx_tpm_enable(chip, pwm, false); + } else { + pwm_imx_tpm_config(chip, pwm, state->period, + state->duty_cycle, state->polarity); + if (!curstate.enabled) + pwm_imx_tpm_enable(chip, pwm, true); + } + + mutex_unlock(&tpm->lock); + + return 0; +} + +static int pwm_imx_tpm_request(struct pwm_chip *chip, struct pwm_device *dev) +{ + struct imx_tpm_pwm_chip *tpm = to_imx_tpm_pwm_chip(chip); + + mutex_lock(&tpm->lock); + tpm->user_count++; + mutex_unlock(&tpm->lock); + + return 0; +} + +static void pwm_imx_tpm_free(struct pwm_chip *chip, struct pwm_device *dev) +{ + struct imx_tpm_pwm_chip *tpm = to_imx_tpm_pwm_chip(chip); + + mutex_lock(&tpm->lock); + tpm->user_count--; + mutex_unlock(&tpm->lock); +} + +static const struct pwm_ops imx_tpm_pwm_ops = { + .request = pwm_imx_tpm_request, + .free = pwm_imx_tpm_free, + .get_state = pwm_imx_tpm_get_state, + .apply = pwm_imx_tpm_apply, + .owner = THIS_MODULE, +}; + +static int pwm_imx_tpm_probe(struct platform_device *pdev) +{ + struct imx_tpm_pwm_chip *tpm; + int ret; + u32 val; + + tpm = devm_kzalloc(&pdev->dev, sizeof(*tpm), GFP_KERNEL); + if (!tpm) + return -ENOMEM; + + platform_set_drvdata(pdev, tpm); + + tpm->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(tpm->base)) { + ret = PTR_ERR(tpm->base); + if (ret != -EPROBE_DEFER) + dev_err(&pdev->dev, "pwm ioremap failed %d\n", ret); + return ret; + } + + tpm->clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(tpm->clk)) { + ret = PTR_ERR(tpm->clk); + if (ret != -EPROBE_DEFER) + dev_err(&pdev->dev, "failed to get pwm clk %d\n", ret); + return ret; + } + + ret = clk_prepare_enable(tpm->clk); + if (ret) { + dev_err(&pdev->dev, + "failed to prepare or enable clk %d\n", ret); + return ret; + } + + tpm->chip.dev = &pdev->dev; + tpm->chip.ops = &imx_tpm_pwm_ops; + tpm->chip.base = -1; + /* get channel number */ + val = readl(tpm->base + PWM_IMX_TPM_PARAM); + tpm->chip.npwm = FIELD_GET(PWM_IMX_TPM_PARAM_CHAN, val); + + mutex_init(&tpm->lock); + + ret = pwmchip_add(&tpm->chip); + if (ret) { + dev_err(&pdev->dev, "failed to add pwm chip %d\n", ret); + clk_disable_unprepare(tpm->clk); + } + + return ret; +} + +static int pwm_imx_tpm_remove(struct platform_device *pdev) +{ + struct imx_tpm_pwm_chip *tpm = platform_get_drvdata(pdev); + int ret = pwmchip_remove(&tpm->chip); + + clk_disable_unprepare(tpm->clk); + + return ret; +} + +static int __maybe_unused pwm_imx_tpm_suspend(struct device *dev) +{ + struct imx_tpm_pwm_chip *tpm = dev_get_drvdata(dev); + + if (tpm->enable_count == 0) + clk_disable_unprepare(tpm->clk); + + return 0; +} + +static int __maybe_unused pwm_imx_tpm_resume(struct device *dev) +{ + struct imx_tpm_pwm_chip *tpm = dev_get_drvdata(dev); + int ret = 0; + + if (tpm->enable_count == 0) { + ret = clk_prepare_enable(tpm->clk); + if (ret) + dev_err(dev, + "failed to prepare or enable clk %d\n", + ret); + } + + return ret; +}; + +static SIMPLE_DEV_PM_OPS(imx_tpm_pwm_pm, + pwm_imx_tpm_suspend, pwm_imx_tpm_resume); + +static const struct of_device_id imx_tpm_pwm_dt_ids[] = { + { .compatible = "fsl,imx-tpm-pwm", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, imx_tpm_pwm_dt_ids); + +static struct platform_driver imx_tpm_pwm_driver = { + .driver = { + .name = "imx-tpm-pwm", + .of_match_table = imx_tpm_pwm_dt_ids, + .pm = &imx_tpm_pwm_pm, + }, + .probe = pwm_imx_tpm_probe, + .remove = pwm_imx_tpm_remove, +}; +module_platform_driver(imx_tpm_pwm_driver); + +MODULE_AUTHOR("Anson Huang "); +MODULE_DESCRIPTION("i.MX TPM PWM Driver"); +MODULE_LICENSE("GPL v2"); From patchwork Mon Mar 18 07:41:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anson Huang X-Patchwork-Id: 1057712 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=nxp.com header.i=@nxp.com header.b="IPwx/p9P"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44N7Rr6kcQz9sBV for ; Mon, 18 Mar 2019 18:42:00 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727553AbfCRHlz (ORCPT ); Mon, 18 Mar 2019 03:41:55 -0400 Received: from mail-eopbgr00067.outbound.protection.outlook.com ([40.107.0.67]:7502 "EHLO EUR02-AM5-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727531AbfCRHly (ORCPT ); Mon, 18 Mar 2019 03:41:54 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=12B47s41r6WVMjNwY2Bys+/e8IDF2fW1ux+7yBvMVWs=; b=IPwx/p9PAdxzDuKM5CI83eHfwCzPaACmNz9T0U+IYr3003KpBSHAjVPSOQWR263OlbDA/jOe/bUqZINTToNeaPLtp85JMhLA30HHUQW7inc8+OhxKFfI/r1CjFl+3UO9D9L7GbiFdsfUxsO1bu/tfpXxRKX8BMxaAPe7rkC4T6Y= Received: from DB3PR0402MB3916.eurprd04.prod.outlook.com (52.134.72.18) by DB3PR0402MB3819.eurprd04.prod.outlook.com (52.134.71.158) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1709.14; Mon, 18 Mar 2019 07:41:51 +0000 Received: from DB3PR0402MB3916.eurprd04.prod.outlook.com ([fe80::f1b4:a1fb:cfd1:3f08]) by DB3PR0402MB3916.eurprd04.prod.outlook.com ([fe80::f1b4:a1fb:cfd1:3f08%6]) with mapi id 15.20.1709.015; Mon, 18 Mar 2019 07:41:51 +0000 From: Anson Huang To: "thierry.reding@gmail.com" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "shawnguo@kernel.org" , "s.hauer@pengutronix.de" , "kernel@pengutronix.de" , "festevam@gmail.com" , "linux@armlinux.org.uk" , "otavio@ossystems.com.br" , "stefan@agner.ch" , Leonard Crestez , Robin Gong , "jan.tuerk@emtrion.com" , "linux-pwm@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "u.kleine-koenig@pengutronix.de" CC: dl-linux-imx Subject: [PATCH V5 3/5] ARM: imx_v6_v7_defconfig: Add TPM PWM support by default Thread-Topic: [PATCH V5 3/5] ARM: imx_v6_v7_defconfig: Add TPM PWM support by default Thread-Index: AQHU3V4MfZ2vurRsVkeU+XGh49tVZg== Date: Mon, 18 Mar 2019 07:41:51 +0000 Message-ID: <1552894581-3391-4-git-send-email-Anson.Huang@nxp.com> References: <1552894581-3391-1-git-send-email-Anson.Huang@nxp.com> In-Reply-To: <1552894581-3391-1-git-send-email-Anson.Huang@nxp.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.7.4 x-clientproxiedby: HK2PR0401CA0011.apcprd04.prod.outlook.com (2603:1096:202:2::21) To DB3PR0402MB3916.eurprd04.prod.outlook.com (2603:10a6:8:10::18) authentication-results: spf=none (sender IP is ) smtp.mailfrom=anson.huang@nxp.com; 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DIR:OUT; SFP:1101; SCL:1; SRVR:DB3PR0402MB3819; H:DB3PR0402MB3916.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: PBLFRuAEVUoR3m4haaAQHFI9jNArbxgIb2gbjNY/y9pYE9H/tPbZo2vYM0TCxfa2y7TnmqMsFgRqy3UMR2CeFplTIXOyzzezgkRnulDLnKT0osRffiVFLQyqGHrAtyeJPTp1UfHQO2K/WNo8Z6r+oPFEwto9jJAkeOCuA2mKapnKI+HthAAPp7OuaSy+pGzTRqlmvAUQGbTgTG6OB1/d7hF13g1eVg+Limquzs1VQxIzBW3V3r5ih9v1TOOnzfSx5/6Vf7TEpxTGK6M/o++mXf6E/KzUqNt1Q7SSVQCzvXkw6ykBKmwIAT9RgLomVWcIBZcLc1p14/KmXw4ZddmlfYJGuZ4FFTpz7gBndAwfTRMMC9nfwGfiLFrPbkSQaFL6179OJWQqcPEDwDJsqABigW5TKqdQ5zwqfsJ4IIkhs8E= MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 370e2fae-3584-43df-5b18-08d6ab752ee7 X-MS-Exchange-CrossTenant-originalarrivaltime: 18 Mar 2019 07:41:51.0694 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB3PR0402MB3819 Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org Select CONFIG_PWM_IMX_TPM by default to support i.MX7ULP TPM PWM. Signed-off-by: Anson Huang --- No changes. --- arch/arm/configs/imx_v6_v7_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig index 5586a50..57862c6 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig @@ -399,6 +399,7 @@ CONFIG_MPL3115=y CONFIG_PWM=y CONFIG_PWM_FSL_FTM=y CONFIG_PWM_IMX=y +CONFIG_PWM_IMX_TPM=y CONFIG_NVMEM_IMX_OCOTP=y CONFIG_NVMEM_VF610_OCOTP=y CONFIG_TEE=y From patchwork Mon Mar 18 07:41:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anson Huang X-Patchwork-Id: 1057713 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; 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Mon, 18 Mar 2019 07:41:59 +0000 Received: from DB3PR0402MB3916.eurprd04.prod.outlook.com ([fe80::f1b4:a1fb:cfd1:3f08]) by DB3PR0402MB3916.eurprd04.prod.outlook.com ([fe80::f1b4:a1fb:cfd1:3f08%6]) with mapi id 15.20.1709.015; Mon, 18 Mar 2019 07:41:59 +0000 From: Anson Huang To: "thierry.reding@gmail.com" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "shawnguo@kernel.org" , "s.hauer@pengutronix.de" , "kernel@pengutronix.de" , "festevam@gmail.com" , "linux@armlinux.org.uk" , "otavio@ossystems.com.br" , "stefan@agner.ch" , Leonard Crestez , Robin Gong , "jan.tuerk@emtrion.com" , "linux-pwm@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "u.kleine-koenig@pengutronix.de" CC: dl-linux-imx Subject: [PATCH V5 4/5] ARM: dts: imx7ulp: Add pwm0 support Thread-Topic: [PATCH V5 4/5] ARM: dts: imx7ulp: Add pwm0 support Thread-Index: AQHU3V4RXZq8Mgx1q0m22G0uu6mIag== Date: Mon, 18 Mar 2019 07:41:59 +0000 Message-ID: <1552894581-3391-5-git-send-email-Anson.Huang@nxp.com> References: <1552894581-3391-1-git-send-email-Anson.Huang@nxp.com> In-Reply-To: <1552894581-3391-1-git-send-email-Anson.Huang@nxp.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.7.4 x-clientproxiedby: HK2PR0401CA0011.apcprd04.prod.outlook.com (2603:1096:202:2::21) To DB3PR0402MB3916.eurprd04.prod.outlook.com (2603:10a6:8:10::18) authentication-results: spf=none (sender IP is ) smtp.mailfrom=anson.huang@nxp.com; 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DIR:OUT; SFP:1101; SCL:1; SRVR:DB3PR0402MB3819; H:DB3PR0402MB3916.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: wOqb5V0uZBZh3jScNPghYyDNIF/BaY0JCj6U3PZ4bk1U3Zii7Sf3hSnnmUMw4nmjBYhb5PUgvNimvYfqN0ROEUCrCU3C5UYA+wMrivlPO1PojUOxysoq9nUajN6PDiBwCJBB90Qi+27qA61JwiwBMz/uuukjWrrofoFaGyYoH5RUT/Xf+QXFLtKM57H/tSbniBmlhx0p/TXkKqaBVFJedT66FidPJziWWIySa6ySiiRPnrVvtBos8AF6t0cc18Xyob98YsqiNCoOlYIqJiMXRdd8F9DQ59wqvuE68KNwD7SaIQvFgkER+PXacPcAaeup3ReJhKYwWeAJ2Xi9IJt8+Ack4Ji/b8sbdPZPG4acp6/k18emHDOOaIKvFuGHh2LStf2W48i78G9SzBST44iWgOhEdes+hNOdh/XYhMYDNiM= MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4ab6aac0-9c60-4ca5-434d-08d6ab7533fb X-MS-Exchange-CrossTenant-originalarrivaltime: 18 Mar 2019 07:41:59.4444 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB3PR0402MB3819 Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org Add i.MX7ULP EVK board PWM0 support. Signed-off-by: Anson Huang --- No changes. --- arch/arm/boot/dts/imx7ulp-evk.dts | 12 ++++++++++++ arch/arm/boot/dts/imx7ulp.dtsi | 10 ++++++++++ 2 files changed, 22 insertions(+) diff --git a/arch/arm/boot/dts/imx7ulp-evk.dts b/arch/arm/boot/dts/imx7ulp-evk.dts index a09026a..3f5ea18 100644 --- a/arch/arm/boot/dts/imx7ulp-evk.dts +++ b/arch/arm/boot/dts/imx7ulp-evk.dts @@ -40,6 +40,12 @@ status = "okay"; }; +&pwm0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0>; + status = "okay"; +}; + &usdhc0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc0>; @@ -57,6 +63,12 @@ bias-pull-up; }; + pinctrl_pwm0: pwm0grp { + fsl,pins = < + IMX7ULP_PAD_PTF2__TPM4_CH1 0x2 + >; + }; + pinctrl_usdhc0: usdhc0grp { fsl,pins = < IMX7ULP_PAD_PTD1__SDHC0_CMD 0x43 diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi index eb349fd..49cb16c 100644 --- a/arch/arm/boot/dts/imx7ulp.dtsi +++ b/arch/arm/boot/dts/imx7ulp.dtsi @@ -124,6 +124,16 @@ status = "disabled"; }; + pwm0: pwm@40250000 { + compatible = "fsl,imx-tpm-pwm"; + reg = <0x40250000 0x1000>; + assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>; + assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>; + clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>; + #pwm-cells = <2>; + status = "disabled"; + }; + tpm5: tpm@40260000 { compatible = "fsl,imx7ulp-tpm"; reg = <0x40260000 0x1000>; From patchwork Mon Mar 18 07:42:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anson Huang X-Patchwork-Id: 1057714 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=nxp.com header.i=@nxp.com header.b="EcZUqOPM"; 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Mon, 18 Mar 2019 07:42:10 +0000 Received: from DB3PR0402MB3916.eurprd04.prod.outlook.com ([fe80::f1b4:a1fb:cfd1:3f08]) by DB3PR0402MB3916.eurprd04.prod.outlook.com ([fe80::f1b4:a1fb:cfd1:3f08%6]) with mapi id 15.20.1709.015; Mon, 18 Mar 2019 07:42:10 +0000 From: Anson Huang To: "thierry.reding@gmail.com" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "shawnguo@kernel.org" , "s.hauer@pengutronix.de" , "kernel@pengutronix.de" , "festevam@gmail.com" , "linux@armlinux.org.uk" , "otavio@ossystems.com.br" , "stefan@agner.ch" , Leonard Crestez , Robin Gong , "jan.tuerk@emtrion.com" , "linux-pwm@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "u.kleine-koenig@pengutronix.de" CC: dl-linux-imx Subject: [PATCH V5 5/5] ARM: dts: imx7ulp-evk: Add backlight support Thread-Topic: [PATCH V5 5/5] ARM: dts: imx7ulp-evk: Add backlight support Thread-Index: AQHU3V4YxXPMTt/i9kOHYsUEpGuDXQ== Date: Mon, 18 Mar 2019 07:42:10 +0000 Message-ID: <1552894581-3391-6-git-send-email-Anson.Huang@nxp.com> References: <1552894581-3391-1-git-send-email-Anson.Huang@nxp.com> In-Reply-To: <1552894581-3391-1-git-send-email-Anson.Huang@nxp.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.7.4 x-clientproxiedby: HK2PR0401CA0011.apcprd04.prod.outlook.com (2603:1096:202:2::21) To DB3PR0402MB3916.eurprd04.prod.outlook.com (2603:10a6:8:10::18) authentication-results: spf=none (sender IP is ) smtp.mailfrom=anson.huang@nxp.com; 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DIR:OUT; SFP:1101; SCL:1; SRVR:DB3PR0402MB3819; H:DB3PR0402MB3916.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: 28TDyv/3skyVTFjJj0ox684P/ls4LTJua6PQ5Q0ayQmygnZbvSUBQwlQfRWnog67p715WxwY6QXu0iStJ8/+51WY1MKKUk86CIvpDoA6TOjbjN3XlMRNvyEyDUk2QgaDupjwOl+wlueclauIYMgDQaeiGXBzFWthW/b/myIMRsht5nfMIIdnGQWDoGUHlm2LM1KXUFaVYB/3v3QPDh5yf/L/KAIOyj5UuW2iSbqdz299CrIRtWZf48OMzCORUHdW5FjUpYVMCRNKhEp3K13GhywKyrizYUg+5U7AH7VH2P9T7MBt8seOGZN7mFXWdxV7UB6FtD/xccZQNIMDfXoBFDyVqG8tA+puoZFgEFow8D+90GKvZMtdSk/mVXHpIVhbBq2MQbhn9AWl1QzHhq3LxQyN1noGjo2Ji9HdQAj1xlM= MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: e361be5f-baf2-4c70-357b-08d6ab753a84 X-MS-Exchange-CrossTenant-originalarrivaltime: 18 Mar 2019 07:42:10.6274 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB3PR0402MB3819 Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org This patch adds i.MX7ULP EVK board MIPI-DSI backlight support. Signed-off-by: Anson Huang --- No changes. --- arch/arm/boot/dts/imx7ulp-evk.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/imx7ulp-evk.dts b/arch/arm/boot/dts/imx7ulp-evk.dts index 3f5ea18..f90f2f3 100644 --- a/arch/arm/boot/dts/imx7ulp-evk.dts +++ b/arch/arm/boot/dts/imx7ulp-evk.dts @@ -22,6 +22,14 @@ reg = <0x60000000 0x40000000>; }; + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm0 1 50000>; + brightness-levels = <0 20 25 30 35 40 100>; + default-brightness-level = <6>; + status = "okay"; + }; + reg_vsd_3v3: regulator-vsd-3v3 { compatible = "regulator-fixed"; regulator-name = "VSD_3V3";