From patchwork Tue Mar 12 13:03:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 1055381 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="JsOAJjjd"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44JZtB629Yz9s5c for ; Wed, 13 Mar 2019 00:04:02 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726009AbfCLNEA (ORCPT ); Tue, 12 Mar 2019 09:04:00 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:15475 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725917AbfCLNEA (ORCPT ); Tue, 12 Mar 2019 09:04:00 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 12 Mar 2019 06:04:01 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 12 Mar 2019 06:03:59 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 12 Mar 2019 06:03:59 -0700 Received: from HQMAIL104.nvidia.com (172.18.146.11) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 12 Mar 2019 13:03:55 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Tue, 12 Mar 2019 13:03:55 +0000 Received: from vidyas-desktop.nvidia.com (Not Verified[10.24.37.38]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 12 Mar 2019 06:03:55 -0700 From: Vidya Sagar To: , , , , , CC: , , , , Subject: [PATCH] PCI: tegra: Use the DMA-API to get the MSI address Date: Tue, 12 Mar 2019 18:33:48 +0530 Message-ID: <1552395828-31021-1-git-send-email-vidyas@nvidia.com> X-Mailer: git-send-email 2.7.4 X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1552395841; bh=7gbZF6HfCAgpqMFMhWOWuaO8hRjsMTpNsr972vNQXok=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: X-NVConfidentiality:MIME-Version:Content-Type; b=JsOAJjjd7Sj6M0feH+K35IyYCFMyjH7LlLFLVRQSMA8zXYTr0fKU2mFt2lMNu5FKH BJrZAJPohRj4ajDctFDELQ6gzjcyoLxcqu3/hBxwb+cH3f5VBqQ9vkPkLjWKr4SzWi fmFX9+U5D7+8Ocvv1aRbKHe28PZ8CQcw95o6bWudHhF691+G2SYFjfJsgz2eYcAiZg CfpAUU6A/UH9py6Y28nD5ms3oi9gXdUg5/SDWXNIW8A83Wi5WE8MvKrUVW91TdsWLp i46X0CdOMt29BfDLxdWltXnvXT6GBiLgazZ6TsH/FVrbwWdklHl3Edid57mB0/KSQA dHERm0xPPfFwA== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Since the upstream MSI memory writes are generated by downstream devices, it is logically correct to have MSI target memory coming from the DMA pool reserved for PCIe than from the general memory pool reserved for CPU access. This avoids PCIe DMA addresses coinciding with MSI target address thereby raising unwanted MSI interrupts. This patch also enforces to limit the MSI target address to 32-bits to make it work for PCIe endponits that support only 32-bit MSI target address and those that support 64-bit MSI target address anyway work with 32-bit MSI target address Signed-off-by: Vidya Sagar Reviewed-by: Thierry Reding Acked-by: Thierry Reding --- Earlier, a different patch was sent with the subject "PCI: tegra: Do not allocate MSI target memory" ( http://patchwork.ozlabs.org/patch/1049550/ ) to address the same issue, but since I'm going to use a different subject for this patch, I'm sending it as a different patch instead of a different version to the previous patch drivers/pci/controller/pci-tegra.c | 28 ++++++++++++++++++++-------- 1 file changed, 20 insertions(+), 8 deletions(-) diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pci-tegra.c index f4f53d092e00..55a1626ddb69 100644 --- a/drivers/pci/controller/pci-tegra.c +++ b/drivers/pci/controller/pci-tegra.c @@ -231,8 +231,8 @@ struct tegra_msi { struct msi_controller chip; DECLARE_BITMAP(used, INT_PCI_MSI_NR); struct irq_domain *domain; - unsigned long pages; struct mutex lock; + void *virt; u64 phys; int irq; }; @@ -1536,7 +1536,7 @@ static int tegra_pcie_msi_setup(struct tegra_pcie *pcie) err = platform_get_irq_byname(pdev, "msi"); if (err < 0) { dev_err(dev, "failed to get IRQ: %d\n", err); - goto err; + goto free_irq_domain; } msi->irq = err; @@ -1545,17 +1545,29 @@ static int tegra_pcie_msi_setup(struct tegra_pcie *pcie) tegra_msi_irq_chip.name, pcie); if (err < 0) { dev_err(dev, "failed to request IRQ: %d\n", err); - goto err; + goto free_irq_domain; + } + + err = dma_set_coherent_mask(dev, DMA_BIT_MASK(32)); + if (err < 0) { + dev_err(dev, "failed to set dma coherent mask: %d\n", err); + goto free_irq; + } + + msi->virt = dma_alloc_coherent(dev, PAGE_SIZE, &msi->phys, GFP_KERNEL); + if (!msi->virt) { + dev_err(dev, "failed to alloc dma mem for MSI\n"); + err = -ENOMEM; + goto free_irq; } - /* setup AFI/FPCI range */ - msi->pages = __get_free_pages(GFP_KERNEL, 0); - msi->phys = virt_to_phys((void *)msi->pages); host->msi = &msi->chip; return 0; -err: +free_irq: + free_irq(msi->irq, pcie); +free_irq_domain: irq_domain_remove(msi->domain); return err; } @@ -1592,7 +1604,7 @@ static void tegra_pcie_msi_teardown(struct tegra_pcie *pcie) struct tegra_msi *msi = &pcie->msi; unsigned int i, irq; - free_pages(msi->pages, 0); + dma_free_coherent(pcie->dev, PAGE_SIZE, msi->virt, msi->phys); if (msi->irq > 0) free_irq(msi->irq, pcie);