From patchwork Fri Mar 1 19:33:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Bergner X-Patchwork-Id: 1050403 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-497252-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="wk/okuhI"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44B02z0H13z9s00 for ; Sat, 2 Mar 2019 06:33:43 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:to:cc :from:subject:date:mime-version:content-type :content-transfer-encoding:message-id; q=dns; s=default; b=LKhIo GewhQRJ6qd4iNairAt6eQtxnrxx8T7bDyIA9PjxSqzoJ+N2Of5Fno1RsIGlQlRUv WzOuZ8ka26YnBpxfwnELX0RDCEdn1ETKJLs6ntOUfUHiEyvoWqgW62M2j8ymorgm ZNeBGLgv8jLqLAjgw1TAU/+Ry4a1eOKHhLV2ZQ= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:to:cc :from:subject:date:mime-version:content-type :content-transfer-encoding:message-id; s=default; bh=AvwoOsDJgag Yl8t+0rF0pFDAs7U=; b=wk/okuhIkO62D5ZyFgHPgX0t0AwM1Y9Uuy/ci3UUdNw QwP8IkJo+bP5ctFRGaf+95BkYhXa6sddH3p12vKgOzu+HqhchNpTRGd4l+9mJjmP i2qGRhcrmiCE/2sevTZPyD7WdeSFOkhlsKKUe9pvM1AL5iQdftnEQ35lNvR9xpWM = Received: (qmail 23270 invoked by alias); 1 Mar 2019 19:33:36 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 22900 invoked by uid 89); 1 Mar 2019 19:33:35 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-11.8 required=5.0 tests=BAYES_00, GIT_PATCH_2, GIT_PATCH_3, KAM_ASCII_DIVIDERS, KHOP_DYNAMIC, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 spammy=sf, spilled, define_expand X-HELO: mx0a-001b2d01.pphosted.com Received: from mx0a-001b2d01.pphosted.com (HELO mx0a-001b2d01.pphosted.com) (148.163.156.1) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 01 Mar 2019 19:33:34 +0000 Received: from pps.filterd (m0098399.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x21JODq0136571 for ; Fri, 1 Mar 2019 14:33:32 -0500 Received: from e35.co.us.ibm.com (e35.co.us.ibm.com [32.97.110.153]) by mx0a-001b2d01.pphosted.com with ESMTP id 2qyas88j99-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Fri, 01 Mar 2019 14:33:32 -0500 Received: from localhost by e35.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Fri, 1 Mar 2019 19:33:30 -0000 Received: from b03ledav006.gho.boulder.ibm.com (b03ledav006.gho.boulder.ibm.com [9.17.130.237]) by b03cxnp08028.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x21JXSi215663202 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 1 Mar 2019 19:33:28 GMT Received: from b03ledav006.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 93C01C605A; Fri, 1 Mar 2019 19:33:28 +0000 (GMT) Received: from b03ledav006.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 13482C6059; Fri, 1 Mar 2019 19:33:27 +0000 (GMT) Received: from otta.local (unknown [9.80.225.99]) by b03ledav006.gho.boulder.ibm.com (Postfix) with ESMTP; Fri, 1 Mar 2019 19:33:27 +0000 (GMT) To: GCC Patches Cc: Segher Boessenkool From: Peter Bergner Subject: [PATCH, rs6000] Fix PR88845: ICE in lra_set_insn_recog_data Date: Fri, 1 Mar 2019 13:33:27 -0600 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.13; rv:60.0) Gecko/20100101 Thunderbird/60.5.1 MIME-Version: 1.0 x-cbid: 19030119-0012-0000-0000-000017132517 X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00010687; HX=3.00000242; KW=3.00000007; PH=3.00000004; SC=3.00000281; SDB=6.01168191; UDB=6.00610348; IPR=6.00948806; MB=3.00025798; MTD=3.00000008; XFM=3.00000015; UTC=2019-03-01 19:33:31 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19030119-0013-0000-0000-0000565FCA47 Message-Id: X-IsSubscribed: yes PR88845 shows a problem where LRA spilled an input operand of an inline asm statement by calling our generic movsf pattern which ended up generating an insn we don't have a pattern for, so we ICE. The insn was: (insn (set (reg:SF 125) (subreg:SF (reg:SI 124) 0))) The problem is that rs6000_emit_move_si_sf_subreg() is disabled for LRA and so wasn't able to call gen_movsf_from_si() which generates the correct pattern for moving a 32-bit value from a GPR to a FPR. The patch below fixes the issue by allowing rs6000_emit_move_si_sf_subreg() to be called during LRA as well as creating an expander so that when it is called during LRA, we can create the scratch register that is required for its associated splitter. We have to do this, since LRA has already converted all of the scratches into real registers before it does any spilling. This passed bootstrap and regtesting on powerpc64le-linux with no regressions. Ok for mainline? Peter gcc/ PR rtl-optimization/88845 * config/rs6000/rs6000.c (rs6000_emit_move_si_sf_subreg): Enable during LRA. * config/rs6000/rs6000.md (movsf_from_si): New expander; old insn and splitter renamed from this ... (movsf_from_si_internal): ... to this. gcc/testsuite/ PR rtl-optimization/88845 * gcc.target/powerpc/pr88845.c: New test. Index: gcc/config/rs6000/rs6000.c =================================================================== --- gcc/config/rs6000/rs6000.c (revision 269263) +++ gcc/config/rs6000/rs6000.c (working copy) @@ -9887,7 +9887,7 @@ valid_sf_si_move (rtx dest, rtx src, mac static bool rs6000_emit_move_si_sf_subreg (rtx dest, rtx source, machine_mode mode) { - if (TARGET_DIRECT_MOVE_64BIT && !lra_in_progress && !reload_completed + if (TARGET_DIRECT_MOVE_64BIT && !reload_completed && (!SUBREG_P (dest) || !sf_subreg_operand (dest, mode)) && SUBREG_P (source) && sf_subreg_operand (source, mode)) { Index: gcc/config/rs6000/rs6000.md =================================================================== --- gcc/config/rs6000/rs6000.md (revision 269263) +++ gcc/config/rs6000/rs6000.md (working copy) @@ -7353,9 +7353,31 @@ (define_insn "*mov_softfloat" ;; This function is called before reload, and it creates the temporary as ;; needed. +(define_expand "movsf_from_si" + [(parallel [(set (match_operand:SF 0 "nonimmediate_operand") + (unspec:SF [(match_operand:SI 1 "input_operand" )] + UNSPEC_SF_FROM_SI)) + (clobber (match_scratch:DI 2))])] + "TARGET_NO_SF_SUBREG + && (register_operand (operands[0], SFmode) + || register_operand (operands[1], SImode))" +{ + if (lra_in_progress + && REG_P (operands[0]) + && REG_P (operands[1])) + { + /* If LRA is generating a direct move from a GPR to a FPR, + then the splitter is going to need a scratch register. */ + rtx insn = gen_movsf_from_si_internal (operands[0], operands[1]); + XEXP (XVECEXP (insn, 0, 1), 0) = gen_reg_rtx (DImode); + emit_insn (insn); + DONE; + } +}) + ;; LWZ LFS LXSSP LXSSPX STW STFIWX ;; STXSIWX GPR->VSX VSX->GPR GPR->GPR -(define_insn_and_split "movsf_from_si" +(define_insn_and_split "movsf_from_si_internal" [(set (match_operand:SF 0 "nonimmediate_operand" "=!r, f, wb, wu, m, Z, Z, wy, ?r, !r") Index: gcc/testsuite/gcc.target/powerpc/pr88845.c =================================================================== --- gcc/testsuite/gcc.target/powerpc/pr88845.c (nonexistent) +++ gcc/testsuite/gcc.target/powerpc/pr88845.c (working copy) @@ -0,0 +1,25 @@ +/* { dg-do compile { target powerpc*-*-linux* } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ +/* { dg-skip-if "" { powerpc*-*-*spe* } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-options "-mcpu=power8 -O2" } */ +/* { dg-final { scan-assembler {\mmtvsrd\M} { target { lp64 } } } } */ +/* { dg-final { scan-assembler {\mxscvspdpn\M} { target { lp64 } } } } */ + +/* Verify that we do not ICE and that we generate a direct move + for float types when compiling for 64-bit. */ + +struct a { + unsigned ui; + float f; +}; + +void +foo (void) +{ + float e; + struct a s; + e = s.f; + __asm__("" : : "d" (e)); +}