From patchwork Thu Feb 21 21:43:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Goldschmidt X-Patchwork-Id: 1046464 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Jvzc4kUg"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 4457Kp1b5Nz9s71 for ; Fri, 22 Feb 2019 08:44:46 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id D297EC21E3A; Thu, 21 Feb 2019 21:44:00 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 6D253C21F35; Thu, 21 Feb 2019 21:43:45 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id C5FFBC21DA6; Thu, 21 Feb 2019 21:43:41 +0000 (UTC) Received: from mail-wr1-f67.google.com (mail-wr1-f67.google.com [209.85.221.67]) by lists.denx.de (Postfix) with ESMTPS id BB7B1C21C4A for ; Thu, 21 Feb 2019 21:43:40 +0000 (UTC) Received: by mail-wr1-f67.google.com with SMTP id r5so106344wrg.9 for ; Thu, 21 Feb 2019 13:43:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=xlK8aK6AripZfqrWWXrTBGXOljmfPlrz2Y5rsGm1eWg=; b=Jvzc4kUgrMM7ZMYs/HUvdOoOa40bcOkDSFVXNHjE+ZUMnJ5M5lIF/8lnD3/K55aTtZ B54kI1rO2vC1cedie1vn/bxKHLUTz1Y15Jpcwqjqah9RZcsCugwX43JxDDGKbldWTQHw A6z6fyc1K6CRwwzxod4+E3tZ6Nrez0SsoHxbDHRg5seuSgvzi+CsZCXTbcM+dHztsAv2 sMQNBCJbYVSl1jXyvlOrrrcqZJY6qjZG8eFZccnq6PBShsyYufy3xVyRnvmcATbq79a5 TB6S4SY0K1DJjFQTAl4sgTQ9eCtG9zPiUtr/6dEJ1X28shODpg4EJ2JMiJXUVG0TeXny 6/OQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=xlK8aK6AripZfqrWWXrTBGXOljmfPlrz2Y5rsGm1eWg=; b=TK604flo8Oa/7f2U4ExQ42ByGShxaZ+M77zMcY9sW30dpYqOMCpJ/nsLS3RMi/8KL5 fNj9FlShNkkxqNyQQyk3NMBTXtHNf9APhxR24eFrQKHHT/DBE969A1Ju7IblzKnvy9V0 RylAfzk+IEz7rervMN4+F+WVYzTUCeIR/KdsWUe6u0r8hBCg+iIjeF/KAuPO/3RFce+t EJMAfcx0jLRdNwKAgbdm9+JPEblo3b1NcP/cjm/Qd6N6JOyMYfmMrweMbv6r7NmWxOUL OR1ivjhb74klr8jQ0X2f3uGqmJPsYK/3cQiL23tpjuYcHxN6NAE7KXORwcHzucaZ1hog 13jw== X-Gm-Message-State: AHQUAuaigQmYKFZuo1j9mRsrspGfSbbx2o6kzIvfC3qdPrXceoABz8ve F/Hr+LMQhSEFSco8LDIOAzE= X-Google-Smtp-Source: AHgI3Ia+V5ZGZ/T6Az+MxHmAO2YXE1WLCQUxJq70COje53XKmbKXpmonEFX5/PAYLeVcsk+MncOK+w== X-Received: by 2002:a5d:6682:: with SMTP id l2mr382160wru.271.1550785420347; Thu, 21 Feb 2019 13:43:40 -0800 (PST) Received: from ubuntu.home ([2a02:8071:6a3:700:9065:254c:ff38:3288]) by smtp.gmail.com with ESMTPSA id m26sm4308wmg.13.2019.02.21.13.43.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 21 Feb 2019 13:43:39 -0800 (PST) From: Simon Goldschmidt To: Marek Vasut , u-boot@lists.denx.de Date: Thu, 21 Feb 2019 22:43:25 +0100 Message-Id: <20190221214332.4246-2-simon.k.r.goldschmidt@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190221214332.4246-1-simon.k.r.goldschmidt@gmail.com> References: <20190221214332.4246-1-simon.k.r.goldschmidt@gmail.com> Cc: Tom Rini Subject: [U-Boot] [PATCH v2 1/8] arm: socfpga: gen5: sync devicetrees to Linux X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This is again a sync to linux-next + pending patches in Dinh's tree at commit 1c909b2dfe6a ("ARM: dts: socfpga: update more missing reset properties")' It adds missing peripheral reset properties to socfpga.dtsi and removes U-Boot specific leftovers from socfpga_cyclone5_socrates.dts. Signed-off-by: Simon Goldschmidt --- Changes in v2: - cleanly merged Linux dts (moved change of SDR controller base address to a separate patch) arch/arm/dts/socfpga.dtsi | 19 +++++++++++++++++-- arch/arm/dts/socfpga_cyclone5_socrates.dts | 2 -- 2 files changed, 17 insertions(+), 4 deletions(-) diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi index 2458d6707d..ec1966480f 100644 --- a/arch/arm/dts/socfpga.dtsi +++ b/arch/arm/dts/socfpga.dtsi @@ -84,6 +84,7 @@ #dma-requests = <32>; clocks = <&l4_main_clk>; clock-names = "apb_pclk"; + resets = <&rst DMA_RESET>; }; }; @@ -100,6 +101,7 @@ reg = <0xffc00000 0x1000>; interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>; clocks = <&can0_clk>; + resets = <&rst CAN0_RESET>; status = "disabled"; }; @@ -108,6 +110,7 @@ reg = <0xffc01000 0x1000>; interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>; clocks = <&can1_clk>; + resets = <&rst CAN1_RESET>; status = "disabled"; }; @@ -585,6 +588,7 @@ compatible = "snps,dw-apb-gpio"; reg = <0xff708000 0x1000>; clocks = <&l4_mp_clk>; + resets = <&rst GPIO0_RESET>; status = "disabled"; porta: gpio-controller@0 { @@ -605,6 +609,7 @@ compatible = "snps,dw-apb-gpio"; reg = <0xff709000 0x1000>; clocks = <&l4_mp_clk>; + resets = <&rst GPIO1_RESET>; status = "disabled"; portb: gpio-controller@0 { @@ -625,6 +630,7 @@ compatible = "snps,dw-apb-gpio"; reg = <0xff70a000 0x1000>; clocks = <&l4_mp_clk>; + resets = <&rst GPIO2_RESET>; status = "disabled"; portc: gpio-controller@0 { @@ -735,6 +741,7 @@ #size-cells = <0>; clocks = <&l4_mp_clk>, <&sdmmc_clk_divided>; clock-names = "biu", "ciu"; + resets = <&rst SDMMC_RESET>; status = "disabled"; }; @@ -746,9 +753,9 @@ <0xffb80000 0x10000>; reg-names = "nand_data", "denali_reg"; interrupts = <0x0 0x90 0x4>; - dma-mask = <0xffffffff>; clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>; clock-names = "nand", "nand_x", "ecc"; + resets = <&rst NAND_RESET>; status = "disabled"; }; @@ -759,7 +766,7 @@ qspi: spi@ff705000 { compatible = "cdns,qspi-nor"; - #address-cells = <1>; + #address-cells = <1>; #size-cells = <0>; reg = <0xff705000 0x1000>, <0xffa00000 0x1000>; @@ -768,6 +775,7 @@ cdns,fifo-width = <4>; cdns,trigger-address = <0x00000000>; clocks = <&qspi_clk>; + resets = <&rst QSPI_RESET>; status = "disabled"; }; @@ -786,6 +794,7 @@ sdr: sdr@ffc25000 { compatible = "altr,sdr-ctl", "syscon"; reg = <0xffc25000 0x1000>; + resets = <&rst SDR_RESET>; }; sdramedac { @@ -802,6 +811,7 @@ interrupts = <0 154 4>; num-cs = <4>; clocks = <&spi_m_clk>; + resets = <&rst SPIM0_RESET>; status = "disabled"; }; @@ -813,6 +823,7 @@ interrupts = <0 155 4>; num-cs = <4>; clocks = <&spi_m_clk>; + resets = <&rst SPIM1_RESET>; status = "disabled"; }; @@ -879,6 +890,7 @@ dmas = <&pdma 28>, <&pdma 29>; dma-names = "tx", "rx"; + resets = <&rst UART0_RESET>; }; uart1: serial1@ffc03000 { @@ -891,6 +903,7 @@ dmas = <&pdma 30>, <&pdma 31>; dma-names = "tx", "rx"; + resets = <&rst UART1_RESET>; }; usbphy0: usbphy { @@ -930,6 +943,7 @@ reg = <0xffd02000 0x1000>; interrupts = <0 171 4>; clocks = <&osc1>; + resets = <&rst L4WD0_RESET>; status = "disabled"; }; @@ -938,6 +952,7 @@ reg = <0xffd03000 0x1000>; interrupts = <0 172 4>; clocks = <&osc1>; + resets = <&rst L4WD1_RESET>; status = "disabled"; }; }; diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts b/arch/arm/dts/socfpga_cyclone5_socrates.dts index 93c3fa4a48..8d5d3996f6 100644 --- a/arch/arm/dts/socfpga_cyclone5_socrates.dts +++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts @@ -76,7 +76,6 @@ &qspi { status = "okay"; - u-boot,dm-pre-reloc; flash: flash@0 { #address-cells = <1>; @@ -91,6 +90,5 @@ cdns,tchsh-ns = <4>; cdns,tslch-ns = <4>; status = "okay"; - u-boot,dm-pre-reloc; }; }; From patchwork Thu Feb 21 21:43:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Goldschmidt X-Patchwork-Id: 1046463 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Thu, 21 Feb 2019 13:43:40 -0800 (PST) From: Simon Goldschmidt To: Marek Vasut , u-boot@lists.denx.de Date: Thu, 21 Feb 2019 22:43:26 +0100 Message-Id: <20190221214332.4246-3-simon.k.r.goldschmidt@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190221214332.4246-1-simon.k.r.goldschmidt@gmail.com> References: <20190221214332.4246-1-simon.k.r.goldschmidt@gmail.com> Cc: Tom Rini Subject: [U-Boot] [PATCH v2 2/8] arm: socfpga: gen5: add reset & sdr node to SPL devicetrees X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The SPL for socfpga gen5 currently takes all peripherals out of reset unconditionally. To implement proper reset handling for peripherals, the reset node has to be provided with the SPL dts. In preparation to move the DDR driver to DM, the sdr node is required in SPL, too. This patch adds "u-boot,dm-pre-reloc" to U-Boot specific dtsi addon files so that the reset manager and SDR driver correctly probe in SPL. Signed-off-by: Simon Goldschmidt --- Changes in v2: None arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi | 8 ++++++++ arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts | 8 ++++++++ arch/arm/dts/socfpga_cyclone5_de0_nano_soc-u-boot.dtsi | 8 ++++++++ arch/arm/dts/socfpga_cyclone5_de10_nano.dts | 8 ++++++++ arch/arm/dts/socfpga_cyclone5_de1_soc.dts | 8 ++++++++ arch/arm/dts/socfpga_cyclone5_is1.dts | 8 ++++++++ arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi | 8 ++++++++ arch/arm/dts/socfpga_cyclone5_sockit-u-boot.dtsi | 8 ++++++++ arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi | 8 ++++++++ arch/arm/dts/socfpga_cyclone5_sr1500.dts | 8 ++++++++ arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi | 8 ++++++++ 11 files changed, 88 insertions(+) diff --git a/arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi index c44d1ee2fa..8aaec56285 100644 --- a/arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi +++ b/arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi @@ -17,6 +17,14 @@ }; }; +&rst { + u-boot,dm-pre-reloc; +}; + +&sdr { + u-boot,dm-pre-reloc; +}; + &watchdog0 { status = "disabled"; }; diff --git a/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts b/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts index a387071674..61907771e0 100644 --- a/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts +++ b/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts @@ -30,6 +30,14 @@ }; }; +&rst { + u-boot,dm-pre-reloc; +}; + +&sdr { + u-boot,dm-pre-reloc; +}; + &gmac1 { status = "okay"; phy-mode = "rgmii"; diff --git a/arch/arm/dts/socfpga_cyclone5_de0_nano_soc-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_de0_nano_soc-u-boot.dtsi index 08d81da169..00434185f6 100644 --- a/arch/arm/dts/socfpga_cyclone5_de0_nano_soc-u-boot.dtsi +++ b/arch/arm/dts/socfpga_cyclone5_de0_nano_soc-u-boot.dtsi @@ -16,6 +16,14 @@ }; }; +&rst { + u-boot,dm-pre-reloc; +}; + +&sdr { + u-boot,dm-pre-reloc; +}; + &watchdog0 { status = "disabled"; }; diff --git a/arch/arm/dts/socfpga_cyclone5_de10_nano.dts b/arch/arm/dts/socfpga_cyclone5_de10_nano.dts index e9105743ea..dc84f3de26 100644 --- a/arch/arm/dts/socfpga_cyclone5_de10_nano.dts +++ b/arch/arm/dts/socfpga_cyclone5_de10_nano.dts @@ -32,6 +32,14 @@ }; }; +&rst { + u-boot,dm-pre-reloc; +}; + +&sdr { + u-boot,dm-pre-reloc; +}; + &gmac1 { status = "okay"; phy-mode = "rgmii"; diff --git a/arch/arm/dts/socfpga_cyclone5_de1_soc.dts b/arch/arm/dts/socfpga_cyclone5_de1_soc.dts index 4f076bce93..585d914e30 100644 --- a/arch/arm/dts/socfpga_cyclone5_de1_soc.dts +++ b/arch/arm/dts/socfpga_cyclone5_de1_soc.dts @@ -30,6 +30,14 @@ }; }; +&rst { + u-boot,dm-pre-reloc; +}; + +&sdr { + u-boot,dm-pre-reloc; +}; + &gmac1 { status = "okay"; phy-mode = "rgmii"; diff --git a/arch/arm/dts/socfpga_cyclone5_is1.dts b/arch/arm/dts/socfpga_cyclone5_is1.dts index b7054bfd5a..8947128be9 100644 --- a/arch/arm/dts/socfpga_cyclone5_is1.dts +++ b/arch/arm/dts/socfpga_cyclone5_is1.dts @@ -37,6 +37,14 @@ }; }; +&rst { + u-boot,dm-pre-reloc; +}; + +&sdr { + u-boot,dm-pre-reloc; +}; + &gmac1 { status = "okay"; phy-mode = "rgmii"; diff --git a/arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi index 9436e0fa8b..13d44072f4 100644 --- a/arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi +++ b/arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi @@ -17,6 +17,14 @@ }; }; +&rst { + u-boot,dm-pre-reloc; +}; + +&sdr { + u-boot,dm-pre-reloc; +}; + &can0 { status = "okay"; }; diff --git a/arch/arm/dts/socfpga_cyclone5_sockit-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_sockit-u-boot.dtsi index 648f1bd01d..07564a9f13 100644 --- a/arch/arm/dts/socfpga_cyclone5_sockit-u-boot.dtsi +++ b/arch/arm/dts/socfpga_cyclone5_sockit-u-boot.dtsi @@ -17,6 +17,14 @@ }; }; +&rst { + u-boot,dm-pre-reloc; +}; + +&sdr { + u-boot,dm-pre-reloc; +}; + &watchdog0 { status = "disabled"; }; diff --git a/arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi index 31bd1dba0f..cf0eb8bb8c 100644 --- a/arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi +++ b/arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi @@ -17,6 +17,14 @@ }; }; +&rst { + u-boot,dm-pre-reloc; +}; + +&sdr { + u-boot,dm-pre-reloc; +}; + &watchdog0 { status = "disabled"; }; diff --git a/arch/arm/dts/socfpga_cyclone5_sr1500.dts b/arch/arm/dts/socfpga_cyclone5_sr1500.dts index 6a6c29be79..8a1678ed72 100644 --- a/arch/arm/dts/socfpga_cyclone5_sr1500.dts +++ b/arch/arm/dts/socfpga_cyclone5_sr1500.dts @@ -33,6 +33,14 @@ }; }; +&rst { + u-boot,dm-pre-reloc; +}; + +&sdr { + u-boot,dm-pre-reloc; +}; + &gmac1 { status = "okay"; phy-mode = "rgmii"; diff --git a/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi index 360b946ba2..90d1fd8858 100644 --- a/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi +++ b/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi @@ -17,6 +17,14 @@ }; }; +&rst { + u-boot,dm-pre-reloc; +}; + +&sdr { + u-boot,dm-pre-reloc; +}; + &watchdog0 { status = "disabled"; }; From patchwork Thu Feb 21 21:43:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Goldschmidt X-Patchwork-Id: 1046465 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; 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bh=mIyA0hmqXmszbib/QT5JS7rN003mhXVp/WW065PKR9E=; b=nQqaoUVtotbJ7MJEoHxo7jYlu69ElLxR4JZbJVjYarCEgDX/rY+Rz1Xmqc/ONPXvJL RsSTEPPtswGrhAfvWfx9pdwiWQTCQE9/rZAGwKk01MV4HxGUgPs7AU0ygMiQ/dDk0n5f hs3JCBm0fGK7en8DYKnuT4rSKK85F8fjfepc2RvAKoQ4E5TAqnbaN8MW80k/CJo4bUML LxHnaH1mKESfVE1lcZZbDeF10MIhoYaYglRfAXW9nVZt3dzuPeaJ/q9xHSbi0GmTfTB1 /5mgELCsiQf1AlZCO8g5KGmaOlRa+nrroE+BgMGUHKLeCaa6vX4iRu0yP1eoPQ4eD2mJ pH2A== X-Gm-Message-State: AHQUAubR+lDa6NSwJg4PwP8wVglT+aqeao1RfE6gAS7h9jp6X9neCTGe BUWopGghJvDEZ3bl8ZJV6TM= X-Google-Smtp-Source: AHgI3IZGpYnvym5Nc8v4lFBmeGm0Tc8QZ0vwR5HfKJpDTK/O6d4/K6Wt9hbZ0FLapbP2ei8VOjKHgw== X-Received: by 2002:a5d:6a88:: with SMTP id s8mr410030wru.303.1550785422505; Thu, 21 Feb 2019 13:43:42 -0800 (PST) Received: from ubuntu.home ([2a02:8071:6a3:700:9065:254c:ff38:3288]) by smtp.gmail.com with ESMTPSA id m26sm4308wmg.13.2019.02.21.13.43.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 21 Feb 2019 13:43:41 -0800 (PST) From: Simon Goldschmidt To: Marek Vasut , u-boot@lists.denx.de Date: Thu, 21 Feb 2019 22:43:27 +0100 Message-Id: <20190221214332.4246-4-simon.k.r.goldschmidt@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190221214332.4246-1-simon.k.r.goldschmidt@gmail.com> References: <20190221214332.4246-1-simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee , Tom Rini Subject: [U-Boot] [PATCH v2 3/8] arm: socfpga: move gen5 SDR driver to DM X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" To clean up reset handling for socfpga gen5, port the DDR driver to DM using UCLASS_RAM and implement proper reset handling. This gets us rid of one ad-hoc call to socfpga_per_reset(). The gen5 driver is implemented in 2 distinct files. One of it (containing the calibration training) is not touched much and is kept at using hard coded addresses since the code grows even more otherwise. SPL is changed from calling hard into the DDR driver code to just probing UCLASS_RESET and UCLASS_RAM. It is happy after finding a RAM driver after that. Signed-off-by: Simon Goldschmidt --- Changes in v2: - port DDR driver to DM UCLASS_RAM - don't change DDR calibration training driver (code got too big) - use reset.h code instead of socfpga_per_reset() arch/arm/Kconfig | 2 + arch/arm/dts/socfpga.dtsi | 4 +- .../mach-socfpga/include/mach/sdram_gen5.h | 4 - arch/arm/mach-socfpga/spl_gen5.c | 29 ++-- drivers/ddr/altera/Kconfig | 1 + drivers/ddr/altera/sdram_gen5.c | 143 ++++++++++++++++-- drivers/ddr/altera/sequencer.c | 9 +- drivers/ddr/altera/sequencer.h | 35 +++++ 8 files changed, 185 insertions(+), 42 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 455f06cfee..8ff4529095 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -821,12 +821,14 @@ config ARCH_SOCFPGA select DM_SERIAL select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 select OF_CONTROL + select RAM if TARGET_SOCFPGA_GEN5 select SPL_DM_RESET if DM_RESET select SPL_DM_SERIAL select SPL_LIBCOMMON_SUPPORT select SPL_LIBGENERIC_SUPPORT select SPL_NAND_SUPPORT if SPL_NAND_DENALI select SPL_OF_CONTROL + select SPL_RAM if TARGET_SOCFPGA_GEN5 select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10 select SPL_SERIAL_SUPPORT select SPL_WATCHDOG_SUPPORT diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi index ec1966480f..51a6a51b53 100644 --- a/arch/arm/dts/socfpga.dtsi +++ b/arch/arm/dts/socfpga.dtsi @@ -791,9 +791,9 @@ reg = <0xfffec000 0x100>; }; - sdr: sdr@ffc25000 { + sdr: sdr@ffc20000 { compatible = "altr,sdr-ctl", "syscon"; - reg = <0xffc25000 0x1000>; + reg = <0xffc20000 0x6000>; resets = <&rst SDR_RESET>; }; diff --git a/arch/arm/mach-socfpga/include/mach/sdram_gen5.h b/arch/arm/mach-socfpga/include/mach/sdram_gen5.h index a238d5d17f..c41208591a 100644 --- a/arch/arm/mach-socfpga/include/mach/sdram_gen5.h +++ b/arch/arm/mach-socfpga/include/mach/sdram_gen5.h @@ -7,10 +7,6 @@ #ifndef __ASSEMBLY__ -unsigned long sdram_calculate_size(void); -int sdram_mmr_init_full(unsigned int sdr_phy_reg); -int sdram_calibration_full(void); - const struct socfpga_sdram_config *socfpga_get_sdram_config(void); void socfpga_get_seq_ac_init(const u32 **init, unsigned int *nelem); diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c index 4c9f7997be..1bff8cbfcf 100644 --- a/arch/arm/mach-socfpga/spl_gen5.c +++ b/arch/arm/mach-socfpga/spl_gen5.c @@ -20,6 +20,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -66,9 +67,9 @@ u32 spl_boot_mode(const u32 boot_device) void board_init_f(ulong dummy) { const struct cm_config *cm_default_cfg = cm_get_default_config(); - unsigned long sdram_size; unsigned long reg; int ret; + struct udevice *dev; /* * First C code to run. Clear fake OCRAM ECC first as SBE @@ -98,7 +99,6 @@ void board_init_f(ulong dummy) socfpga_bridges_reset(1); } - socfpga_per_reset(SOCFPGA_RESET(SDR), 0); socfpga_per_reset(SOCFPGA_RESET(UART0), 0); socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0); @@ -142,27 +142,16 @@ void board_init_f(ulong dummy) hang(); } + ret = uclass_get_device(UCLASS_RESET, 0, &dev); + if (ret) + debug("Reset init failed: %d\n", ret); + /* enable console uart printing */ preloader_console_init(); - if (sdram_mmr_init_full(0xffffffff) != 0) { - puts("SDRAM init failed.\n"); - hang(); - } - - debug("SDRAM: Calibrating PHY\n"); - /* SDRAM calibration */ - if (sdram_calibration_full() == 0) { - puts("SDRAM calibration failed.\n"); - hang(); - } - - sdram_size = sdram_calculate_size(); - debug("SDRAM: %ld MiB\n", sdram_size >> 20); - - /* Sanity check ensure correct SDRAM size specified */ - if (get_ram_size(0, sdram_size) != sdram_size) { - puts("SDRAM size check failed!\n"); + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + debug("DRAM init failed: %d\n", ret); hang(); } diff --git a/drivers/ddr/altera/Kconfig b/drivers/ddr/altera/Kconfig index 2b28a97f6e..7370d4133a 100644 --- a/drivers/ddr/altera/Kconfig +++ b/drivers/ddr/altera/Kconfig @@ -1,5 +1,6 @@ config ALTERA_SDRAM bool "SoCFPGA DDR SDRAM driver" + depends on RAM depends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 help Enable DDR SDRAM controller for the SoCFPGA devices. diff --git a/drivers/ddr/altera/sdram_gen5.c b/drivers/ddr/altera/sdram_gen5.c index 821060459c..fcd89b619d 100644 --- a/drivers/ddr/altera/sdram_gen5.c +++ b/drivers/ddr/altera/sdram_gen5.c @@ -3,14 +3,30 @@ * Copyright Altera Corporation (C) 2014-2015 */ #include +#include #include #include +#include +#include #include #include +#include #include #include #include +#include "sequencer.h" + +#ifdef CONFIG_SPL_BUILD + +struct altera_gen5_sdram_priv { + struct ram_info info; +}; + +struct altera_gen5_sdram_platdata { + struct socfpga_sdr *sdr; +}; + struct sdram_prot_rule { u32 sdram_start; /* SDRAM start address */ u32 sdram_end; /* SDRAM end address */ @@ -26,8 +42,8 @@ struct sdram_prot_rule { static struct socfpga_system_manager *sysmgr_regs = (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; -static struct socfpga_sdr_ctrl *sdr_ctrl = - (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS; + +static unsigned long sdram_calculate_size(struct socfpga_sdr_ctrl *sdr_ctrl); /** * get_errata_rows() - Up the number of DRAM rows to cover entire address space @@ -104,7 +120,8 @@ static int get_errata_rows(const struct socfpga_sdram_config *cfg) } /* SDRAM protection rules vary from 0-19, a total of 20 rules. */ -static void sdram_set_rule(struct sdram_prot_rule *prule) +static void sdram_set_rule(struct socfpga_sdr_ctrl *sdr_ctrl, + struct sdram_prot_rule *prule) { u32 lo_addr_bits; u32 hi_addr_bits; @@ -141,7 +158,8 @@ static void sdram_set_rule(struct sdram_prot_rule *prule) writel(0, &sdr_ctrl->prot_rule_rdwr); } -static void sdram_get_rule(struct sdram_prot_rule *prule) +static void sdram_get_rule(struct socfpga_sdr_ctrl *sdr_ctrl, + struct sdram_prot_rule *prule) { u32 addr; u32 id; @@ -172,7 +190,8 @@ static void sdram_get_rule(struct sdram_prot_rule *prule) } static void -sdram_set_protection_config(const u32 sdram_start, const u32 sdram_end) +sdram_set_protection_config(struct socfpga_sdr_ctrl *sdr_ctrl, + const u32 sdram_start, const u32 sdram_end) { struct sdram_prot_rule rule; int rules; @@ -185,7 +204,7 @@ sdram_set_protection_config(const u32 sdram_start, const u32 sdram_end) for (rules = 0; rules < 20; rules++) { rule.rule = rules; - sdram_set_rule(&rule); + sdram_set_rule(sdr_ctrl, &rule); } /* new rule: accept SDRAM */ @@ -200,13 +219,13 @@ sdram_set_protection_config(const u32 sdram_start, const u32 sdram_end) rule.rule = 0; /* set new rule */ - sdram_set_rule(&rule); + sdram_set_rule(sdr_ctrl, &rule); /* default rule: reject everything */ writel(0x3ff, &sdr_ctrl->protport_default); } -static void sdram_dump_protection_config(void) +static void sdram_dump_protection_config(struct socfpga_sdr_ctrl *sdr_ctrl) { struct sdram_prot_rule rule; int rules; @@ -216,7 +235,7 @@ static void sdram_dump_protection_config(void) for (rules = 0; rules < 20; rules++) { rule.rule = rules; - sdram_get_rule(&rule); + sdram_get_rule(sdr_ctrl, &rule); debug("Rule %d, rules ...\n", rules); debug(" sdram start %x\n", rule.sdram_start); debug(" sdram end %x\n", rule.sdram_end); @@ -322,7 +341,8 @@ static u32 sdr_get_addr_rw(const struct socfpga_sdram_config *cfg) * * This function loads the register values into the SDRAM controller block. */ -static void sdr_load_regs(const struct socfpga_sdram_config *cfg) +static void sdr_load_regs(struct socfpga_sdr_ctrl *sdr_ctrl, + const struct socfpga_sdram_config *cfg) { const u32 ctrl_cfg = sdr_get_ctrlcfg(cfg); const u32 dram_addrw = sdr_get_addr_rw(cfg); @@ -426,7 +446,8 @@ static void sdr_load_regs(const struct socfpga_sdram_config *cfg) * * Initialize the SDRAM MMR. */ -int sdram_mmr_init_full(unsigned int sdr_phy_reg) +int sdram_mmr_init_full(struct socfpga_sdr_ctrl *sdr_ctrl, + unsigned int sdr_phy_reg) { const struct socfpga_sdram_config *cfg = socfpga_get_sdram_config(); const unsigned int rows = @@ -436,7 +457,7 @@ int sdram_mmr_init_full(unsigned int sdr_phy_reg) writel(rows, &sysmgr_regs->iswgrp_handoff[4]); - sdr_load_regs(cfg); + sdr_load_regs(sdr_ctrl, cfg); /* saving this value to SYSMGR.ISWGRP.HANDOFF.FPGA2SDR */ writel(cfg->fpgaport_rst, &sysmgr_regs->iswgrp_handoff[3]); @@ -459,9 +480,10 @@ int sdram_mmr_init_full(unsigned int sdr_phy_reg) SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK, 1 << SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB); - sdram_set_protection_config(0, sdram_calculate_size() - 1); + sdram_set_protection_config(sdr_ctrl, 0, + sdram_calculate_size(sdr_ctrl) - 1); - sdram_dump_protection_config(); + sdram_dump_protection_config(sdr_ctrl); return 0; } @@ -472,7 +494,7 @@ int sdram_mmr_init_full(unsigned int sdr_phy_reg) * Calculate SDRAM device size based on SDRAM controller parameters. * Size is specified in bytes. */ -unsigned long sdram_calculate_size(void) +static unsigned long sdram_calculate_size(struct socfpga_sdr_ctrl *sdr_ctrl) { unsigned long temp; unsigned long row, bank, col, cs, width; @@ -534,3 +556,94 @@ unsigned long sdram_calculate_size(void) return temp; } + +static int altera_gen5_sdram_ofdata_to_platdata(struct udevice *dev) +{ + struct altera_gen5_sdram_platdata *plat = dev->platdata; + + plat->sdr = (struct socfpga_sdr *)devfdt_get_addr_index(dev, 0); + if (!plat->sdr) + return -ENODEV; + + return 0; +} + +static int altera_gen5_sdram_probe(struct udevice *dev) +{ + int ret; + unsigned long sdram_size; + struct altera_gen5_sdram_platdata *plat = dev->platdata; + struct altera_gen5_sdram_priv *priv = dev_get_priv(dev); + struct socfpga_sdr_ctrl *sdr_ctrl = &plat->sdr->sdr_ctrl; + struct reset_ctl_bulk resets; + + ret = reset_get_bulk(dev, &resets); + if (ret) { + dev_err(dev, "Can't get reset: %d\n", ret); + return -ENODEV; + } + reset_deassert_bulk(&resets); + + if (sdram_mmr_init_full(sdr_ctrl, 0xffffffff) != 0) { + puts("SDRAM init failed.\n"); + goto failed; + } + + debug("SDRAM: Calibrating PHY\n"); + /* SDRAM calibration */ + if (sdram_calibration_full(plat->sdr) == 0) { + puts("SDRAM calibration failed.\n"); + goto failed; + } + + sdram_size = sdram_calculate_size(sdr_ctrl); + debug("SDRAM: %ld MiB\n", sdram_size >> 20); + + /* Sanity check ensure correct SDRAM size specified */ + if (get_ram_size(0, sdram_size) != sdram_size) { + puts("SDRAM size check failed!\n"); + goto failed; + } + + priv->info.base = 0; + priv->info.size = sdram_size; + + return 0; + +failed: + reset_release_bulk(&resets); + return -ENODEV; +} + +static int altera_gen5_sdram_get_info(struct udevice *dev, + struct ram_info *info) +{ + struct altera_gen5_sdram_priv *priv = dev_get_priv(dev); + + info->base = priv->info.base; + info->size = priv->info.size; + + return 0; +} + +static struct ram_ops altera_gen5_sdram_ops = { + .get_info = altera_gen5_sdram_get_info, +}; + +static const struct udevice_id altera_gen5_sdram_ids[] = { + { .compatible = "altr,sdr-ctl" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(altera_gen5_sdram) = { + .name = "altr_sdr_ctl", + .id = UCLASS_RAM, + .of_match = altera_gen5_sdram_ids, + .ops = &altera_gen5_sdram_ops, + .ofdata_to_platdata = altera_gen5_sdram_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct altera_gen5_sdram_platdata), + .probe = altera_gen5_sdram_probe, + .priv_auto_alloc_size = sizeof(struct altera_gen5_sdram_priv), +}; + +#endif /* CONFIG_SPL_BUILD */ diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c index 5e7a943b68..0e4526288e 100644 --- a/drivers/ddr/altera/sequencer.c +++ b/drivers/ddr/altera/sequencer.c @@ -3705,12 +3705,19 @@ static void initialize_tracking(void) &sdr_reg_file->trk_rfsh); } -int sdram_calibration_full(void) +int sdram_calibration_full(struct socfpga_sdr *sdr) { struct param_type my_param; struct gbl_type my_gbl; u32 pass; + /* + * For size reasons, this file uses hard coded addresses. + * Check if we are called with the correct address. + */ + if (sdr != (struct socfpga_sdr *)SOCFPGA_SDR_ADDRESS) + return -ENODEV; + memset(&my_param, 0, sizeof(my_param)); memset(&my_gbl, 0, sizeof(my_gbl)); diff --git a/drivers/ddr/altera/sequencer.h b/drivers/ddr/altera/sequencer.h index a5760b03a5..d7f6935201 100644 --- a/drivers/ddr/altera/sequencer.h +++ b/drivers/ddr/altera/sequencer.h @@ -223,4 +223,39 @@ struct socfpga_data_mgr { u32 mem_t_add; u32 t_rl_add; }; + +/* This struct describes the controller @ SOCFPGA_SDR_ADDRESS */ +struct socfpga_sdr { + /* SDR_PHYGRP_SCCGRP_ADDRESS */ + u8 _align1[0xe00]; + /* SDR_PHYGRP_SCCGRP_ADDRESS | 0xe00 */ + struct socfpga_sdr_scc_mgr sdr_scc_mgr; + u8 _align2[0x1bc]; + /* SDR_PHYGRP_PHYMGRGRP_ADDRESS */ + struct socfpga_phy_mgr_cmd phy_mgr_cmd; + u8 _align3[0x2c]; + /* SDR_PHYGRP_PHYMGRGRP_ADDRESS | 0x40 */ + struct socfpga_phy_mgr_cfg phy_mgr_cfg; + u8 _align4[0xfa0]; + /* SDR_PHYGRP_RWMGRGRP_ADDRESS */ + u8 rwmgr_grp[0x800]; + /* SDR_PHYGRP_RWMGRGRP_ADDRESS | 0x800 */ + struct socfpga_sdr_rw_load_manager sdr_rw_load_mgr_regs; + u8 _align5[0x3f0]; + /* SDR_PHYGRP_RWMGRGRP_ADDRESS | 0xC00 */ + struct socfpga_sdr_rw_load_jump_manager sdr_rw_load_jump_mgr_regs; + u8 _align6[0x13f0]; + /* SDR_PHYGRP_DATAMGRGRP_ADDRESS */ + struct socfpga_data_mgr data_mgr; + u8 _align7[0x7f0]; + /* SDR_PHYGRP_REGFILEGRP_ADDRESS */ + struct socfpga_sdr_reg_file sdr_reg_file; + u8 _align8[0x7c8]; + /* SDR_CTRLGRP_ADDRESS */ + struct socfpga_sdr_ctrl sdr_ctrl; + u8 _align9[0xea4]; +}; + +int sdram_calibration_full(struct socfpga_sdr *sdr); + #endif /* _SEQUENCER_H_ */ From patchwork Thu Feb 21 21:43:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Goldschmidt X-Patchwork-Id: 1046467 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Enk6aAvb"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 4457Ms4qrLz9s2R for ; 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Thu, 21 Feb 2019 13:43:43 -0800 (PST) Received: from ubuntu.home ([2a02:8071:6a3:700:9065:254c:ff38:3288]) by smtp.gmail.com with ESMTPSA id m26sm4308wmg.13.2019.02.21.13.43.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 21 Feb 2019 13:43:42 -0800 (PST) From: Simon Goldschmidt To: Marek Vasut , u-boot@lists.denx.de Date: Thu, 21 Feb 2019 22:43:28 +0100 Message-Id: <20190221214332.4246-5-simon.k.r.goldschmidt@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190221214332.4246-1-simon.k.r.goldschmidt@gmail.com> References: <20190221214332.4246-1-simon.k.r.goldschmidt@gmail.com> Cc: Miquel Raynal Subject: [U-Boot] [PATCH v2 4/8] mtd: rawnand: denali: add reset handling X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This adds reset handling to the devicetree-enabled Denali NAND driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt --- Changes in v2: - fix copy/paste issues - add .remove callback to release the resets drivers/mtd/nand/raw/denali.h | 2 ++ drivers/mtd/nand/raw/denali_dt.c | 14 ++++++++++++++ 2 files changed, 16 insertions(+) diff --git a/drivers/mtd/nand/raw/denali.h b/drivers/mtd/nand/raw/denali.h index 019deda094..63ae828768 100644 --- a/drivers/mtd/nand/raw/denali.h +++ b/drivers/mtd/nand/raw/denali.h @@ -10,6 +10,7 @@ #include #include #include +#include #define DEVICE_RESET 0x0 #define DEVICE_RESET__BANK(bank) BIT(bank) @@ -315,6 +316,7 @@ struct denali_nand_info { void (*host_write)(struct denali_nand_info *denali, u32 addr, u32 data); void (*setup_dma)(struct denali_nand_info *denali, dma_addr_t dma_addr, int page, int write); + struct reset_ctl_bulk resets; }; #define DENALI_CAP_HW_ECC_FIXUP BIT(0) diff --git a/drivers/mtd/nand/raw/denali_dt.c b/drivers/mtd/nand/raw/denali_dt.c index d384b974df..a92abca022 100644 --- a/drivers/mtd/nand/raw/denali_dt.c +++ b/drivers/mtd/nand/raw/denali_dt.c @@ -131,15 +131,29 @@ static int denali_dt_probe(struct udevice *dev) denali->clk_x_rate = 200000000; } + ret = reset_get_bulk(dev, &denali->resets); + if (ret) + dev_warn(dev, "Can't get reset: %d\n", ret); + else + reset_deassert_bulk(&denali->resets); + return denali_init(denali); } +static int denali_dt_remove(struct udevice *dev) +{ + struct denali_nand_info *denali = dev_get_priv(dev); + + return reset_release_bulk(&denali->resets); +} + U_BOOT_DRIVER(denali_nand_dt) = { .name = "denali-nand-dt", .id = UCLASS_MISC, .of_match = denali_nand_dt_ids, .probe = denali_dt_probe, .priv_auto_alloc_size = sizeof(struct denali_nand_info), + .remove = denali_dt_remove, }; void board_nand_init(void) From patchwork Thu Feb 21 21:43:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Goldschmidt X-Patchwork-Id: 1046471 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; 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For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt --- Changes in v2: - add .remove callback to release the resets drivers/spi/cadence_qspi.c | 16 ++++++++++++++++ drivers/spi/cadence_qspi.h | 4 ++++ 2 files changed, 20 insertions(+) diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index 11fce9c4fe..3bfa0201c4 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include "cadence_qspi.h" @@ -154,10 +155,17 @@ static int cadence_spi_probe(struct udevice *bus) { struct cadence_spi_platdata *plat = bus->platdata; struct cadence_spi_priv *priv = dev_get_priv(bus); + int ret; priv->regbase = plat->regbase; priv->ahbbase = plat->ahbbase; + ret = reset_get_bulk(bus, &priv->resets); + if (ret) + dev_warn(bus, "Can't get reset: %d\n", ret); + else + reset_deassert_bulk(&priv->resets); + if (!priv->qspi_is_init) { cadence_qspi_apb_controller_init(plat); priv->qspi_is_init = 1; @@ -166,6 +174,13 @@ static int cadence_spi_probe(struct udevice *bus) return 0; } +static int cadence_spi_remove(struct udevice *dev) +{ + struct cadence_spi_priv *priv = dev_get_priv(dev); + + return reset_release_bulk(&priv->resets); +} + static int cadence_spi_set_mode(struct udevice *bus, uint mode) { struct cadence_spi_priv *priv = dev_get_priv(bus); @@ -342,4 +357,5 @@ U_BOOT_DRIVER(cadence_spi) = { .platdata_auto_alloc_size = sizeof(struct cadence_spi_platdata), .priv_auto_alloc_size = sizeof(struct cadence_spi_priv), .probe = cadence_spi_probe, + .remove = cadence_spi_remove, }; diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h index 055900def0..d4ede6e15e 100644 --- a/drivers/spi/cadence_qspi.h +++ b/drivers/spi/cadence_qspi.h @@ -7,6 +7,8 @@ #ifndef __CADENCE_QSPI_H__ #define __CADENCE_QSPI_H__ +#include + #define CQSPI_IS_ADDR(cmd_len) (cmd_len > 1 ? 1 : 0) #define CQSPI_NO_DECODER_MAX_CS 4 @@ -42,6 +44,8 @@ struct cadence_spi_priv { unsigned int qspi_calibrated_hz; unsigned int qspi_calibrated_cs; unsigned int previous_hz; + + struct reset_ctl_bulk resets; }; /* Functions call declaration */ From patchwork Thu Feb 21 21:43:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Goldschmidt X-Patchwork-Id: 1046466 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="De336kzO"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 4457Mm6YT8z9s2R for ; Fri, 22 Feb 2019 08:46:28 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 7232DC21F3E; Thu, 21 Feb 2019 21:45:10 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=FREEMAIL_FROM, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 774CEC21F82; Thu, 21 Feb 2019 21:43:56 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 3D059C21F51; Thu, 21 Feb 2019 21:43:49 +0000 (UTC) Received: from mail-wm1-f66.google.com (mail-wm1-f66.google.com [209.85.128.66]) by lists.denx.de (Postfix) with ESMTPS id 09AF8C21F53 for ; Thu, 21 Feb 2019 21:43:46 +0000 (UTC) Received: by mail-wm1-f66.google.com with SMTP id z84so106522wmg.4 for ; Thu, 21 Feb 2019 13:43:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=dGvmOqGdTHuZNYwumBpTg5PwfdplIkmuysPEC1cwVIc=; b=De336kzOH7nlj0iXpfmTZk7BbHVV6T+Js/JsM9fRBuCBFc3eaBTFYqJETcfPsMiAyA y8Dqr3MRzxagvXB3R1HL7X2K24TgWzQXv1hbrfb6UXvsqaCsG9Zd1E1e8/pzDCaXEeJh if3zbWEUj7om1cLExSje4zABiY73N0aTgBrwm+74PKU5DnoFlDbBAwuv97HcV1F6mYdA tCvtkLMcrlWaE4iD8iJf0+On6pf5zLlx/U6Hbzsqfk4hMZ9Hz5AA7A6QhX6zEDf0tGSf WdVUZ2Ze2rl1iUV60IhYYKPBJ9wkY/VmPoeJM7AUYjzEerlkXRaE6qkt998UwiF8+lYd UhJA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=dGvmOqGdTHuZNYwumBpTg5PwfdplIkmuysPEC1cwVIc=; b=hN9EpQRnYAG8DdIGS+aKr4sOzVV1VoMWsqpZxWjoQGTbg4M6PjrVsNzDv77ypcGgrA e7sA4Ce5CIT4lFIeHRXCv9rDQU/bFNbmUybj2TaEEGCNsviqEWASvF3dzE2kAhPN/kl5 7XGMzsILhPVInXb9wV3t9cZJvvKZAIpxpRS5qsWiOnlF+0aoTyI9HE6Los4O9CemBtYU izdTfSYXhZHfiOGQKMwvClwBodSiMJnJA4bvkfP0kpMQwjHq++ZEmxHFNYIewmByVqcX 2StwoVzgy5uwNXtiW2kRUaBJChTxU99TyV1YkI+5fsFBlHW2ZWsPDOMKY8R3Stdhspb1 Czfg== X-Gm-Message-State: AHQUAuaiqQ2LWW9yrml57BdAcBBjwqn86OfjrYWTnHJYUMRzvv8UI/2P vmlBg5A7pcM5KMJQ3UScy/s= X-Google-Smtp-Source: AHgI3IasikxPB7Y2698WTAU4s6Py2ORkCLhkLf+/19qTbK5gGGYkLEgp/pvHd+oe5KsF9nSM4+jfGA== X-Received: by 2002:a1c:4844:: with SMTP id v65mr381171wma.66.1550785425749; Thu, 21 Feb 2019 13:43:45 -0800 (PST) Received: from ubuntu.home ([2a02:8071:6a3:700:9065:254c:ff38:3288]) by smtp.gmail.com with ESMTPSA id m26sm4308wmg.13.2019.02.21.13.43.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 21 Feb 2019 13:43:45 -0800 (PST) From: Simon Goldschmidt To: Marek Vasut , u-boot@lists.denx.de Date: Thu, 21 Feb 2019 22:43:30 +0100 Message-Id: <20190221214332.4246-7-simon.k.r.goldschmidt@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190221214332.4246-1-simon.k.r.goldschmidt@gmail.com> References: <20190221214332.4246-1-simon.k.r.goldschmidt@gmail.com> Subject: [U-Boot] [PATCH v2 6/8] reset: socfpga: add reset handling for old kernels X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This adds code to take peripherals out of reset based on an environment variable. This is in preparation for removing the code that does this from SPL. However, some drivers even in current Linux cannot handle peripheral reset, so until this works, we need a compatibility workaround. This workaround is implemented in the 'remove' callback of this reset driver, which is called on OS_PREPARE: it checks if the environment variable "socfpga_permodrst_ungate" - if it is set to 1, it deasserts all peripheral resets, which is what the gen5 SPL did up to now. This is in preparation to clean up the SPL and implementing proper reset handling for U-Boot. Signed-off-by: Simon Goldschmidt --- Changes in v2: - moved from Kernel option "OLD_SOCFPGA_KERNEL_COMPAT" to environment variable "socfpga_permodrst_ungate" drivers/reset/reset-socfpga.c | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c index b2acfcd2ec..749f671e05 100644 --- a/drivers/reset/reset-socfpga.c +++ b/drivers/reset/reset-socfpga.c @@ -89,6 +89,36 @@ static int socfpga_reset_probe(struct udevice *dev) return 0; } +#ifndef CONFIG_SPL_BUILD +/* + * This remove function is called before starting OS to deassert peripheral + * resets for Kernels that don't support this. + * + * The reset driver checks the environment variable "socfpga_permodrst_ungate" + * when it is removed. If this variable is '1', all peripherals in 'permodrst' + * are taken out of reset before booting into the OS. + * This should be required for gen5 systems only that are running Linux kernels + * without proper peripheral reset support for all drivers used. + */ +static int socfpga_reset_remove(struct udevice *dev) +{ + struct socfpga_reset_data *data = dev_get_priv(dev); + const char *env_str; + long val; + + env_str = env_get("socfpga_permodrst_ungate"); + if (env_str) { + val = simple_strtol(env_str, NULL, 0); + if (val == 1) { + puts("Deasserting all peripheral resets\n"); + writel(0, data->membase + 4); + } + } + + return 0; +} +#endif + static const struct udevice_id socfpga_reset_match[] = { { .compatible = "altr,rst-mgr" }, { /* sentinel */ }, @@ -101,4 +131,8 @@ U_BOOT_DRIVER(socfpga_reset) = { .probe = socfpga_reset_probe, .priv_auto_alloc_size = sizeof(struct socfpga_reset_data), .ops = &socfpga_reset_ops, +#ifndef CONFIG_SPL_BUILD + .remove = socfpga_reset_remove, + .flags = DM_FLAG_OS_PREPARE, +#endif }; From patchwork Thu Feb 21 21:43:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Goldschmidt X-Patchwork-Id: 1046468 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="fGCnklKq"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 4457NC4rv5z9s2R for ; Fri, 22 Feb 2019 08:46:51 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 58DEFC21F51; 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Thu, 21 Feb 2019 13:43:46 -0800 (PST) Received: from ubuntu.home ([2a02:8071:6a3:700:9065:254c:ff38:3288]) by smtp.gmail.com with ESMTPSA id m26sm4308wmg.13.2019.02.21.13.43.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 21 Feb 2019 13:43:46 -0800 (PST) From: Simon Goldschmidt To: Marek Vasut , u-boot@lists.denx.de Date: Thu, 21 Feb 2019 22:43:31 +0100 Message-Id: <20190221214332.4246-8-simon.k.r.goldschmidt@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190221214332.4246-1-simon.k.r.goldschmidt@gmail.com> References: <20190221214332.4246-1-simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee , Tom Rini , Joe Hershberger , Stefan Roese Subject: [U-Boot] [PATCH v2 7/8] arm: socfpga: gen5: deassert peripheral reset by default X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" To keep the current behaviour of taking all peripherals out of reset before booting the OS before removing that code from socfpga gen5 SPL, this enables the new behaviour by default for all gen5 boards by adding the environment variable "socfpga_permodrst_ungate=1" to the default environment. This can be overridden in board config files or by saving an environment without this variable enabled. Signed-off-by: Simon Goldschmidt --- Changes in v2: - this patch is new in v2 include/configs/socfpga_common.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index c9cbf8f5e3..2510c6fd7b 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -321,6 +321,19 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #include +#ifdef CONFIG_TARGET_SOCFPGA_GEN5 +/* + * Handle compatibility for peripheral reset for Linux kernels that haven't + * implemented peripheral reset for all drivers. + * Define this to "" disable this compatibility. + */ +#ifndef SOCFPGA_PERMODRST_UNGATE +#define SOCFPGA_PERMODRST_UNGATE "socfpga_permodrst_ungate=1\0" +#endif +#else +#define SOCFPGA_PERMODRST_UNGATE "" +#endif + #ifndef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ @@ -330,6 +343,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void); "scriptaddr=0x02100000\0" \ "pxefile_addr_r=0x02200000\0" \ "ramdisk_addr_r=0x02300000\0" \ + SOCFPGA_PERMODRST_UNGATE \ BOOTENV #endif From patchwork Thu Feb 21 21:43:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Goldschmidt X-Patchwork-Id: 1046469 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="tuctRQ2q"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 4457NV2Gfyz9s2R for ; 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Thu, 21 Feb 2019 13:43:47 -0800 (PST) Received: from ubuntu.home ([2a02:8071:6a3:700:9065:254c:ff38:3288]) by smtp.gmail.com with ESMTPSA id m26sm4308wmg.13.2019.02.21.13.43.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 21 Feb 2019 13:43:47 -0800 (PST) From: Simon Goldschmidt To: Marek Vasut , u-boot@lists.denx.de Date: Thu, 21 Feb 2019 22:43:32 +0100 Message-Id: <20190221214332.4246-9-simon.k.r.goldschmidt@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190221214332.4246-1-simon.k.r.goldschmidt@gmail.com> References: <20190221214332.4246-1-simon.k.r.goldschmidt@gmail.com> Cc: Tom Rini Subject: [U-Boot] [PATCH v2 8/8] arm: socfpga: implement proper peripheral reset X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This commit removes ad-hoc reset handling for peripheral resets from SPL for socfpga gen5. This is done because as U-Boot drivers support reset handling by now. Signed-off-by: Simon Goldschmidt --- Changes in v2: - removed Kconfig option OLD_SOCFPGA_KERNEL_COMPAT since compatibility now uses an environment variable arch/arm/mach-socfpga/misc_gen5.c | 10 ---------- arch/arm/mach-socfpga/spl_gen5.c | 10 ---------- 2 files changed, 20 deletions(-) diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c index 6e11ba6cb2..9865f5b5b1 100644 --- a/arch/arm/mach-socfpga/misc_gen5.c +++ b/arch/arm/mach-socfpga/misc_gen5.c @@ -201,16 +201,6 @@ int arch_early_init_r(void) /* Add device descriptor to FPGA device table */ socfpga_fpga_add(&altera_fpga[0]); -#ifdef CONFIG_DESIGNWARE_SPI - /* Get Designware SPI controller out of reset */ - socfpga_per_reset(SOCFPGA_RESET(SPIM0), 0); - socfpga_per_reset(SOCFPGA_RESET(SPIM1), 0); -#endif - -#ifdef CONFIG_NAND_DENALI - socfpga_per_reset(SOCFPGA_RESET(NAND), 0); -#endif - return 0; } diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c index 1bff8cbfcf..e1e65261eb 100644 --- a/arch/arm/mach-socfpga/spl_gen5.c +++ b/arch/arm/mach-socfpga/spl_gen5.c @@ -36,16 +36,12 @@ u32 spl_boot_device(void) return BOOT_DEVICE_RAM; case 0x2: /* NAND Flash (1.8V) */ case 0x3: /* NAND Flash (3.0V) */ - socfpga_per_reset(SOCFPGA_RESET(NAND), 0); return BOOT_DEVICE_NAND; case 0x4: /* SD/MMC External Transceiver (1.8V) */ case 0x5: /* SD/MMC Internal Transceiver (3.0V) */ - socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0); - socfpga_per_reset(SOCFPGA_RESET(DMA), 0); return BOOT_DEVICE_MMC1; case 0x6: /* QSPI Flash (1.8V) */ case 0x7: /* QSPI Flash (3.0V) */ - socfpga_per_reset(SOCFPGA_RESET(QSPI), 0); return BOOT_DEVICE_SPI; default: printf("Invalid boot device (bsel=%08x)!\n", bsel); @@ -99,9 +95,7 @@ void board_init_f(ulong dummy) socfpga_bridges_reset(1); } - socfpga_per_reset(SOCFPGA_RESET(UART0), 0); socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0); - timer_init(); debug("Reconfigure Clock Manager\n"); @@ -123,10 +117,6 @@ void board_init_f(ulong dummy) sysmgr_pinmux_init(); sysmgr_config_warmrstcfgio(0); - /* De-assert reset for peripherals and bridges based on handoff */ - reset_deassert_peripherals_handoff(); - socfpga_bridges_reset(0); - debug("Unfreezing/Thaw all I/O banks\n"); /* unfreeze / thaw all IO banks */ sys_mgr_frzctrl_thaw_req();