From patchwork Thu Feb 21 18:03:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dong Aisheng X-Patchwork-Id: 1046351 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=nxp.com header.i=@nxp.com header.b="cuaZnP14"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 4452R01PWwz9s70 for ; Fri, 22 Feb 2019 05:03:56 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726361AbfBUSDz (ORCPT ); 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Thu, 21 Feb 2019 18:03:44 +0000 From: Aisheng Dong To: "linux-clk@vger.kernel.org" CC: "linux-arm-kernel@lists.infradead.org" , "sboyd@kernel.org" , "mturquette@baylibre.com" , "shawnguo@kernel.org" , Fabio Estevam , dl-linux-imx , "kernel@pengutronix.de" , Aisheng Dong , Rob Herring , "devicetree@vger.kernel.org" Subject: [PATCH 1/4] dt-bindings: firmware: imx-scu: new binding to parse clocks from device tree Thread-Topic: [PATCH 1/4] dt-bindings: firmware: imx-scu: new binding to parse clocks from device tree Thread-Index: AQHUyg/ILVDNycVxtkiL1Tyb3hPiwQ== Date: Thu, 21 Feb 2019 18:03:43 +0000 Message-ID: <1550771836-10014-2-git-send-email-aisheng.dong@nxp.com> References: <1550771836-10014-1-git-send-email-aisheng.dong@nxp.com> In-Reply-To: <1550771836-10014-1-git-send-email-aisheng.dong@nxp.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.7.4 x-clientproxiedby: HK2PR04CA0044.apcprd04.prod.outlook.com (2603:1096:202:14::12) To VI1PR04MB4222.eurprd04.prod.outlook.com (2603:10a6:803:3e::21) authentication-results: spf=none (sender IP is ) smtp.mailfrom=aisheng.dong@nxp.com; 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SFS:(10009020)(136003)(396003)(376002)(366004)(39860400002)(346002)(189003)(199004)(2906002)(8936002)(186003)(81156014)(4326008)(71200400001)(71190400001)(6506007)(97736004)(99286004)(102836004)(26005)(50226002)(2351001)(6512007)(68736007)(81166006)(386003)(3846002)(14454004)(6116002)(476003)(316002)(8676002)(5660300002)(478600001)(54906003)(2616005)(25786009)(44832011)(36756003)(305945005)(446003)(105586002)(106356001)(6486002)(486006)(76176011)(7736002)(14444005)(53936002)(66066001)(52116002)(256004)(2501003)(6436002)(5640700003)(11346002)(6916009)(86362001); DIR:OUT; SFP:1101; SCL:1; SRVR:VI1PR04MB1663; H:VI1PR04MB4222.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: EAXG5fsPFZXOIG/XsMSByP1sZoh9CHr+6uiA3aoC6pn5Q/Ht/qmWs9zNnoQe/7IlbFkEDFrmVZw3UVZ+yQuLZg8E6XLMkie2YHHol5pusMnEbz1m1YIheecVFpzks+cgykgle9i3UPACCwaqlmn7PEd450hafg6Pd0OUuTwcMaocbNKe3OVggDMcP2hD86Cz7J0PCkmYdKbAwCRo/DCt2HPetvJ80fDtcSTUlS1zJaZMJJ3pK8HGZdS/0afXNaGUESUU0ITxR0G0c3SVoF6GLs7weSQjA6Ed3nNp8bxz6cxNxxqNsaHgU0TlfQuCKwBtmeK+pTwkw/NWhthXjJnzvtPVR37ev+XAGLRCV/boNEi5XCEGcLWCAGFr6mIrZ4AZROzjMJu3Ic1Invk0cuXBFTrhdLFMA0XTtgmqOhKEtnM= MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 9e8aff01-a314-4eea-74a6-08d69826eae4 X-MS-Exchange-CrossTenant-originalarrivaltime: 21 Feb 2019 18:03:40.2800 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB1663 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org There's a few limitations on one cell clock binding (#clock-cells = <1>) that we have to define all clock IDs for device tree to reference. This may cause troubles if we want to use common clock IDs for multi platforms support when the clock of those platforms are mostly the same. e.g. Current clock IDs name are defined with SS prefix. However the device may reside in different SS across CPUs, that means the SS prefix may not valid anymore for a new SoC. Furthermore, the device availability of those clocks may also vary a bit. For such situation, We formerly planned to add all new IDs for each SS and dynamically check availability for different SoC in driver. That can be done but that may involve a lot effort and may result in more changes and duplicated code in driver, also make device tree upstreaming hard which depends on Clock IDs. To relief this situation, we want to move the clock definition into device tree which can fully decouple the dependency of Clock ID definition from device tree. And no frequent changes required in clock driver any more. Then we can use the existence of clock nodes in device tree to address the device and clock availability differences across different SoCs. For SCU clocks, only two params required, thus two new property created: rsrc-id = ; clk-type = ; And as we want to support clock set parent function, 'clocks' property is also used to pass all the possible input parents. Cc: Rob Herring Cc: Stephen Boyd Cc: Shawn Guo Cc: Sascha Hauer Cc: Michael Turquette Cc: devicetree@vger.kernel.org Signed-off-by: Dong Aisheng --- .../devicetree/bindings/arm/freescale/fsl,scu.txt | 29 ++++++++++++++++------ include/dt-bindings/firmware/imx/rsrc.h | 17 +++++++++++++ 2 files changed, 38 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt index 72d481c..2816789 100644 --- a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt +++ b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt @@ -78,6 +78,19 @@ Required properties: "fsl,imx8qm-clock" "fsl,imx8qxp-clock" followed by "fsl,scu-clk" +- #clock-cells: Should be 0. +- rsrc-id: Resource ID associated with this clock +- clk-type: Type of this clock. + Refer to for + available clock types supported by SCU. +- clock-output-names: Shall be the corresponding names of the outputs. + +Optional properties: +- clocks: Shall be the input parent clock(s) phandle for the clock. + For multiplexed clocks, the list order must match the hardware + programming order. + +Legacy Clock binding (DEPRECATED): - #clock-cells: Should be 1. Contains the Clock ID value. - clocks: List of clock specifiers, must contain an entry for each required entry in clock-names @@ -129,6 +142,13 @@ lsio_mu1: mailbox@5d1c0000 { #mbox-cells = <2>; }; +uart0_clk: uart0-clock-controller { + compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-clk"; + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; +}; + firmware { scu { compatible = "fsl,imx-scu"; @@ -143,11 +163,6 @@ firmware { &lsio_mu1 1 2 &lsio_mu1 1 3>; - clk: clk { - compatible = "fsl,imx8qxp-clk", "fsl,scu-clk"; - #clock-cells = <1>; - }; - iomuxc { compatible = "fsl,imx8qxp-iomuxc"; @@ -175,8 +190,6 @@ serial@5a060000 { ... pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lpuart0>; - clocks = <&clk IMX8QXP_UART0_CLK>, - <&clk IMX8QXP_UART0_IPG_CLK>; - clock-names = "per", "ipg"; + clocks = <&uart0_clk>; power-domains = <&pd IMX_SC_R_UART_0>; }; diff --git a/include/dt-bindings/firmware/imx/rsrc.h b/include/dt-bindings/firmware/imx/rsrc.h index 4481f2d..f650fc3 100644 --- a/include/dt-bindings/firmware/imx/rsrc.h +++ b/include/dt-bindings/firmware/imx/rsrc.h @@ -556,4 +556,21 @@ #define IMX_SC_R_VPU 540 #define IMX_SC_R_LAST 541 +/* + * Defines for SC PM CLK + */ +#define IMX_SC_PM_CLK_SLV_BUS 0 /* Slave bus clock */ +#define IMX_SC_PM_CLK_MST_BUS 1 /* Master bus clock */ +#define IMX_SC_PM_CLK_PER 2 /* Peripheral clock */ +#define IMX_SC_PM_CLK_PHY 3 /* Phy clock */ +#define IMX_SC_PM_CLK_MISC 4 /* Misc clock */ +#define IMX_SC_PM_CLK_MISC0 0 /* Misc 0 clock */ +#define IMX_SC_PM_CLK_MISC1 1 /* Misc 1 clock */ +#define IMX_SC_PM_CLK_MISC2 2 /* Misc 2 clock */ +#define IMX_SC_PM_CLK_MISC3 3 /* Misc 3 clock */ +#define IMX_SC_PM_CLK_MISC4 4 /* Misc 4 clock */ +#define IMX_SC_PM_CLK_CPU 2 /* CPU clock */ +#define IMX_SC_PM_CLK_PLL 4 /* PLL */ +#define IMX_SC_PM_CLK_BYPASS 4 /* Bypass clock */ + #endif /* __DT_BINDINGS_RSCRC_IMX_H */ From patchwork Thu Feb 21 18:03:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dong Aisheng X-Patchwork-Id: 1046353 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=nxp.com header.i=@nxp.com header.b="klFXjV4X"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 4452R371bqz9s9L for ; Fri, 22 Feb 2019 05:03:59 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725866AbfBUSD6 (ORCPT ); Thu, 21 Feb 2019 13:03:58 -0500 Received: from mail-eopbgr40049.outbound.protection.outlook.com ([40.107.4.49]:61888 "EHLO EUR03-DB5-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726146AbfBUSD6 (ORCPT ); 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Same as SCU clock, we want to move the clock definition into device tree which can fully decouple the dependency of Clock ID definition from device tree. And no frequent changes required in clock driver any more to handle the difference. We can use the existence of clock nodes in device tree to address the device and clock availability differences across different SoCs. Cc: Rob Herring Cc: Stephen Boyd Cc: Shawn Guo Cc: Sascha Hauer Cc: Michael Turquette Cc: devicetree@vger.kernel.org Signed-off-by: Dong Aisheng --- Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt b/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt index 965cfa4..a317844 100644 --- a/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt +++ b/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt @@ -11,6 +11,20 @@ enabled by these control bits, it might still not be running based on the base resource. Required properties: +- compatible: Should be one of: + "fsl,imx8qxp-lpcg" + "fsl,imx8qm-lpcg" followed by "fsl,imx8qxp-lpcg". +- reg: Address and length of the register set. +- #clock-cells: Should be 1. One LPCG supports multiple clocks. +- clocks: Input parent clocks phandle array for each clock. +- bit-offset: An integer array indicating the bit offset for each clock. +- hw-autogate: Boolean array indicating whether supports HW autogate for + each clock. +- clock-output-names: Shall be the corresponding names of the outputs. + NOTE this property must be specified in the same order + as the clock bit-offset and hw-autogate property. + +Legacy binding (DEPRECATED): - compatible: Should be one of: "fsl,imx8qxp-lpcg-adma", "fsl,imx8qxp-lpcg-conn",