From patchwork Tue Feb 19 20:55:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shravan Kumar Ramani X-Patchwork-Id: 1044893 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=mellanox.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 443tLN18wcz9s6w for ; Wed, 20 Feb 2019 07:55:56 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726110AbfBSUzz (ORCPT ); Tue, 19 Feb 2019 15:55:55 -0500 Received: from mail-il-dmz.mellanox.com ([193.47.165.129]:50355 "EHLO mellanox.co.il" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726321AbfBSUzy (ORCPT ); Tue, 19 Feb 2019 15:55:54 -0500 Received: from Internal Mail-Server by MTLPINE1 (envelope-from sramani@mellanox.com) with ESMTPS (AES256-SHA encrypted); 19 Feb 2019 22:55:49 +0200 Received: from farm-0002.mtbu.labs.mlnx (farm-0002.mtbu.labs.mlnx [10.15.2.32]) by mtbu-labmailer.labs.mlnx (8.14.4/8.14.4) with ESMTP id x1JKtmEW026535; Tue, 19 Feb 2019 15:55:48 -0500 Received: (from sramani@localhost) by farm-0002.mtbu.labs.mlnx (8.14.7/8.13.8/Submit) id x1JKtgTM032250; Tue, 19 Feb 2019 15:55:42 -0500 From: Shravan Kumar Ramani To: Linus Walleij , Bartosz Golaszewski Cc: Shravan Kumar Ramani , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/1] gpio: add driver for Mellanox BlueField GPIO controller Date: Tue, 19 Feb 2019 15:55:29 -0500 Message-Id: X-Mailer: git-send-email 2.1.2 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This patch adds support for the GPIO controller used by Mellanox BlueField SOCs. Reviewed-by: David Woods Signed-off-by: Shravan Kumar Ramani --- drivers/gpio/Kconfig | 6 ++ drivers/gpio/Makefile | 1 + drivers/gpio/gpio-mlxbf.c | 246 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 253 insertions(+) create mode 100644 drivers/gpio/gpio-mlxbf.c diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index b5a2845..c950fe8 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -1292,6 +1292,12 @@ config GPIO_MERRIFIELD help Say Y here to support Intel Merrifield GPIO. +config GPIO_MLXBF + tristate "Mellanox BlueField SoC GPIO" + depends on (MELLANOX_PLATFORM && ARM64 && ACPI) || COMPILE_TEST + help + Say Y here if you want GPIO support on Mellanox BlueField SoC. + config GPIO_ML_IOH tristate "OKI SEMICONDUCTOR ML7213 IOH GPIO support" depends on X86 || COMPILE_TEST diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 37628f8..8d54279 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -83,6 +83,7 @@ obj-$(CONFIG_GPIO_MENZ127) += gpio-menz127.o obj-$(CONFIG_GPIO_MERRIFIELD) += gpio-merrifield.o obj-$(CONFIG_GPIO_MC33880) += gpio-mc33880.o obj-$(CONFIG_GPIO_MC9S08DZ60) += gpio-mc9s08dz60.o +obj-$(CONFIG_GPIO_MLXBF) += gpio-mlxbf.o obj-$(CONFIG_GPIO_ML_IOH) += gpio-ml-ioh.o obj-$(CONFIG_GPIO_MM_LANTIQ) += gpio-mm-lantiq.o obj-$(CONFIG_GPIO_MOCKUP) += gpio-mockup.o diff --git a/drivers/gpio/gpio-mlxbf.c b/drivers/gpio/gpio-mlxbf.c new file mode 100644 index 0000000..bf197aa --- /dev/null +++ b/drivers/gpio/gpio-mlxbf.c @@ -0,0 +1,246 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Number of pins on BlueField */ +#define MLXBF_GPIO_NR 54 + +/* Pad Electrical Controls. */ +#define GPIO_PAD_CONTROL__FIRST_WORD 0x0700 +#define GPIO_PAD_CONTROL_1__FIRST_WORD 0x0708 +#define GPIO_PAD_CONTROL_2__FIRST_WORD 0x0710 +#define GPIO_PAD_CONTROL_3__FIRST_WORD 0x0718 + +#define GPIO_PIN_DIR_I 0x1040 +#define GPIO_PIN_DIR_O 0x1048 +#define GPIO_PIN_STATE 0x1000 +#define GPIO_SCRATCHPAD 0x20 + +#ifdef CONFIG_PM +struct bluefield_context_save_regs { + u64 gpio_scratchpad; + u64 gpio_pad_control[MLXBF_GPIO_NR]; + u64 gpio_pin_dir_i; + u64 gpio_pin_dir_o; +}; +#endif + +/* Device state structure. */ +struct gpio_state { + struct gpio_chip gc; + + /* Must hold this lock to modify shared data. */ + spinlock_t lock; + + /* Memory Address */ + void __iomem *dc_base; + +#ifdef CONFIG_PM + struct bluefield_context_save_regs csave_regs; +#endif +}; + +static int gpio_bf_set_input(struct gpio_chip *chip, unsigned int offset) +{ + struct gpio_state *gs = gpiochip_get_data(chip); + u64 in; + u64 out; + + out = readq(gs->dc_base + GPIO_PIN_DIR_O); + in = readq(gs->dc_base + GPIO_PIN_DIR_I); + + writeq(out & ~BIT(offset), gs->dc_base + GPIO_PIN_DIR_O); + writeq(in | BIT(offset), gs->dc_base + GPIO_PIN_DIR_I); + + return 0; +} + +static int gpio_bf_set_output(struct gpio_chip *chip, unsigned int offset) +{ + struct gpio_state *gs = gpiochip_get_data(chip); + u64 in; + u64 out; + + out = readq(gs->dc_base + GPIO_PIN_DIR_O); + in = readq(gs->dc_base + GPIO_PIN_DIR_I); + + writeq(out | BIT(offset), gs->dc_base + GPIO_PIN_DIR_O); + writeq(in & ~BIT(offset), gs->dc_base + GPIO_PIN_DIR_I); + + return 0; +} + +static int gpio_bf_set_output_lock(struct gpio_chip *chip, + unsigned int offset, int value) +{ + struct gpio_state *gs = gpiochip_get_data(chip); + + spin_lock(&gs->lock); + gpio_bf_set_output(chip, offset); + spin_unlock(&gs->lock); + + return 0; +} + +static int gpio_bf_set_input_lock(struct gpio_chip *chip, unsigned int offset) +{ + struct gpio_state *gs = gpiochip_get_data(chip); + + spin_lock(&gs->lock); + gpio_bf_set_input(chip, offset); + spin_unlock(&gs->lock); + + return 0; +} + +static int gpio_bf_get(struct gpio_chip *chip, unsigned int offset) +{ + u64 value; + struct gpio_state *gs = gpiochip_get_data(chip); + + value = readq(gs->dc_base + GPIO_PIN_STATE); + + return (value >> offset) & 1; +} + +static void gpio_bf_set(struct gpio_chip *chip, unsigned int offset, int value) +{ + u64 data; + struct gpio_state *gs = gpiochip_get_data(chip); + + spin_lock(&gs->lock); + data = readq(gs->dc_base + GPIO_PIN_STATE); + + if (value) + data |= BIT(offset); + else + data &= ~BIT(offset); + writeq(data, gs->dc_base + GPIO_PIN_STATE); + spin_unlock(&gs->lock); +} + +static int gpiodrv_probe(struct platform_device *pdev) +{ + struct gpio_state *gs; + struct device *dev = &pdev->dev; + struct gpio_chip *gc; + struct resource *dc_res; + int ret; + + dc_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!dc_res) + return -EINVAL; + + gs = devm_kzalloc(&pdev->dev, sizeof(struct gpio_state), GFP_KERNEL); + if (!gs) + return -ENOMEM; + + gs->dc_base = devm_ioremap_resource(&pdev->dev, dc_res); + if (!gs->dc_base) + return -ENOMEM; + + gc = &gs->gc; + gc->direction_input = gpio_bf_set_input_lock; + gc->get = gpio_bf_get; + gc->direction_output = gpio_bf_set_output_lock; + gc->set = gpio_bf_set; + gc->label = dev_name(dev); + gc->parent = &pdev->dev; + gc->owner = THIS_MODULE; + gc->base = 0; + gc->ngpio = MLXBF_GPIO_NR; + + ret = devm_gpiochip_add_data(dev, &gs->gc, gs); + if (ret) { + dev_err(&pdev->dev, "Failed adding memory mapped gpiochip\n"); + goto err; + } + + spin_lock_init(&gs->lock); + platform_set_drvdata(pdev, gs); + dev_info(&pdev->dev, "registered Mellanox BlueField GPIO"); + return 0; + +err: + dev_err(&pdev->dev, "Probe, Failed\n"); + return ret; +} + +#ifdef CONFIG_PM +static int gpiodrv_suspend(struct platform_device *pdev, pm_message_t state) +{ + struct gpio_state *gs = platform_get_drvdata(pdev); + + gs->csave_regs.gpio_scratchpad = readq(gs->dc_base + GPIO_SCRATCHPAD); + gs->csave_regs.gpio_pad_control[0] = + readq(gs->dc_base + GPIO_PAD_CONTROL__FIRST_WORD); + gs->csave_regs.gpio_pad_control[1] = + readq(gs->dc_base + GPIO_PAD_CONTROL_1__FIRST_WORD); + gs->csave_regs.gpio_pad_control[2] = + readq(gs->dc_base + GPIO_PAD_CONTROL_2__FIRST_WORD); + gs->csave_regs.gpio_pad_control[3] = + readq(gs->dc_base + GPIO_PAD_CONTROL_3__FIRST_WORD); + gs->csave_regs.gpio_pin_dir_i = readq(gs->dc_base + GPIO_PIN_DIR_I); + gs->csave_regs.gpio_pin_dir_o = readq(gs->dc_base + GPIO_PIN_DIR_O); + + return 0; +} + +static int gpiodrv_resume(struct platform_device *pdev) +{ + struct gpio_state *gs = platform_get_drvdata(pdev); + + writeq(gs->csave_regs.gpio_scratchpad, gs->dc_base + GPIO_SCRATCHPAD); + writeq(gs->csave_regs.gpio_pad_control[0], gs->dc_base + + GPIO_PAD_CONTROL__FIRST_WORD); + writeq(gs->csave_regs.gpio_pad_control[1], gs->dc_base + + GPIO_PAD_CONTROL_1__FIRST_WORD); + writeq(gs->csave_regs.gpio_pad_control[2], gs->dc_base + + GPIO_PAD_CONTROL_2__FIRST_WORD); + writeq(gs->csave_regs.gpio_pad_control[3], gs->dc_base + + GPIO_PAD_CONTROL_3__FIRST_WORD); + writeq(gs->csave_regs.gpio_pin_dir_i, gs->dc_base + GPIO_PIN_DIR_I); + writeq(gs->csave_regs.gpio_pin_dir_o, gs->dc_base + GPIO_PIN_DIR_O); + + return 0; +} +#endif + +static const struct acpi_device_id gpiodrv_acpi_match[] = { + { "MLNXBF02", 0 }, + {} +}; +MODULE_DEVICE_TABLE(acpi, gpiodrv_acpi_match); + +static struct platform_driver gpiodrv_gpio_driver = { + .driver = { + .name = "gpiodrv", + .acpi_match_table = ACPI_PTR(gpiodrv_acpi_match), + }, + .probe = gpiodrv_probe, +#ifdef CONFIG_PM + .suspend = gpiodrv_suspend, + .resume = gpiodrv_resume, +#endif +}; + +module_platform_driver(gpiodrv_gpio_driver); + +MODULE_DESCRIPTION("Mellanox BlueField GPIO Driver"); +MODULE_AUTHOR("Mellanox Technologies"); +MODULE_LICENSE("GPL");