From patchwork Thu Feb 14 06:37:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "liwei (CM)" X-Patchwork-Id: 1041842 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=huawei.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 440RX45V7Tz9sN4 for ; Thu, 14 Feb 2019 17:37:24 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2405734AbfBNGhQ (ORCPT ); Thu, 14 Feb 2019 01:37:16 -0500 Received: from szxga01-in.huawei.com ([45.249.212.187]:2450 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S2405731AbfBNGhQ (ORCPT ); Thu, 14 Feb 2019 01:37:16 -0500 Received: from DGGEMM403-HUB.china.huawei.com (unknown [172.30.72.53]) by Forcepoint Email with ESMTP id 2B6C4177AAF109FCAA99; Thu, 14 Feb 2019 14:37:14 +0800 (CST) Received: from DGGEMM526-MBX.china.huawei.com ([169.254.8.222]) by DGGEMM403-HUB.china.huawei.com ([10.3.20.211]) with mapi id 14.03.0415.000; Thu, 14 Feb 2019 14:37:12 +0800 From: "liwei (CM)" To: Manivannan Sadhasivam , "vinholikatti@gmail.com" , "jejb@linux.vnet.ibm.com" , "martin.petersen@oracle.com" , "robh+dt@kernel.org" CC: "linux-scsi@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "devicetree@vger.kernel.org" , "john.stultz@linaro.org" , "amit.kucheria@linaro.org" , "guodong.xu@linaro.org" Subject: =?gb2312?b?tPC4tDogW1BBVENIIHYyIDIvM10gYXJtNjQ6IGR0czogaGlzaWxp?= =?gb2312?b?Y29uOiBoaTM2NzA6IEFkZCBVRlMgY29udHJvbGxlciBzdXBwb3J0?= Thread-Topic: [PATCH v2 2/3] arm64: dts: hisilicon: hi3670: Add UFS controller support Thread-Index: AQHUpMhqsIxwTfArFk+ccYDgjfW3NqXfFdiw Date: Thu, 14 Feb 2019 06:37:11 +0000 Message-ID: <1699CE87DE933F49876AD744B5DC140F0672AA14@dggemm526-mbx.china.huawei.com> References: <20190105072859.9134-1-manivannan.sadhasivam@linaro.org> <20190105072859.9134-3-manivannan.sadhasivam@linaro.org> In-Reply-To: <20190105072859.9134-3-manivannan.sadhasivam@linaro.org> Accept-Language: zh-CN, en-US Content-Language: zh-CN X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.189.155.72] MIME-Version: 1.0 X-CFilter-Loop: Reflected Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Fine to me. Thanks! Acked-by: Wei Li -----邮件原件----- 发件人: Manivannan Sadhasivam [mailto:manivannan.sadhasivam@linaro.org] 发送时间: 2019年1月5日 15:29 收件人: vinholikatti@gmail.com; jejb@linux.vnet.ibm.com; martin.petersen@oracle.com; liwei (CM); robh+dt@kernel.org 抄送: linux-scsi@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; devicetree@vger.kernel.org; john.stultz@linaro.org; amit.kucheria@linaro.org; guodong.xu@linaro.org; Manivannan Sadhasivam 主题: [PATCH v2 2/3] arm64: dts: hisilicon: hi3670: Add UFS controller support Add UFS controller support for HiSilicon HI3670 SoC. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi index 6ccdf5040ffd..285219dd657f 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi @@ -654,6 +654,24 @@ clock-names = "apb_pclk"; }; + /* UFS */ + ufs: ufs@ff3c0000 { + compatible = "hisilicon,hi3670-ufs", "jedec,ufs-2.1"; + /* 0: HCI standard */ + /* 1: UFS SYS CTRL */ + reg = <0x0 0xff3c0000 0x0 0x1000>, + <0x0 0xff3e0000 0x0 0x1000>; + interrupt-parent = <&gic>; + interrupts = ; + clocks = <&crg_ctrl HI3670_CLK_GATE_UFSIO_REF>, + <&crg_ctrl HI3670_CLK_GATE_UFS_SUBSYS>; + clock-names = "ref_clk", "phy_clk"; + freq-table-hz = <0 0>, <0 0>; + /* offset: 0x84; bit: 12 */ + resets = <&crg_rst 0x84 12>; + reset-names = "rst"; + }; + /* SD */ dwmmc1: dwmmc1@ff37f000 { compatible = "hisilicon,hi3670-dw-mshc";