From patchwork Fri Feb 1 03:36:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 1034561 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="TGSOet0x"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43rN7S1hGfz9s9G for ; Fri, 1 Feb 2019 14:36:36 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726634AbfBADgb (ORCPT ); Thu, 31 Jan 2019 22:36:31 -0500 Received: from hqemgate16.nvidia.com ([216.228.121.65]:19748 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725807AbfBADgb (ORCPT ); Thu, 31 Jan 2019 22:36:31 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 31 Jan 2019 19:35:48 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 31 Jan 2019 19:36:30 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 31 Jan 2019 19:36:30 -0800 Received: from HQMAIL103.nvidia.com (172.20.187.11) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 1 Feb 2019 03:36:29 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Fri, 1 Feb 2019 03:36:29 +0000 Received: from josephl-linux.nvidia.com (Not Verified[10.19.108.132]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Thu, 31 Jan 2019 19:36:29 -0800 From: Joseph Lo To: Thierry Reding , Jonathan Hunter , Daniel Lezcano , Thomas Gleixner CC: , , Joseph Lo , , , Rob Herring Subject: [PATCH V5 1/7] dt-bindings: timer: add Tegra210 timer Date: Fri, 1 Feb 2019 11:36:15 +0800 Message-ID: <20190201033621.16814-2-josephl@nvidia.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190201033621.16814-1-josephl@nvidia.com> References: <20190201033621.16814-1-josephl@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1548992148; bh=WYuizYEwPLMs4uXjU5D6aArbthr+CJvktgtG6XANlFw=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=TGSOet0xPPADj2oxOTdJm2NUbgw+cowhYFcMSLl+5lNF+l/7lurGdQnkdAN/NBFob OSuCn2TSRLEoSUkQu2bYjkUqQ5R6bt2zj7Q9DshzqLZpfFx9yoshRE7d3COG5jPOlk SBvjLeCU06+jPq8OWppD24P02QRRK+55hSUnCCL4I+gL/drTjZ/oCOkGFIzPpA+w2j aiUbvHqb4x32GoD6h4pw874YcD5F3iiDkUtG7OB8fFVvh9m0tfhkEcdkoyOPozTLdK qTA3MOmHPpMQBjg+g8DLThZxaRflkATPBC8YMQbFhlTlW2ygcjEyRACuYR2F+ThAF+ XdUrhBczyG4+g== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org The Tegra210 timer provides fourteen 29-bit timer counters and one 32-bit timestamp counter. The TMRs run at either a fixed 1 MHz clock rate derived from the oscillator clock (TMR0-TMR9) or directly at the oscillator clock (TMR10-TMR13). Each TMR can be programmed to generate one-shot periodic, or watchdog interrupts. Cc: Daniel Lezcano Cc: Thomas Gleixner Cc: linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: Joseph Lo Reviewed-by: Rob Herring --- v5: * no change v4: * no change v3: * no change v2: * list all the interrupts that are supported by tegra210 timers block * add RB tag from Rob. --- .../bindings/timer/nvidia,tegra210-timer.txt | 36 +++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.txt diff --git a/Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.txt b/Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.txt new file mode 100644 index 000000000000..032cda96fe0d --- /dev/null +++ b/Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.txt @@ -0,0 +1,36 @@ +NVIDIA Tegra210 timer + +The Tegra210 timer provides fourteen 29-bit timer counters and one 32-bit +timestamp counter. The TMRs run at either a fixed 1 MHz clock rate derived +from the oscillator clock (TMR0-TMR9) or directly at the oscillator clock +(TMR10-TMR13). Each TMR can be programmed to generate one-shot, periodic, +or watchdog interrupts. + +Required properties: +- compatible : "nvidia,tegra210-timer". +- reg : Specifies base physical address and size of the registers. +- interrupts : A list of 14 interrupts; one per each timer channels 0 through + 13. +- clocks : Must contain one entry, for the module clock. + See ../clocks/clock-bindings.txt for details. + +timer@60005000 { + compatible = "nvidia,tegra210-timer"; + reg = <0x0 0x60005000 0x0 0x400>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&tegra_car TEGRA210_CLK_TIMER>; + clock-names = "timer"; +}; From patchwork Fri Feb 1 03:36:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 1034564 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="LNGvN6MC"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43rN7V6Ms4z9sMx for ; Fri, 1 Feb 2019 14:36:38 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727433AbfBADgi (ORCPT ); Thu, 31 Jan 2019 22:36:38 -0500 Received: from hqemgate15.nvidia.com ([216.228.121.64]:4011 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725807AbfBADgi (ORCPT ); Thu, 31 Jan 2019 22:36:38 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 31 Jan 2019 19:36:04 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 31 Jan 2019 19:36:33 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 31 Jan 2019 19:36:33 -0800 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 1 Feb 2019 03:36:33 +0000 Received: from HQMAIL108.nvidia.com (172.18.146.13) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 1 Feb 2019 03:36:32 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Fri, 1 Feb 2019 03:36:32 +0000 Received: from josephl-linux.nvidia.com (Not Verified[10.19.108.132]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Thu, 31 Jan 2019 19:36:32 -0800 From: Joseph Lo To: Thierry Reding , Jonathan Hunter , Daniel Lezcano , "Thomas Gleixner" CC: , , Joseph Lo , , "Thierry Reding" Subject: [PATCH V5 2/7] clocksource: tegra: add Tegra210 timer support Date: Fri, 1 Feb 2019 11:36:16 +0800 Message-ID: <20190201033621.16814-3-josephl@nvidia.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190201033621.16814-1-josephl@nvidia.com> References: <20190201033621.16814-1-josephl@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1548992164; bh=MjzOx8nwbnzHeQXE0E5oqA7yx2T0g/wnTZMwKT7cyzQ=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=LNGvN6MCHoF4YJT3wxORM7B+iWWy3/1PJo08cKujg01+z9un2auEisopjgfvVtBio KkBM6SGfYKf8Qi2p1I1ROzjzdRInX2Ph5SjNCiTknRMN2EwHuJSxnYrcJic5jal+ZX vjBn7AaxAolP0UlhNzfkJPdcSj5/7zWGuXfCM4cz/4WyF8egYFUeRJCCIoVQXkucRy mzmI5bsyYYy4wBedbZuP6tXIQuDlpySDU7SMp9qMC5hl/6ax7rI1jygIDS7EKGAeo0 l4YjSYxuszV4pa+Gq5j8YE3yvAGnqow7scM2tfrLj9x4Po7cjJP6im6J9ly8r/OoGx gPljNKaeFLrCg== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Add support for the Tegra210 timer that runs at oscillator clock (TMR10-TMR13). We need these timers to work as clock event device and to replace the ARMv8 architected timer due to it can't survive across the power cycle of the CPU core or CPUPORESET signal. So it can't be a wake-up source when CPU suspends in power down state. Also convert the original driver to use timer-of API. Cc: Daniel Lezcano Cc: Thomas Gleixner Cc: linux-kernel@vger.kernel.org Signed-off-by: Joseph Lo Acked-by: Thierry Reding --- v5: * add ack tag from Thierry v4: * merge timer-tegra210.c in previous version into timer-tegra20.c v3: * use timer-of API v2: * add error clean-up code --- drivers/clocksource/Kconfig | 2 +- drivers/clocksource/timer-tegra20.c | 369 ++++++++++++++++++++-------- include/linux/cpuhotplug.h | 1 + 3 files changed, 272 insertions(+), 100 deletions(-) diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index a9e26f6a81a1..6af78534a285 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -131,7 +131,7 @@ config SUN5I_HSTIMER config TEGRA_TIMER bool "Tegra timer driver" if COMPILE_TEST select CLKSRC_MMIO - depends on ARM + select TIMER_OF help Enables support for the Tegra driver. diff --git a/drivers/clocksource/timer-tegra20.c b/drivers/clocksource/timer-tegra20.c index 4293943f4e2b..96a809341c9b 100644 --- a/drivers/clocksource/timer-tegra20.c +++ b/drivers/clocksource/timer-tegra20.c @@ -15,21 +15,24 @@ * */ -#include +#include +#include +#include +#include +#include #include -#include #include -#include -#include -#include -#include -#include #include #include -#include -#include +#include +#include +#include + +#include "timer-of.h" +#ifdef CONFIG_ARM #include +#endif #define RTC_SECONDS 0x08 #define RTC_SHADOW_SECONDS 0x0c @@ -43,70 +46,147 @@ #define TIMER2_BASE 0x8 #define TIMER3_BASE 0x50 #define TIMER4_BASE 0x58 - -#define TIMER_PTV 0x0 -#define TIMER_PCR 0x4 - +#define TIMER10_BASE 0x90 + +#define TIMER_PTV 0x0 +#define TIMER_PTV_EN BIT(31) +#define TIMER_PTV_PER BIT(30) +#define TIMER_PCR 0x4 +#define TIMER_PCR_INTR_CLR BIT(30) + +#ifdef CONFIG_ARM +#define TIMER_BASE TIMER3_BASE +#else +#define TIMER_BASE TIMER10_BASE +#endif +#define TIMER10_IRQ_IDX 10 +#define TIMER_FOR_CPU(cpu) (TIMER_BASE + (cpu) * 8) +#define IRQ_IDX_FOR_CPU(cpu) (TIMER10_IRQ_IDX + cpu) + +static u32 usec_config; static void __iomem *timer_reg_base; +#ifdef CONFIG_ARM static void __iomem *rtc_base; - static struct timespec64 persistent_ts; static u64 persistent_ms, last_persistent_ms; - static struct delay_timer tegra_delay_timer; - -#define timer_writel(value, reg) \ - writel_relaxed(value, timer_reg_base + (reg)) -#define timer_readl(reg) \ - readl_relaxed(timer_reg_base + (reg)) +#endif static int tegra_timer_set_next_event(unsigned long cycles, struct clock_event_device *evt) { - u32 reg; + void __iomem *reg_base = timer_of_base(to_timer_of(evt)); - reg = 0x80000000 | ((cycles > 1) ? (cycles-1) : 0); - timer_writel(reg, TIMER3_BASE + TIMER_PTV); + writel(TIMER_PTV_EN | + ((cycles > 1) ? (cycles - 1) : 0), /* n+1 scheme */ + reg_base + TIMER_PTV); return 0; } -static inline void timer_shutdown(struct clock_event_device *evt) +static int tegra_timer_shutdown(struct clock_event_device *evt) { - timer_writel(0, TIMER3_BASE + TIMER_PTV); + void __iomem *reg_base = timer_of_base(to_timer_of(evt)); + + writel(0, reg_base + TIMER_PTV); + + return 0; } -static int tegra_timer_shutdown(struct clock_event_device *evt) +static int tegra_timer_set_periodic(struct clock_event_device *evt) { - timer_shutdown(evt); + void __iomem *reg_base = timer_of_base(to_timer_of(evt)); + + writel(TIMER_PTV_EN | TIMER_PTV_PER | + ((timer_of_rate(to_timer_of(evt)) / HZ) - 1), + reg_base + TIMER_PTV); + return 0; } -static int tegra_timer_set_periodic(struct clock_event_device *evt) +static irqreturn_t tegra_timer_isr(int irq, void *dev_id) { - u32 reg = 0xC0000000 | ((1000000 / HZ) - 1); + struct clock_event_device *evt = (struct clock_event_device *)dev_id; + void __iomem *reg_base = timer_of_base(to_timer_of(evt)); + + writel(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR); + evt->event_handler(evt); + + return IRQ_HANDLED; +} + +#ifdef CONFIG_ARM64 +static DEFINE_PER_CPU(struct timer_of, tegra_to) = { + .flags = TIMER_OF_CLOCK | TIMER_OF_BASE, + + .clkevt = { + .name = "tegra_timer", + .rating = 460, + .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, + .set_next_event = tegra_timer_set_next_event, + .set_state_shutdown = tegra_timer_shutdown, + .set_state_periodic = tegra_timer_set_periodic, + .set_state_oneshot = tegra_timer_shutdown, + .tick_resume = tegra_timer_shutdown, + }, +}; + +static int tegra_timer_setup(unsigned int cpu) +{ + struct timer_of *to = per_cpu_ptr(&tegra_to, cpu); + + irq_force_affinity(to->clkevt.irq, cpumask_of(cpu)); + enable_irq(to->clkevt.irq); + + clockevents_config_and_register(&to->clkevt, timer_of_rate(to), + 1, /* min */ + 0x1fffffff); /* 29 bits */ - timer_shutdown(evt); - timer_writel(reg, TIMER3_BASE + TIMER_PTV); return 0; } -static struct clock_event_device tegra_clockevent = { - .name = "timer0", - .rating = 300, - .features = CLOCK_EVT_FEAT_ONESHOT | - CLOCK_EVT_FEAT_PERIODIC | - CLOCK_EVT_FEAT_DYNIRQ, - .set_next_event = tegra_timer_set_next_event, - .set_state_shutdown = tegra_timer_shutdown, - .set_state_periodic = tegra_timer_set_periodic, - .set_state_oneshot = tegra_timer_shutdown, - .tick_resume = tegra_timer_shutdown, +static int tegra_timer_stop(unsigned int cpu) +{ + struct timer_of *to = per_cpu_ptr(&tegra_to, cpu); + + to->clkevt.set_state_shutdown(&to->clkevt); + disable_irq_nosync(to->clkevt.irq); + + return 0; +} +#else /* CONFIG_ARM */ +static struct timer_of tegra_to = { + .flags = TIMER_OF_CLOCK | TIMER_OF_BASE | TIMER_OF_IRQ, + + .clkevt = { + .name = "tegra_timer", + .rating = 300, + .features = CLOCK_EVT_FEAT_ONESHOT | + CLOCK_EVT_FEAT_PERIODIC | + CLOCK_EVT_FEAT_DYNIRQ, + .set_next_event = tegra_timer_set_next_event, + .set_state_shutdown = tegra_timer_shutdown, + .set_state_periodic = tegra_timer_set_periodic, + .set_state_oneshot = tegra_timer_shutdown, + .tick_resume = tegra_timer_shutdown, + .cpumask = cpu_possible_mask, + }, + + .of_irq = { + .index = 2, + .flags = IRQF_TIMER | IRQF_TRIGGER_HIGH, + .handler = tegra_timer_isr, + }, }; static u64 notrace tegra_read_sched_clock(void) { - return timer_readl(TIMERUS_CNTR_1US); + return readl(timer_reg_base + TIMERUS_CNTR_1US); +} + +static unsigned long tegra_delay_timer_read_counter_long(void) +{ + return readl(timer_reg_base + TIMERUS_CNTR_1US); } /* @@ -143,98 +223,188 @@ static void tegra_read_persistent_clock64(struct timespec64 *ts) timespec64_add_ns(&persistent_ts, delta * NSEC_PER_MSEC); *ts = persistent_ts; } +#endif -static unsigned long tegra_delay_timer_read_counter_long(void) +static int tegra_timer_suspend(void) { - return readl(timer_reg_base + TIMERUS_CNTR_1US); +#ifdef CONFIG_ARM64 + int cpu; + + for_each_possible_cpu(cpu) { + struct timer_of *to = per_cpu_ptr(&tegra_to, cpu); + void __iomem *reg_base = timer_of_base(to); + + writel(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR); + } +#else + void __iomem *reg_base = timer_of_base(&tegra_to); + + writel(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR); +#endif + + return 0; } -static irqreturn_t tegra_timer_interrupt(int irq, void *dev_id) +static void tegra_timer_resume(void) { - struct clock_event_device *evt = (struct clock_event_device *)dev_id; - timer_writel(1<<30, TIMER3_BASE + TIMER_PCR); - evt->event_handler(evt); - return IRQ_HANDLED; + writel(usec_config, timer_reg_base + TIMERUS_USEC_CFG); } -static struct irqaction tegra_timer_irq = { - .name = "timer0", - .flags = IRQF_TIMER | IRQF_TRIGGER_HIGH, - .handler = tegra_timer_interrupt, - .dev_id = &tegra_clockevent, +static struct syscore_ops tegra_timer_syscore_ops = { + .suspend = tegra_timer_suspend, + .resume = tegra_timer_resume, }; -static int __init tegra20_init_timer(struct device_node *np) +static int tegra_timer_init(struct device_node *np, struct timer_of *to) { - struct clk *clk; - unsigned long rate; - int ret; + int ret = 0; - timer_reg_base = of_iomap(np, 0); - if (!timer_reg_base) { - pr_err("Can't map timer registers\n"); - return -ENXIO; - } + ret = timer_of_init(np, to); + if (ret < 0) + goto out; - tegra_timer_irq.irq = irq_of_parse_and_map(np, 2); - if (tegra_timer_irq.irq <= 0) { - pr_err("Failed to map timer IRQ\n"); - return -EINVAL; - } + timer_reg_base = timer_of_base(to); - clk = of_clk_get(np, 0); - if (IS_ERR(clk)) { - pr_warn("Unable to get timer clock. Assuming 12Mhz input clock.\n"); - rate = 12000000; - } else { - clk_prepare_enable(clk); - rate = clk_get_rate(clk); - } - - switch (rate) { + /* + * Configure microsecond timers to have 1MHz clock + * Config register is 0xqqww, where qq is "dividend", ww is "divisor" + * Uses n+1 scheme + */ + switch (timer_of_rate(to)) { case 12000000: - timer_writel(0x000b, TIMERUS_USEC_CFG); + usec_config = 0x000b; /* (11+1)/(0+1) */ + break; + case 12800000: + usec_config = 0x043f; /* (63+1)/(4+1) */ break; case 13000000: - timer_writel(0x000c, TIMERUS_USEC_CFG); + usec_config = 0x000c; /* (12+1)/(0+1) */ + break; + case 16800000: + usec_config = 0x0453; /* (83+1)/(4+1) */ break; case 19200000: - timer_writel(0x045f, TIMERUS_USEC_CFG); + usec_config = 0x045f; /* (95+1)/(4+1) */ break; case 26000000: - timer_writel(0x0019, TIMERUS_USEC_CFG); + usec_config = 0x0019; /* (25+1)/(0+1) */ + break; + case 38400000: + usec_config = 0x04bf; /* (191+1)/(4+1) */ + break; + case 48000000: + usec_config = 0x002f; /* (47+1)/(0+1) */ break; default: - WARN(1, "Unknown clock rate"); + ret = -EINVAL; + goto out; + } + + writel(usec_config, timer_of_base(to) + TIMERUS_USEC_CFG); + + register_syscore_ops(&tegra_timer_syscore_ops); +out: + return ret; +} + +#ifdef CONFIG_ARM64 +static int __init tegra210_timer_init(struct device_node *np) +{ + int cpu, ret = 0; + struct timer_of *to; + + to = this_cpu_ptr(&tegra_to); + ret = tegra_timer_init(np, to); + if (ret < 0) + goto out; + + for_each_possible_cpu(cpu) { + struct timer_of *cpu_to; + + cpu_to = per_cpu_ptr(&tegra_to, cpu); + cpu_to->of_base.base = timer_reg_base + TIMER_FOR_CPU(cpu); + cpu_to->of_clk.rate = timer_of_rate(to); + cpu_to->clkevt.cpumask = cpumask_of(cpu); + + cpu_to->clkevt.irq = + irq_of_parse_and_map(np, IRQ_IDX_FOR_CPU(cpu)); + if (!cpu_to->clkevt.irq) { + pr_err("%s: can't map IRQ for CPU%d\n", + __func__, cpu); + ret = -EINVAL; + goto out; + } + + irq_set_status_flags(cpu_to->clkevt.irq, IRQ_NOAUTOEN); + ret = request_irq(cpu_to->clkevt.irq, tegra_timer_isr, + IRQF_TIMER | IRQF_NOBALANCING, + cpu_to->clkevt.name, &cpu_to->clkevt); + if (ret) { + pr_err("%s: cannot setup irq %d for CPU%d\n", + __func__, cpu_to->clkevt.irq, cpu); + ret = -EINVAL; + goto out_irq; + } + } + + cpuhp_setup_state(CPUHP_AP_TEGRA_TIMER_STARTING, + "AP_TEGRA_TIMER_STARTING", tegra_timer_setup, + tegra_timer_stop); + + return ret; + +out_irq: + for_each_possible_cpu(cpu) { + struct timer_of *cpu_to; + + cpu_to = per_cpu_ptr(&tegra_to, cpu); + if (cpu_to->clkevt.irq) { + free_irq(cpu_to->clkevt.irq, &cpu_to->clkevt); + irq_dispose_mapping(cpu_to->clkevt.irq); + } } +out: + timer_of_cleanup(to); + return ret; +} +TIMER_OF_DECLARE(tegra210_timer, "nvidia,tegra210-timer", tegra210_timer_init); +#else /* CONFIG_ARM */ +static int __init tegra20_init_timer(struct device_node *np) +{ + int ret = 0; + + ret = tegra_timer_init(np, &tegra_to); + if (ret < 0) + goto out; - sched_clock_register(tegra_read_sched_clock, 32, 1000000); + tegra_to.of_base.base = timer_reg_base + TIMER_FOR_CPU(0); + tegra_to.of_clk.rate = 1000000; /* microsecond timer */ + sched_clock_register(tegra_read_sched_clock, 32, + timer_of_rate(&tegra_to)); ret = clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US, - "timer_us", 1000000, 300, 32, - clocksource_mmio_readl_up); + "timer_us", timer_of_rate(&tegra_to), + 300, 32, clocksource_mmio_readl_up); if (ret) { pr_err("Failed to register clocksource\n"); - return ret; + goto out; } tegra_delay_timer.read_current_timer = tegra_delay_timer_read_counter_long; - tegra_delay_timer.freq = 1000000; + tegra_delay_timer.freq = timer_of_rate(&tegra_to); register_current_timer_delay(&tegra_delay_timer); - ret = setup_irq(tegra_timer_irq.irq, &tegra_timer_irq); - if (ret) { - pr_err("Failed to register timer IRQ: %d\n", ret); - return ret; - } + clockevents_config_and_register(&tegra_to.clkevt, + timer_of_rate(&tegra_to), + 0x1, + 0x1fffffff); - tegra_clockevent.cpumask = cpu_possible_mask; - tegra_clockevent.irq = tegra_timer_irq.irq; - clockevents_config_and_register(&tegra_clockevent, 1000000, - 0x1, 0x1fffffff); + return ret; +out: + timer_of_cleanup(&tegra_to); - return 0; + return ret; } TIMER_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra20_init_timer); @@ -261,3 +431,4 @@ static int __init tegra20_init_rtc(struct device_node *np) return register_persistent_clock(tegra_read_persistent_clock64); } TIMER_OF_DECLARE(tegra20_rtc, "nvidia,tegra20-rtc", tegra20_init_rtc); +#endif diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h index fd586d0301e7..e78281d07b70 100644 --- a/include/linux/cpuhotplug.h +++ b/include/linux/cpuhotplug.h @@ -121,6 +121,7 @@ enum cpuhp_state { CPUHP_AP_EXYNOS4_MCT_TIMER_STARTING, CPUHP_AP_ARM_TWD_STARTING, CPUHP_AP_QCOM_TIMER_STARTING, + CPUHP_AP_TEGRA_TIMER_STARTING, CPUHP_AP_ARMADA_TIMER_STARTING, CPUHP_AP_MARCO_TIMER_STARTING, CPUHP_AP_MIPS_GIC_TIMER_STARTING, From patchwork Fri Feb 1 03:36:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 1034562 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="f35sUKHD"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43rN7T4xLJz9sMp for ; Fri, 1 Feb 2019 14:36:37 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727368AbfBADgg (ORCPT ); Thu, 31 Jan 2019 22:36:36 -0500 Received: from hqemgate16.nvidia.com ([216.228.121.65]:19760 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727283AbfBADgg (ORCPT ); Thu, 31 Jan 2019 22:36:36 -0500 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 31 Jan 2019 19:35:54 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Thu, 31 Jan 2019 19:36:35 -0800 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Thu, 31 Jan 2019 19:36:35 -0800 Received: from HQMAIL112.nvidia.com (172.18.146.18) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 1 Feb 2019 03:36:35 +0000 Received: from HQMAIL108.nvidia.com (172.18.146.13) by HQMAIL112.nvidia.com (172.18.146.18) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 1 Feb 2019 03:36:35 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Fri, 1 Feb 2019 03:36:35 +0000 Received: from josephl-linux.nvidia.com (Not Verified[10.19.108.132]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Thu, 31 Jan 2019 19:36:35 -0800 From: Joseph Lo To: Thierry Reding , Jonathan Hunter , Daniel Lezcano , "Thomas Gleixner" CC: , , Joseph Lo , Thierry Reding Subject: [PATCH V5 3/7] soc/tegra: default select TEGRA_TIMER for Tegra210 Date: Fri, 1 Feb 2019 11:36:17 +0800 Message-ID: <20190201033621.16814-4-josephl@nvidia.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190201033621.16814-1-josephl@nvidia.com> References: <20190201033621.16814-1-josephl@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1548992154; bh=rfKr9EUL2CgTAShMTwUd+t7fkfZnzmuoxS8xXiknlIQ=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=f35sUKHDxp42oyYQ3ltfin3TMQO8FgXbmvoX2cy+7W8QYh3lk0TjZJHByVfhytejN SHfHemecIPEb8bhbgdo+HgMbM2gMLEBHmX2xLkYjTOKsTYtW4k+9QLxBmuFYbuFdWY G86zRfB5s39HJ+HetbGpdnHI4wVKQJOdf3VD24SPERMmY9HnDFKxgbNL5O9WAIVUdf 0RXycJrac8eMuRlgFIVhjdnn0Oh+Cpye192tcqYAJL52EJUIoSpj8LDWeRkjj1v05q +mLUeJYAXSUBe1mDQCwah5s2Htw1RIXDMKEsWLiS3GdetQbvs29ZaVzMQhCRLA4uIA RpQtwq4j2DTdQ== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org The tegra timer is necessary for Tegra210 to support CPU idle power-down state. So select it by default. Signed-off-by: Joseph Lo Acked-by: Thierry Reding --- v5: * add ack tag from Thierry v4: * new added in this version --- drivers/soc/tegra/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/tegra/Kconfig b/drivers/soc/tegra/Kconfig index fe4481676da6..a0b03443d8c1 100644 --- a/drivers/soc/tegra/Kconfig +++ b/drivers/soc/tegra/Kconfig @@ -76,6 +76,7 @@ config ARCH_TEGRA_210_SOC select PINCTRL_TEGRA210 select SOC_TEGRA_FLOWCTRL select SOC_TEGRA_PMC + select TEGRA_TIMER help Enable support for the NVIDIA Tegra210 SoC. Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 From patchwork Fri Feb 1 03:36:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 1034565 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="jPk9WJvF"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43rN7Y1LWbz9s9G for ; Fri, 1 Feb 2019 14:36:41 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725807AbfBADgj (ORCPT ); Thu, 31 Jan 2019 22:36:39 -0500 Received: from hqemgate15.nvidia.com ([216.228.121.64]:4024 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727283AbfBADgi (ORCPT ); Thu, 31 Jan 2019 22:36:38 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 31 Jan 2019 19:36:09 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 31 Jan 2019 19:36:38 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 31 Jan 2019 19:36:38 -0800 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 1 Feb 2019 03:36:37 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Fri, 1 Feb 2019 03:36:37 +0000 Received: from josephl-linux.nvidia.com (Not Verified[10.19.108.132]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Thu, 31 Jan 2019 19:36:37 -0800 From: Joseph Lo To: Thierry Reding , Jonathan Hunter , Daniel Lezcano , Thomas Gleixner CC: , , Joseph Lo Subject: [PATCH V5 4/7] arm64: dts: tegra210: fix timer node Date: Fri, 1 Feb 2019 11:36:18 +0800 Message-ID: <20190201033621.16814-5-josephl@nvidia.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190201033621.16814-1-josephl@nvidia.com> References: <20190201033621.16814-1-josephl@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1548992169; bh=XM9X8l3VLpXW3kN1JPu9vpI4LiWKf8z8ffKj/rnZ6vo=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=jPk9WJvFdUgTzGWBTnCCglSbmxe/CzJpAFxa9xhE29r8QLn65L5+f0nK8IwIf+stj IjNXzE3KVs9RO7cVhzlFDieATa3RyHu8rYCWmSa2ZKOzJH85uNtZ3/m3WMnS7qohOx ldpCXjV/EXV1+ejYxUerdbwUUnyvk+MRCQO6petMeINBXR28XqA1lgLTlypuIDH6Yc BmVg/rEm8no6CFbpwEEfSb03w+AM4fBVMFkuWsBHMhpFxuybpJGblg9v113ihFablL 9sAXl1qswONxp39Pr09AfrNsU6bNtm2mZn29J3RU+OoMjT0h8J+X4WItwUFkvjbwhP gGVatmWLnpeMw== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Fix timer node to make it work with Tegra210 timer driver. Signed-off-by: Joseph Lo --- v5: * no change v4: * no change v3: * no change v2: * list all the IRQs per each timer channels 0 through 13 * remove compatible string of "nvidia,tegra30-timer" --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index b5858b5ea052..2b387364afc3 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -384,14 +384,22 @@ }; timer@60005000 { - compatible = "nvidia,tegra210-timer", "nvidia,tegra20-timer"; + compatible = "nvidia,tegra210-timer"; reg = <0x0 0x60005000 0x0 0x400>; - interrupts = , + interrupts = , + , , , , , - ; + , + , + , + , + , + , + , + ; clocks = <&tegra_car TEGRA210_CLK_TIMER>; clock-names = "timer"; }; From patchwork Fri Feb 1 03:36:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 1034566 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="PrK9YF2J"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43rN7b3fXfz9sMp for ; Fri, 1 Feb 2019 14:36:43 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727283AbfBADgm (ORCPT ); Thu, 31 Jan 2019 22:36:42 -0500 Received: from hqemgate14.nvidia.com ([216.228.121.143]:10186 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726270AbfBADgl (ORCPT ); Thu, 31 Jan 2019 22:36:41 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 31 Jan 2019 19:36:42 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 31 Jan 2019 19:36:40 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 31 Jan 2019 19:36:40 -0800 Received: from HQMAIL102.nvidia.com (172.18.146.10) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 1 Feb 2019 03:36:40 +0000 Received: from HQMAIL104.nvidia.com (172.18.146.11) by HQMAIL102.nvidia.com (172.18.146.10) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 1 Feb 2019 03:36:40 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Fri, 1 Feb 2019 03:36:40 +0000 Received: from josephl-linux.nvidia.com (Not Verified[10.19.108.132]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Thu, 31 Jan 2019 19:36:40 -0800 From: Joseph Lo To: Thierry Reding , Jonathan Hunter , Daniel Lezcano , "Thomas Gleixner" CC: , , Joseph Lo Subject: [PATCH V5 5/7] arm64: dts: tegra210: add CPU idle states properties Date: Fri, 1 Feb 2019 11:36:19 +0800 Message-ID: <20190201033621.16814-6-josephl@nvidia.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190201033621.16814-1-josephl@nvidia.com> References: <20190201033621.16814-1-josephl@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1548992202; bh=EAHR5dYK49fVOvTv6R3OnOvXVLJhHdpr9Z7P1amBxrc=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=PrK9YF2Jy/oMBqgVQc2h4hbaflpSG/11PdufdL5t5/rwcDn2yBmUVHj9X7QfKa25m nWEMIbUtk1slkqe3UQWHl8Jj4pdo5ux7JsEHXWP4WRMXL9vj68/84jIPNylUly2oSK bbU34oMldZU/4I/dJtBHIrquCLJ76B05hoXY/j97/08Wv+dvACRO5D+sQfEENX+s9+ vLt7zM6nsqcvdb6eEUd/xSOdBVGHPlTV2jtz4jFQl+xNsoF6hiRXsffzpfzFEpmVpB GviOTiJyV3n69CEjd5g+VedHqSuz3z/rz8WNhqKJZBfcXxidjbFC1VpJzhHSWhZN4z 1/KfxgfmedfjA== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Add idle states properties for generic ARM CPU idle driver. This includes a C7 state which is the power down state of CPU cores. Signed-off-by: Joseph Lo --- v5: * no change v4: * no change v3: * no change v2: * add entry-latency-us and exit-latency-us properties Note: This dt patch depends on the DT changes in below series. http://patchwork.ozlabs.org/project/linux-tegra/list/?series=84380 --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 2b387364afc3..75534692604c 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -1318,24 +1318,43 @@ <&dfll>; clock-names = "cpu_g", "pll_x", "pll_p", "dfll"; clock-latency = <300000>; + cpu-idle-states = <&C7>; }; cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <1>; + cpu-idle-states = <&C7>; }; cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <2>; + cpu-idle-states = <&C7>; }; cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <3>; + cpu-idle-states = <&C7>; + }; + + idle-states { + entry-method = "psci"; + + C7: c7 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x40000007>; + entry-latency-us = <250>; + exit-latency-us = <100>; + min-residency-us = <1000>; + wakeup-latency-us = <130>; + idle-state-name = "c7-cpu-powergated"; + status = "disabled"; + }; }; }; From patchwork Fri Feb 1 03:36:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 1034567 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="OY1hTBLW"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43rN7c4Hsvz9sMx for ; Fri, 1 Feb 2019 14:36:44 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727401AbfBADgn (ORCPT ); Thu, 31 Jan 2019 22:36:43 -0500 Received: from hqemgate14.nvidia.com ([216.228.121.143]:10191 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726270AbfBADgm (ORCPT ); Thu, 31 Jan 2019 22:36:42 -0500 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 31 Jan 2019 19:36:44 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Thu, 31 Jan 2019 19:36:42 -0800 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Thu, 31 Jan 2019 19:36:42 -0800 Received: from HQMAIL102.nvidia.com (172.18.146.10) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 1 Feb 2019 03:36:42 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL102.nvidia.com (172.18.146.10) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Fri, 1 Feb 2019 03:36:42 +0000 Received: from josephl-linux.nvidia.com (Not Verified[10.19.108.132]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Thu, 31 Jan 2019 19:36:42 -0800 From: Joseph Lo To: Thierry Reding , Jonathan Hunter , Daniel Lezcano , Thomas Gleixner CC: , , Joseph Lo Subject: [PATCH V5 6/7] arm64: dts: tegra210-p2180: Enable CPU idle support Date: Fri, 1 Feb 2019 11:36:20 +0800 Message-ID: <20190201033621.16814-7-josephl@nvidia.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190201033621.16814-1-josephl@nvidia.com> References: <20190201033621.16814-1-josephl@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1548992204; bh=4sXVsOQjzr45v1Y4tFkY3FF7tj32/taQgELqc6b7luc=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=OY1hTBLWVl8fkBrkieXJlciYD+/j2M/OQ30GYOuNn9eXzHr4zxZ6D2SAE/DW+hRNO IGTUuhGBuj+A+Gw+NFqizNll1cUtj7bIfcyr/FrKlQLfpKLzndGx17y7auyS71qXX4 o1dM4C7lBS5Mf2s6+jn84+QCNlkhtOTpdMYH7GNL2flQoSCOGqDZ7Gc/7uFb34yvTF kiBrgc6qb5LlqfFLOiPupuB42sGvl7Wimcv1LKD5h0syFPserNkHhEZ1EbfKTBrQKH PPrLWBUgVvjrTfdJLChVseb03R8Sj/9l40NEa9cOS3KaI7l3/Fy6n53nFgP8PfxPX1 yXGJpSys9svsQ== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Enable CPU idle support for Jetson TX1 platform. Signed-off-by: Joseph Lo --- v5: * no change v4: * no change v3: * no change v2: * no change --- arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi index 053458a5db55..d1a492c63e96 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi @@ -305,6 +305,12 @@ cpu@3 { enable-method = "psci"; }; + + idle-states { + c7 { + status = "okay"; + }; + }; }; psci { From patchwork Fri Feb 1 03:36:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 1034568 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="o7D5o6/Z"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43rN7f0nR7z9s9G for ; Fri, 1 Feb 2019 14:36:46 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726270AbfBADgp (ORCPT ); Thu, 31 Jan 2019 22:36:45 -0500 Received: from hqemgate14.nvidia.com ([216.228.121.143]:10198 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725831AbfBADgp (ORCPT ); Thu, 31 Jan 2019 22:36:45 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 31 Jan 2019 19:36:46 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 31 Jan 2019 19:36:44 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 31 Jan 2019 19:36:44 -0800 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 1 Feb 2019 03:36:44 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Fri, 1 Feb 2019 03:36:44 +0000 Received: from josephl-linux.nvidia.com (Not Verified[10.19.108.132]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Thu, 31 Jan 2019 19:36:44 -0800 From: Joseph Lo To: Thierry Reding , Jonathan Hunter , Daniel Lezcano , Thomas Gleixner CC: , , Joseph Lo Subject: [PATCH V5 7/7] arm64: dts: tegra210-smaug: Enable CPU idle support Date: Fri, 1 Feb 2019 11:36:21 +0800 Message-ID: <20190201033621.16814-8-josephl@nvidia.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190201033621.16814-1-josephl@nvidia.com> References: <20190201033621.16814-1-josephl@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1548992206; bh=lqmtsCupYlrDPJ7aTV3NMXoUlvo9AdJMh0ODevoR1Zw=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=o7D5o6/ZIi3QMgiBze3kjVliuCXQQpt+pG7012XWfy+kOjlH00tTLJDkhAHm2TORf mMKQGLANhkZ4VLxeiQJfpTQUaN4JQp7p7GaGvWpGttzGhmD+/6pP2oLoFdnQf8teWz 7RGbyyp+L9eBy7InuYtM3w27k9M8ft1xDD2xrlNuCNlTHlUfOlciwM0exIxA7/8qHS elDlf0nqO5QdE+5yk67iGemCmNZmVjThNxbP+HeIIf2ZHY9A3y4Vb9L3/P3YqtRva7 Ssx2tBbnWux4D457V0OOw5ajfL2pBy8NAjMwtxW0l8KIUfxxkJo4azQ6Ua2Ho+fzcz xDb03377agx7g== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Enable CPU idle support for Smaug platform. Signed-off-by: Joseph Lo --- v5: * no change v4: * no change v3: * no change v2: * no change --- arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts index 5a67890cfb7a..da0eb4530acf 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts @@ -1751,6 +1751,13 @@ cpu@3 { enable-method = "psci"; }; + + idle-states { + c7 { + arm,psci-suspend-param = <0x00010007>; + status = "okay"; + }; + }; }; gpio-keys {