From patchwork Mon Jan 14 13:24:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 1024502 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="XguTTcbM"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43dZ355vD0z9sD4 for ; Tue, 15 Jan 2019 00:25:21 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726534AbfANNZP (ORCPT ); Mon, 14 Jan 2019 08:25:15 -0500 Received: from lelv0142.ext.ti.com ([198.47.23.249]:40766 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726614AbfANNZO (ORCPT ); Mon, 14 Jan 2019 08:25:14 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x0EDP1r4041058; Mon, 14 Jan 2019 07:25:01 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1547472301; bh=/1J959qeP7cM4MKMLmkewqVjCysFTBea7AaLB6rN+lY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=XguTTcbMlPaXHdo+Sr5XTVFMC5/hje6r8r5Xv9a5pOyUssOCHqFJA4XbVWPYtNC5t rcASvHisswUhUWIjU2pcf8+55STLnMyZwaNYpXRDaKrvCRJ2ZgRXjnfgZ9oYwC/9y2 fef1j4oZ1sjnBuQEc4oWYdgwZpKhf1ProVMwNyno= Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x0EDP18W055900 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 14 Jan 2019 07:25:01 -0600 Received: from DFLE100.ent.ti.com (10.64.6.21) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Mon, 14 Jan 2019 07:25:00 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Mon, 14 Jan 2019 07:25:00 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x0EDOoWN028516; Mon, 14 Jan 2019 07:24:56 -0600 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Rob Herring , Lorenzo Pieralisi CC: Kishon Vijay Abraham I , Jingoo Han , Bjorn Helgaas , Mark Rutland , Arnd Bergmann , Greg Kroah-Hartman , Murali Karicheri , Jesper Nilsson , , , , , , Subject: [PATCH 01/24] PCI: keystone: Add start_link/stop_link dw_pcie_ops Date: Mon, 14 Jan 2019 18:54:01 +0530 Message-ID: <20190114132424.6445-2-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190114132424.6445-1-kishon@ti.com> References: <20190114132424.6445-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add start_link/stop_link dw_pcie_ops and invoke ks_pcie_start_link directly from host_init. start_link/stop_link ops is required for adding EP mode support. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 44 +++++++++++------------ 1 file changed, 22 insertions(+), 22 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 420d30ce11f4..24c38ae570b5 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -419,18 +419,33 @@ static int ks_pcie_link_up(struct dw_pcie *pci) return (val == PORT_LOGIC_LTSSM_STATE_L0); } -static void ks_pcie_initiate_link_train(struct keystone_pcie *ks_pcie) +static void ks_pcie_stop_link(struct dw_pcie *pci) { + struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); u32 val; /* Disable Link training */ val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); val &= ~LTSSM_EN_VAL; ks_pcie_app_writel(ks_pcie, CMD_STATUS, LTSSM_EN_VAL | val); +} + +static int ks_pcie_start_link(struct dw_pcie *pci) +{ + struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); + struct device *dev = pci->dev; + u32 val; + + if (dw_pcie_link_up(pci)) { + dev_dbg(dev, "link is already up\n"); + return 0; + } /* Initiate Link Training */ val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); ks_pcie_app_writel(ks_pcie, CMD_STATUS, LTSSM_EN_VAL | val); + + return 0; } /** @@ -515,26 +530,6 @@ static void ks_pcie_quirk(struct pci_dev *dev) } DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, ks_pcie_quirk); -static int ks_pcie_establish_link(struct keystone_pcie *ks_pcie) -{ - struct dw_pcie *pci = ks_pcie->pci; - struct device *dev = pci->dev; - - if (dw_pcie_link_up(pci)) { - dev_info(dev, "Link already up\n"); - return 0; - } - - ks_pcie_initiate_link_train(ks_pcie); - - /* check if the link is up or not */ - if (!dw_pcie_wait_for_link(pci)) - return 0; - - dev_err(dev, "phy link never came up\n"); - return -ETIMEDOUT; -} - static void ks_pcie_msi_irq_handler(struct irq_desc *desc) { unsigned int irq = desc->irq_data.hwirq; @@ -796,7 +791,7 @@ static int __init ks_pcie_host_init(struct pcie_port *pp) dw_pcie_setup_rc(pp); - ks_pcie_establish_link(ks_pcie); + ks_pcie_stop_link(pci); ks_pcie_setup_rc_app_regs(ks_pcie); ks_pcie_setup_interrupts(ks_pcie); writew(PCI_IO_RANGE_TYPE_32 | (PCI_IO_RANGE_TYPE_32 << 8), @@ -813,6 +808,9 @@ static int __init ks_pcie_host_init(struct pcie_port *pp) hook_fault_code(17, ks_pcie_fault, SIGBUS, 0, "Asynchronous external abort"); + ks_pcie_start_link(pci); + dw_pcie_wait_for_link(pci); + return 0; } @@ -875,6 +873,8 @@ static const struct of_device_id ks_pcie_of_match[] = { }; static const struct dw_pcie_ops ks_pcie_dw_pcie_ops = { + .start_link = ks_pcie_start_link, + .stop_link = ks_pcie_stop_link, .link_up = ks_pcie_link_up, }; From patchwork Mon Jan 14 13:24:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 1024506 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="ZoJMJ1UD"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43dZ3P6wbhz9s9G for ; Tue, 15 Jan 2019 00:25:37 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726674AbfANNZY (ORCPT ); Mon, 14 Jan 2019 08:25:24 -0500 Received: from lelv0143.ext.ti.com ([198.47.23.248]:40920 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726525AbfANNZY (ORCPT ); Mon, 14 Jan 2019 08:25:24 -0500 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x0EDP6Tn019195; Mon, 14 Jan 2019 07:25:06 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1547472306; bh=NtKe2jericu7SZi4WCZJdZomxBVNvIwuxybIlJmjYW0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=ZoJMJ1UDlKF49D1BkkOd3yN5yxSOPLnDFdTCZvitzuZ3lbqbVPhY8qraal+Ibh0FB YKnssgPPzJ7jk1v07k28HhwQ+x20X5X/kGi57IjFmM2HFOGGYGyZmL/OY/XUAYHTe+ KRtGGo488jF/peCKVIAtRre590cFDMVj0GsQLAyw= Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x0EDP5j9088411 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 14 Jan 2019 07:25:06 -0600 Received: from DFLE109.ent.ti.com (10.64.6.30) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Mon, 14 Jan 2019 07:25:05 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Mon, 14 Jan 2019 07:25:05 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x0EDOoWO028516; Mon, 14 Jan 2019 07:25:01 -0600 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Rob Herring , Lorenzo Pieralisi CC: Kishon Vijay Abraham I , Jingoo Han , Bjorn Helgaas , Mark Rutland , Arnd Bergmann , Greg Kroah-Hartman , Murali Karicheri , Jesper Nilsson , , , , , , Subject: [PATCH 02/24] PCI: keystone: Cleanup error_irq configuration Date: Mon, 14 Jan 2019 18:54:02 +0530 Message-ID: <20190114132424.6445-3-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190114132424.6445-1-kishon@ti.com> References: <20190114132424.6445-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org pci-keystone driver uses irq_of_parse_and_map to get irq number of error_irq. Use platform_get_irq instead and move platform_get_irq() and request_irq() of error_irq from ks_pcie_add_pcie_port to ks_pcie_probe since error_irq is common to both RC mode and EP mode. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 43 +++++++++-------------- 1 file changed, 17 insertions(+), 26 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 24c38ae570b5..f63268aee2de 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -97,8 +97,6 @@ struct keystone_pcie { struct irq_domain *legacy_irq_domain; struct device_node *np; - int error_irq; - /* Application register space */ void __iomem *va_app_base; /* DT 1st resource */ struct resource app; @@ -726,12 +724,6 @@ static int ks_pcie_config_legacy_irq(struct keystone_pcie *ks_pcie) return ret; } -static void ks_pcie_setup_interrupts(struct keystone_pcie *ks_pcie) -{ - if (ks_pcie->error_irq > 0) - ks_pcie_enable_error_irq(ks_pcie); -} - /* * When a PCI device does not exist during config cycles, keystone host gets a * bus error instead of returning 0xffffffff. This handler always returns 0 @@ -793,7 +785,6 @@ static int __init ks_pcie_host_init(struct pcie_port *pp) ks_pcie_stop_link(pci); ks_pcie_setup_rc_app_regs(ks_pcie); - ks_pcie_setup_interrupts(ks_pcie); writew(PCI_IO_RANGE_TYPE_32 | (PCI_IO_RANGE_TYPE_32 << 8), pci->dbi_base + PCI_IO_BASE); @@ -837,23 +828,6 @@ static int __init ks_pcie_add_pcie_port(struct keystone_pcie *ks_pcie, struct device *dev = &pdev->dev; int ret; - /* - * Index 0 is the platform interrupt for error interrupt - * from RC. This is optional. - */ - ks_pcie->error_irq = irq_of_parse_and_map(ks_pcie->np, 0); - if (ks_pcie->error_irq <= 0) - dev_info(dev, "no error IRQ defined\n"); - else { - ret = request_irq(ks_pcie->error_irq, ks_pcie_err_irq_handler, - IRQF_SHARED, "pcie-error-irq", ks_pcie); - if (ret < 0) { - dev_err(dev, "failed to request error IRQ %d\n", - ks_pcie->error_irq); - return ret; - } - } - pp->ops = &ks_pcie_host_ops; ret = ks_pcie_dw_host_init(ks_pcie); if (ret) { @@ -929,6 +903,7 @@ static int __init ks_pcie_probe(struct platform_device *pdev) u32 num_lanes; char name[10]; int ret; + int irq; int i; ks_pcie = devm_kzalloc(dev, sizeof(*ks_pcie), GFP_KERNEL); @@ -948,6 +923,20 @@ static int __init ks_pcie_probe(struct platform_device *pdev) return ret; } + irq = platform_get_irq(pdev, 0); + if (irq < 0) { + dev_err(dev, "missing IRQ resource: %d\n", irq); + return irq; + } + + ret = request_irq(irq, ks_pcie_err_irq_handler, IRQF_SHARED, + "ks-pcie-error-irq", ks_pcie); + if (ret < 0) { + dev_err(dev, "failed to request error IRQ %d\n", + irq); + return ret; + } + ret = of_property_read_u32(np, "num-lanes", &num_lanes); if (ret) num_lanes = 1; @@ -1003,6 +992,8 @@ static int __init ks_pcie_probe(struct platform_device *pdev) if (ret < 0) goto err_get_sync; + ks_pcie_enable_error_irq(ks_pcie); + return 0; err_get_sync: From patchwork Mon Jan 14 13:24:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 1024504 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="nYzVyI5K"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43dZ3M28nqz9sDB for ; Tue, 15 Jan 2019 00:25:35 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726697AbfANNZ2 (ORCPT ); Mon, 14 Jan 2019 08:25:28 -0500 Received: from lelv0143.ext.ti.com ([198.47.23.248]:40930 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726525AbfANNZ1 (ORCPT ); Mon, 14 Jan 2019 08:25:27 -0500 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x0EDPAxx019305; Mon, 14 Jan 2019 07:25:10 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1547472310; bh=TXLdx2SAosMFqyOjlSQie8ZcUaPTkakA6by1/PgLXHo=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=nYzVyI5KUJ+mMVZEpLIUqw5HX93v3kPPKjIRord7C45K+29Cc7nLbKzK0WvK716Hb 4OvbRZCAzQe3eOtpwps2Vgj5Uv4zo5DQuPP8Dce298Yltlu7oo6yIu39fw0saQQme/ odVtamfyu8iqSd4HWCE5Qf2DKoVUK+lOZy2tomUs= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x0EDPAOb011734 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 14 Jan 2019 07:25:10 -0600 Received: from DFLE109.ent.ti.com (10.64.6.30) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Mon, 14 Jan 2019 07:25:10 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Mon, 14 Jan 2019 07:25:10 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x0EDOoWP028516; Mon, 14 Jan 2019 07:25:06 -0600 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Rob Herring , Lorenzo Pieralisi CC: Kishon Vijay Abraham I , Jingoo Han , Bjorn Helgaas , Mark Rutland , Arnd Bergmann , Greg Kroah-Hartman , Murali Karicheri , Jesper Nilsson , , , , , , Subject: [PATCH 03/24] dt-bindings: PCI: keystone: Add "reg-names" binding information Date: Mon, 14 Jan 2019 18:54:03 +0530 Message-ID: <20190114132424.6445-4-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190114132424.6445-1-kishon@ti.com> References: <20190114132424.6445-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add "reg-names" binding information in order for device tree node to be populated with the correct register strings. This will break old dt compatibility. However Keystone PCI has never worked in upstream kernel due to lack of SERDES support. Before SERDES support is added, cleanup the Keystone PCI dt-bindngs. This new binding will also be used by PCI in AM654 platform. Signed-off-by: Kishon Vijay Abraham I Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/pci/pci-keystone.txt | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/pci-keystone.txt b/Documentation/devicetree/bindings/pci/pci-keystone.txt index 2030ee0dc4f9..3a551687cfa2 100644 --- a/Documentation/devicetree/bindings/pci/pci-keystone.txt +++ b/Documentation/devicetree/bindings/pci/pci-keystone.txt @@ -12,8 +12,10 @@ described here as well as properties that are not applicable. Required Properties:- compatibility: "ti,keystone-pcie" -reg: index 1 is the base address and length of DW application registers. - index 2 is the base address and length of PCI device ID register. +reg: Three register ranges as listed in the reg-names property +reg-names: "dbics" for the DesignWare PCIe registers, "app" for the + TI specific application registers, "config" for the + configuration space address pcie_msi_intc : Interrupt controller device node for MSI IRQ chip interrupt-cells: should be set to 1 From patchwork Mon Jan 14 13:24:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 1024507 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="mF9gl4t4"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43dZ3Y4yWYz9sBZ for ; Tue, 15 Jan 2019 00:25:45 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726718AbfANNZg (ORCPT ); Mon, 14 Jan 2019 08:25:36 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:37158 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726563AbfANNZg (ORCPT ); Mon, 14 Jan 2019 08:25:36 -0500 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x0EDPFgY098049; Mon, 14 Jan 2019 07:25:15 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1547472315; bh=ZOxErDAenCR4nywVOJbopTCQfMydSgJQFf0ad6hjYzM=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=mF9gl4t4rXakuReor+2NmekbjsQHsDqFnPgnchwmK4VZN6lkWMgbMt2i9Hrbs9sVA 5OjgHTqe7DqYPpyhsRIKH7tVjh0J2pQSEKQzrbFFNzrIbF6HrP7Ynw+qoh7LXh1csZ vwFIz4CZLWkI424EW72IKOGyj+wr0H50ETrC7zlE= Received: from DFLE113.ent.ti.com (dfle113.ent.ti.com [10.64.6.34]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x0EDPFhj011765 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 14 Jan 2019 07:25:15 -0600 Received: from DFLE101.ent.ti.com (10.64.6.22) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Mon, 14 Jan 2019 07:25:15 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Mon, 14 Jan 2019 07:25:15 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x0EDOoWQ028516; Mon, 14 Jan 2019 07:25:11 -0600 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Rob Herring , Lorenzo Pieralisi CC: Kishon Vijay Abraham I , Jingoo Han , Bjorn Helgaas , Mark Rutland , Arnd Bergmann , Greg Kroah-Hartman , Murali Karicheri , Jesper Nilsson , , , , , , Subject: [PATCH 04/24] PCI: keystone: Perform host initialization in a single function Date: Mon, 14 Jan 2019 18:54:04 +0530 Message-ID: <20190114132424.6445-5-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190114132424.6445-1-kishon@ti.com> References: <20190114132424.6445-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org No functional change. Instead of having two functions ks_pcie_add_pcie_port and ks_pcie_dw_host_init for initializing host, have a single function to perform all the host initialization. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 63 +++++++++-------------- 1 file changed, 23 insertions(+), 40 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index f63268aee2de..3f917ffa9105 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -446,45 +446,6 @@ static int ks_pcie_start_link(struct dw_pcie *pci) return 0; } -/** - * ks_pcie_dw_host_init() - initialize host for v3_65 dw hardware - * - * Ioremap the register resources, initialize legacy irq domain - * and call dw_pcie_v3_65_host_init() API to initialize the Keystone - * PCI host controller. - */ -static int __init ks_pcie_dw_host_init(struct keystone_pcie *ks_pcie) -{ - struct dw_pcie *pci = ks_pcie->pci; - struct pcie_port *pp = &pci->pp; - struct device *dev = pci->dev; - struct platform_device *pdev = to_platform_device(dev); - struct resource *res; - - /* Index 0 is the config reg. space address */ - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - pci->dbi_base = devm_pci_remap_cfg_resource(dev, res); - if (IS_ERR(pci->dbi_base)) - return PTR_ERR(pci->dbi_base); - - /* - * We set these same and is used in pcie rd/wr_other_conf - * functions - */ - pp->va_cfg0_base = pci->dbi_base + SPACE0_REMOTE_CFG_OFFSET; - pp->va_cfg1_base = pp->va_cfg0_base; - - /* Index 1 is the application reg. space address */ - res = platform_get_resource(pdev, IORESOURCE_MEM, 1); - ks_pcie->va_app_base = devm_ioremap_resource(dev, res); - if (IS_ERR(ks_pcie->va_app_base)) - return PTR_ERR(ks_pcie->va_app_base); - - ks_pcie->app = *res; - - return dw_pcie_host_init(pp); -} - static void ks_pcie_quirk(struct pci_dev *dev) { struct pci_bus *bus = dev->bus; @@ -826,10 +787,32 @@ static int __init ks_pcie_add_pcie_port(struct keystone_pcie *ks_pcie, struct dw_pcie *pci = ks_pcie->pci; struct pcie_port *pp = &pci->pp; struct device *dev = &pdev->dev; + struct resource *res; int ret; + /* Index 0 is the config reg. space address */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + pci->dbi_base = devm_pci_remap_cfg_resource(dev, res); + if (IS_ERR(pci->dbi_base)) + return PTR_ERR(pci->dbi_base); + + /* + * We set these same and is used in pcie rd/wr_other_conf + * functions + */ + pp->va_cfg0_base = pci->dbi_base + SPACE0_REMOTE_CFG_OFFSET; + pp->va_cfg1_base = pp->va_cfg0_base; + + /* Index 1 is the application reg. space address */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + ks_pcie->va_app_base = devm_ioremap_resource(dev, res); + if (IS_ERR(ks_pcie->va_app_base)) + return PTR_ERR(ks_pcie->va_app_base); + + ks_pcie->app = *res; + pp->ops = &ks_pcie_host_ops; - ret = ks_pcie_dw_host_init(ks_pcie); + ret = dw_pcie_host_init(pp); if (ret) { dev_err(dev, "failed to initialize host\n"); return ret; From patchwork Mon Jan 14 13:24:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 1024508 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="SKjVgiWT"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43dZ414FJHz9s9G for ; Tue, 15 Jan 2019 00:26:09 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726561AbfANN0I (ORCPT ); Mon, 14 Jan 2019 08:26:08 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:37304 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726545AbfANN0I (ORCPT ); Mon, 14 Jan 2019 08:26:08 -0500 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x0EDPKb0098063; Mon, 14 Jan 2019 07:25:20 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1547472320; bh=fRCs1u9heVGXhJdOX/5kFPoouLrzDR4CIAvdI4U5mZU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=SKjVgiWTPNKi9M141DjVIVi13fIItZeEen+LkOkVdfDjQkP02nfm8hhqkQZjn3wK2 VCyMies27BaNrsspb2Zyo0mcEtja9auPdzatQncPhF94AA+Q9TLDWneohJsyY0a/3z 4oAcmYCfikqghDVcIDrptGXvMrBAHKN60m7qypRs= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x0EDPKaf088730 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 14 Jan 2019 07:25:20 -0600 Received: from DFLE113.ent.ti.com (10.64.6.34) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Mon, 14 Jan 2019 07:25:19 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Mon, 14 Jan 2019 07:25:20 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x0EDOoWR028516; Mon, 14 Jan 2019 07:25:15 -0600 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Rob Herring , Lorenzo Pieralisi CC: Kishon Vijay Abraham I , Jingoo Han , Bjorn Helgaas , Mark Rutland , Arnd Bergmann , Greg Kroah-Hartman , Murali Karicheri , Jesper Nilsson , , , , , , Subject: [PATCH 05/24] PCI: keystone: Use platform_get_resource_byname to get memory resources Date: Mon, 14 Jan 2019 18:54:05 +0530 Message-ID: <20190114132424.6445-6-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190114132424.6445-1-kishon@ti.com> References: <20190114132424.6445-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Use platform_get_resource_byname() instead of platform_get_resource() which uses index to get memory resources. While at that get the memory resource defined specifically for configuration space instead of deriving the configuration space address from dbics address space. Since pci-keystone driver has never worked out of the box in mainline kernel, dt backward compatibility is ignored. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 3f917ffa9105..88766d4cb50c 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -44,7 +44,6 @@ #define CFG_TYPE1 BIT(24) #define OB_SIZE 0x030 -#define SPACE0_REMOTE_CFG_OFFSET 0x1000 #define OB_OFFSET_INDEX(n) (0x200 + (8 * (n))) #define OB_OFFSET_HI(n) (0x204 + (8 * (n))) #define OB_ENABLEN BIT(0) @@ -790,21 +789,19 @@ static int __init ks_pcie_add_pcie_port(struct keystone_pcie *ks_pcie, struct resource *res; int ret; - /* Index 0 is the config reg. space address */ - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbics"); pci->dbi_base = devm_pci_remap_cfg_resource(dev, res); if (IS_ERR(pci->dbi_base)) return PTR_ERR(pci->dbi_base); - /* - * We set these same and is used in pcie rd/wr_other_conf - * functions - */ - pp->va_cfg0_base = pci->dbi_base + SPACE0_REMOTE_CFG_OFFSET; + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config"); + pp->va_cfg0_base = devm_pci_remap_cfg_resource(dev, res); + if (IS_ERR(pp->va_cfg0_base)) + return PTR_ERR(pp->va_cfg0_base); + pp->va_cfg1_base = pp->va_cfg0_base; - /* Index 1 is the application reg. space address */ - res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "app"); ks_pcie->va_app_base = devm_ioremap_resource(dev, res); if (IS_ERR(ks_pcie->va_app_base)) return PTR_ERR(ks_pcie->va_app_base); From patchwork Mon Jan 14 13:24:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 1024533 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="kwDa8FXb"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43dZ6h6hrxz9s3q for ; Tue, 15 Jan 2019 00:28:28 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726786AbfANN0Z (ORCPT ); Mon, 14 Jan 2019 08:26:25 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:37378 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726470AbfANN0Y (ORCPT ); Mon, 14 Jan 2019 08:26:24 -0500 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x0EDPPKD098075; Mon, 14 Jan 2019 07:25:25 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1547472325; bh=i/fk/tt+1LjhsntKlkuFU4S9fmttwzxDH8syQnMt+Q0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=kwDa8FXbuhQUUiErE1lls7qIheWSUrEoPhE9vxxyxA3sgQR0ynmXnP5v9DGPcwU/5 o02li3c/WCT/mEBuoEX9WG6NPUEtWv7DVQx+FO/EUlb6cHlNt7cruzIwguaBhGF+Xa m5lRS8vuu8z2+hbypSt0LPymTbtu6m7XYMvdD8lU= Received: from DFLE113.ent.ti.com (dfle113.ent.ti.com [10.64.6.34]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x0EDPPSJ093881 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 14 Jan 2019 07:25:25 -0600 Received: from DFLE109.ent.ti.com (10.64.6.30) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Mon, 14 Jan 2019 07:25:25 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Mon, 14 Jan 2019 07:25:25 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x0EDOoWS028516; Mon, 14 Jan 2019 07:25:20 -0600 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Rob Herring , Lorenzo Pieralisi CC: Kishon Vijay Abraham I , Jingoo Han , Bjorn Helgaas , Mark Rutland , Arnd Bergmann , Greg Kroah-Hartman , Murali Karicheri , Jesper Nilsson , , , , , , Subject: [PATCH 06/24] PCI: keystone: Move initializations to appropriate places Date: Mon, 14 Jan 2019 18:54:06 +0530 Message-ID: <20190114132424.6445-7-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190114132424.6445-1-kishon@ti.com> References: <20190114132424.6445-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org No functional change. Move host specific platform_get_resource to ks_add_pcie_port and the common platform_get_resource (applicable to both host and endpoint) to probe. This is in preparation for adding endpoint support to pci-keystone driver. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 27 +++++++++++++---------- 1 file changed, 15 insertions(+), 12 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 88766d4cb50c..ce2f5c25f7a3 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -789,11 +789,6 @@ static int __init ks_pcie_add_pcie_port(struct keystone_pcie *ks_pcie, struct resource *res; int ret; - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbics"); - pci->dbi_base = devm_pci_remap_cfg_resource(dev, res); - if (IS_ERR(pci->dbi_base)) - return PTR_ERR(pci->dbi_base); - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config"); pp->va_cfg0_base = devm_pci_remap_cfg_resource(dev, res); if (IS_ERR(pp->va_cfg0_base)) @@ -801,13 +796,6 @@ static int __init ks_pcie_add_pcie_port(struct keystone_pcie *ks_pcie, pp->va_cfg1_base = pp->va_cfg0_base; - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "app"); - ks_pcie->va_app_base = devm_ioremap_resource(dev, res); - if (IS_ERR(ks_pcie->va_app_base)) - return PTR_ERR(ks_pcie->va_app_base); - - ks_pcie->app = *res; - pp->ops = &ks_pcie_host_ops; ret = dw_pcie_host_init(pp); if (ret) { @@ -878,6 +866,8 @@ static int __init ks_pcie_probe(struct platform_device *pdev) struct dw_pcie *pci; struct keystone_pcie *ks_pcie; struct device_link **link; + struct resource *res; + void __iomem *base; u32 num_viewport; struct phy **phy; u32 num_lanes; @@ -894,6 +884,19 @@ static int __init ks_pcie_probe(struct platform_device *pdev) if (!pci) return -ENOMEM; + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "app"); + ks_pcie->va_app_base = devm_ioremap_resource(dev, res); + if (IS_ERR(ks_pcie->va_app_base)) + return PTR_ERR(ks_pcie->va_app_base); + + ks_pcie->app = *res; + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbics"); + base = devm_pci_remap_cfg_resource(dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + pci->dbi_base = base; pci->dev = dev; pci->ops = &ks_pcie_dw_pcie_ops; From patchwork Mon Jan 14 13:24:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 1024510 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="I7BLWIMk"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43dZ4J4ZMzz9s9G for ; Tue, 15 Jan 2019 00:26:24 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726743AbfANN0I (ORCPT ); Mon, 14 Jan 2019 08:26:08 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:37306 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726554AbfANN0I (ORCPT ); Mon, 14 Jan 2019 08:26:08 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x0EDPUeB098095; Mon, 14 Jan 2019 07:25:30 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1547472330; bh=Oy9h1kP8jbCXe+8kD93AkYommSwhxCLq/ir/s6HONHk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=I7BLWIMkCXUivjd681dUFmq9w/8i0HBJxqyMjwzlhD6gZVkxjv9NSCKZ9cHLWJozz gNL7mZSacsXulhaqrB71ZNrD/e0a+/JcIa7294hkMz8BuxMpfBgGj6tUymevrAhYGw gVMADyVZk9/IIPqteaKo5Zce70edB/Sv7omySTY4= Received: from DLEE111.ent.ti.com (dlee111.ent.ti.com [157.170.170.22]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x0EDPU5q056610 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 14 Jan 2019 07:25:30 -0600 Received: from DLEE108.ent.ti.com (157.170.170.38) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Mon, 14 Jan 2019 07:25:29 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Mon, 14 Jan 2019 07:25:30 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x0EDOoWT028516; Mon, 14 Jan 2019 07:25:25 -0600 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Rob Herring , Lorenzo Pieralisi CC: Kishon Vijay Abraham I , Jingoo Han , Bjorn Helgaas , Mark Rutland , Arnd Bergmann , Greg Kroah-Hartman , Murali Karicheri , Jesper Nilsson , , , , , , Subject: [PATCH 07/24] dt-bindings: PCI: Add dt-binding to configure PCIe mode Date: Mon, 14 Jan 2019 18:54:07 +0530 Message-ID: <20190114132424.6445-8-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190114132424.6445-1-kishon@ti.com> References: <20190114132424.6445-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add "ti,syscon-pcie-mode" dt-binding to hold phandle to the syscon register that should be used to configure PCIe in RC mode or EP mode. Signed-off-by: Kishon Vijay Abraham I Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/pci/pci-keystone.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/pci-keystone.txt b/Documentation/devicetree/bindings/pci/pci-keystone.txt index 3a551687cfa2..8ee07197a063 100644 --- a/Documentation/devicetree/bindings/pci/pci-keystone.txt +++ b/Documentation/devicetree/bindings/pci/pci-keystone.txt @@ -23,6 +23,8 @@ pcie_msi_intc : Interrupt controller device node for MSI IRQ chip ti,syscon-pcie-id : phandle to the device control module required to set device id and vendor id. +ti,syscon-pcie-mode : phandle to the device control module required to configure + PCI in either RC mode or EP mode. Example: pcie_msi_intc: msi-interrupt-controller { From patchwork Mon Jan 14 13:24:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 1024521 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="r+bkx6Le"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43dZ5q2tpFz9sDr for ; Tue, 15 Jan 2019 00:27:43 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726538AbfANN1f (ORCPT ); Mon, 14 Jan 2019 08:27:35 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:37648 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726518AbfANN1e (ORCPT ); Mon, 14 Jan 2019 08:27:34 -0500 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x0EDPZg6098110; Mon, 14 Jan 2019 07:25:35 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1547472335; bh=tWr3enOfHY/N1zh//XsnGspmWYu0ckIGK/nsnUn+GzQ=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=r+bkx6LeW0pSvKeIOFzOA37U9B2R7sdKsI7CFyRpoUBLLGahmjzR8awEFLeUvIOMe s7gm/PgXpsrFbUePRYAk73vSDWqRTKkuLR3aVdYPtITHd26/G4eVaCsr7x97ZLUzs0 Z/oATG0y6z8y9Ik+n+0TDAEm+6B98W0CLRw2bcAQ= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x0EDPZr6088866 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 14 Jan 2019 07:25:35 -0600 Received: from DFLE107.ent.ti.com (10.64.6.28) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Mon, 14 Jan 2019 07:25:34 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Mon, 14 Jan 2019 07:25:34 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x0EDOoWU028516; Mon, 14 Jan 2019 07:25:30 -0600 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Rob Herring , Lorenzo Pieralisi CC: Kishon Vijay Abraham I , Jingoo Han , Bjorn Helgaas , Mark Rutland , Arnd Bergmann , Greg Kroah-Hartman , Murali Karicheri , Jesper Nilsson , , , , , , Subject: [PATCH 08/24] PCI: keystone: Explicitly set the PCIe mode Date: Mon, 14 Jan 2019 18:54:08 +0530 Message-ID: <20190114132424.6445-9-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190114132424.6445-1-kishon@ti.com> References: <20190114132424.6445-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Explicitly set the PCIe mode to BOOTCFG_DEVCFG instead of always relying on the default values. This is required when EP mode has to be explicitly written to BOOTCFG_DEVCFG register. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 37 +++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index ce2f5c25f7a3..d1ecf826dfe8 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -79,6 +79,15 @@ #define PCIE_RC_K2L 0xb00a #define PCIE_RC_K2G 0xb00b +#define KS_PCIE_DEV_TYPE_MASK (0x3 << 1) +#define KS_PCIE_DEV_TYPE(mode) ((mode) << 1) + +#define EP 0x0 +#define LEG_EP 0x1 +#define RC 0x2 + +#define KS_PCIE_SYSCLOCKOUTEN BIT(0) + #define to_keystone_pcie(x) dev_get_drvdata((x)->dev) struct keystone_pcie { @@ -859,6 +868,30 @@ static int ks_pcie_enable_phy(struct keystone_pcie *ks_pcie) return ret; } +static int ks_pcie_set_mode(struct device *dev) +{ + struct device_node *np = dev->of_node; + struct regmap *syscon; + u32 val; + u32 mask; + int ret = 0; + + syscon = syscon_regmap_lookup_by_phandle(np, "ti,syscon-pcie-mode"); + if (IS_ERR(syscon)) + return 0; + + mask = KS_PCIE_DEV_TYPE_MASK | KS_PCIE_SYSCLOCKOUTEN; + val = KS_PCIE_DEV_TYPE(RC) | KS_PCIE_SYSCLOCKOUTEN; + + ret = regmap_update_bits(syscon, 0, mask, val); + if (ret) { + dev_err(dev, "failed to set pcie mode\n"); + return ret; + } + + return 0; +} + static int __init ks_pcie_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -971,6 +1004,10 @@ static int __init ks_pcie_probe(struct platform_device *pdev) goto err_get_sync; } + ret = ks_pcie_set_mode(dev); + if (ret < 0) + goto err_get_sync; + ret = ks_pcie_add_pcie_port(ks_pcie, pdev); if (ret < 0) goto err_get_sync; From patchwork Mon Jan 14 13:24:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 1024512 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="fQ2FpcpH"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43dZ4c3gfyz9sDL for ; Tue, 15 Jan 2019 00:26:40 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726826AbfANN0d (ORCPT ); Mon, 14 Jan 2019 08:26:33 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:35074 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726526AbfANN0c (ORCPT ); Mon, 14 Jan 2019 08:26:32 -0500 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id x0EDPeY5106802; Mon, 14 Jan 2019 07:25:40 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1547472340; bh=7srJLFU2H5APGDHmyq9l+0rZG+OkuO025oUKh/xV4Ug=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=fQ2FpcpHFi9fBft51sGEOe6H5m2YVZz+0j8PiSKYDXcJMdAQeBYBTzGk8mwtul2H+ 2PvNpZW7bcN2E0ttMYe846KuE/7Mfl3L9aJVvVabvIkW4Tx2v6vrCyZlWUh5ImqgGp dlGVQXcCEZDXYY0mptaqcFLubJuAeCsxFzwtK84k= Received: from DLEE115.ent.ti.com (dlee115.ent.ti.com [157.170.170.26]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x0EDPdbp094124 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 14 Jan 2019 07:25:39 -0600 Received: from DLEE101.ent.ti.com (157.170.170.31) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Mon, 14 Jan 2019 07:25:40 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Mon, 14 Jan 2019 07:25:39 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x0EDOoWV028516; Mon, 14 Jan 2019 07:25:35 -0600 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Rob Herring , Lorenzo Pieralisi CC: Kishon Vijay Abraham I , Jingoo Han , Bjorn Helgaas , Mark Rutland , Arnd Bergmann , Greg Kroah-Hartman , Murali Karicheri , Jesper Nilsson , , , , , , Subject: [PATCH 09/24] dt-bindings: PCI: Document "atu" reg-names Date: Mon, 14 Jan 2019 18:54:09 +0530 Message-ID: <20190114132424.6445-10-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190114132424.6445-1-kishon@ti.com> References: <20190114132424.6445-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Document "atu" reg-names required to get the register space for ATU in Synopsys designware core version >= 4.80. Signed-off-by: Kishon Vijay Abraham I --- Documentation/devicetree/bindings/pci/designware-pcie.txt | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt index c124f9bc11f3..5561a1c060d0 100644 --- a/Documentation/devicetree/bindings/pci/designware-pcie.txt +++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt @@ -4,8 +4,11 @@ Required properties: - compatible: "snps,dw-pcie" for RC mode; "snps,dw-pcie-ep" for EP mode; -- reg: Should contain the configuration address space. -- reg-names: Must be "config" for the PCIe configuration space. +- reg: For designware cores version < 4.80 contains the configuration + address space. For designware core version >= 4.80, contains + the configuration and ATU address space +- reg-names: Must be "config" for the PCIe configuration space and "atu" for + the ATU address space. (The old way of getting the configuration address space from "ranges" is deprecated and should be avoided.) - num-lanes: number of lanes to use From patchwork Mon Jan 14 13:24:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 1024530 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="ogUqVufQ"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43dZ6X1GTtz9s3q for ; Tue, 15 Jan 2019 00:28:20 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726849AbfANN0m (ORCPT ); Mon, 14 Jan 2019 08:26:42 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:37436 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726839AbfANN0l (ORCPT ); Mon, 14 Jan 2019 08:26:41 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x0EDPimd098134; Mon, 14 Jan 2019 07:25:44 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1547472345; bh=D3SpjZ5R1aRjfVZ7VM2I5QEfz4WOvJBUIsbp05h8aqY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=ogUqVufQPF4gH6zHydPgoxdYDw/n+mQCs5EYKOMAVsJV0lAmfpZtpIUkjhHPmFqcN Dsli75pOExCF7Gc5hFeGXpulA4twdXnrTKmiXS2C37scp/zqNcgn2+z50ptGDA/rhc c2ZW7+Rtpdr22l/bkYPZqGa/1pi6B3vRQeIj9iMo= Received: from DFLE101.ent.ti.com (dfle101.ent.ti.com [10.64.6.22]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x0EDPi0Y056711 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 14 Jan 2019 07:25:44 -0600 Received: from DFLE112.ent.ti.com (10.64.6.33) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Mon, 14 Jan 2019 07:25:44 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Mon, 14 Jan 2019 07:25:44 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x0EDOoWW028516; Mon, 14 Jan 2019 07:25:40 -0600 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Rob Herring , Lorenzo Pieralisi CC: Kishon Vijay Abraham I , Jingoo Han , Bjorn Helgaas , Mark Rutland , Arnd Bergmann , Greg Kroah-Hartman , Murali Karicheri , Jesper Nilsson , , , , , , Subject: [PATCH 10/24] PCI: dwc: Enable iATU unroll for endpoint too Date: Mon, 14 Jan 2019 18:54:10 +0530 Message-ID: <20190114132424.6445-11-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190114132424.6445-1-kishon@ti.com> References: <20190114132424.6445-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org iatu_unroll_enabled flag is set only for Designware in host mode. However iATU unroll can be applicable for endpoint mode too. Set iatu_unroll_enabled flag in dw_pcie_setup which is common for both host mode and endpoint mode. Signed-off-by: Kishon Vijay Abraham I --- .../pci/controller/dwc/pcie-designware-ep.c | 4 ---- .../pci/controller/dwc/pcie-designware-host.c | 19 ------------------- drivers/pci/controller/dwc/pcie-designware.c | 19 +++++++++++++++++++ 3 files changed, 19 insertions(+), 23 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index 7a2925a16ab8..d5144781005b 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -515,10 +515,6 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) dev_err(dev, "dbi_base/dbi_base2 is not populated\n"); return -EINVAL; } - if (pci->iatu_unroll_enabled && !pci->atu_base) { - dev_err(dev, "atu_base is not populated\n"); - return -EINVAL; - } ret = of_property_read_u32(np, "num-ib-windows", &ep->num_ib_windows); if (ret < 0) { diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index d7184e1a7d92..1fb7eece78ab 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -629,17 +629,6 @@ static struct pci_ops dw_pcie_ops = { .write = dw_pcie_wr_conf, }; -static u8 dw_pcie_iatu_unroll_enabled(struct dw_pcie *pci) -{ - u32 val; - - val = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT); - if (val == 0xffffffff) - return 1; - - return 0; -} - void dw_pcie_setup_rc(struct pcie_port *pp) { u32 val, ctrl, num_ctrls; @@ -693,14 +682,6 @@ void dw_pcie_setup_rc(struct pcie_port *pp) * we should not program the ATU here. */ if (!pp->ops->rd_other_conf) { - /* Get iATU unroll support */ - pci->iatu_unroll_enabled = dw_pcie_iatu_unroll_enabled(pci); - dev_dbg(pci->dev, "iATU unroll: %s\n", - pci->iatu_unroll_enabled ? "enabled" : "disabled"); - - if (pci->iatu_unroll_enabled && !pci->atu_base) - pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET; - dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX0, PCIE_ATU_TYPE_MEM, pp->mem_base, pp->mem_bus_addr, pp->mem_size); diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 93ef8c31fb39..78539452c265 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -339,6 +339,17 @@ int dw_pcie_link_up(struct dw_pcie *pci) (!(val & PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING))); } +static u8 dw_pcie_iatu_unroll_enabled(struct dw_pcie *pci) +{ + u32 val; + + val = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT); + if (val == 0xffffffff) + return 1; + + return 0; +} + void dw_pcie_setup(struct dw_pcie *pci) { int ret; @@ -347,6 +358,14 @@ void dw_pcie_setup(struct dw_pcie *pci) struct device *dev = pci->dev; struct device_node *np = dev->of_node; + /* Get iATU unroll support */ + pci->iatu_unroll_enabled = dw_pcie_iatu_unroll_enabled(pci); + dev_dbg(pci->dev, "iATU unroll: %s\n", + pci->iatu_unroll_enabled ? "enabled" : "disabled"); + + if (pci->iatu_unroll_enabled && !pci->atu_base) + pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET; + ret = of_property_read_u32(np, "num-lanes", &lanes); if (ret) lanes = 0; From patchwork Mon Jan 14 13:24:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 1024528 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="UexewYwf"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43dZ6S4drlz9sD4 for ; Tue, 15 Jan 2019 00:28:16 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726861AbfANN0p (ORCPT ); Mon, 14 Jan 2019 08:26:45 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:35108 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726851AbfANN0n (ORCPT ); Mon, 14 Jan 2019 08:26:43 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id x0EDPnhR106834; Mon, 14 Jan 2019 07:25:49 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1547472349; bh=5utE+jodqQLD4g3Pt/AHbdOGuOmz2jyxoVSY0CpmSSw=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=UexewYwfuHEcVRAYewKVPjpC+xxXDwqrCAqKCw2vcqt+sYJbM3lXDUeDwjzaBiHj4 xHIARdb88JXKBTTT7SDOg9wTmLF064a9xEsmWqcc19strsqiLYZN2GzkuEVrSz87fi WeLKtMV7pt4he7NC1pcJ+oJAsAa8fQetoWk7xtaY= Received: from DLEE109.ent.ti.com (dlee109.ent.ti.com [157.170.170.41]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x0EDPnqL056742 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 14 Jan 2019 07:25:49 -0600 Received: from DLEE110.ent.ti.com (157.170.170.21) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Mon, 14 Jan 2019 07:25:49 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Mon, 14 Jan 2019 07:25:49 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x0EDOoWX028516; Mon, 14 Jan 2019 07:25:45 -0600 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Rob Herring , Lorenzo Pieralisi CC: Kishon Vijay Abraham I , Jingoo Han , Bjorn Helgaas , Mark Rutland , Arnd Bergmann , Greg Kroah-Hartman , Murali Karicheri , Jesper Nilsson , , , , , , Subject: [PATCH 11/24] PCI: dwc: Fix ATU identification for designware version >= 4.80 Date: Mon, 14 Jan 2019 18:54:11 +0530 Message-ID: <20190114132424.6445-12-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190114132424.6445-1-kishon@ti.com> References: <20190114132424.6445-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Synopsys designware version >= 4.80 uses a separate register space for programming ATU. The current code identifies if there exists a separate register space by accessing the register address of ATUs in designware version < 4.80. Accessing this address results in abort in the case of K2G. Fix it here by adding "version" member to struct dw_pcie. This should be set by platform specific drivers and designware core will use it to identify if the platform has a separate ATU space. For platforms which hasn't populated the version member, the old method of identification will still be used. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pcie-designware.c | 14 ++++++++------ drivers/pci/controller/dwc/pcie-designware.h | 1 + 2 files changed, 9 insertions(+), 6 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 78539452c265..37506aba22fe 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -358,13 +358,15 @@ void dw_pcie_setup(struct dw_pcie *pci) struct device *dev = pci->dev; struct device_node *np = dev->of_node; - /* Get iATU unroll support */ - pci->iatu_unroll_enabled = dw_pcie_iatu_unroll_enabled(pci); - dev_dbg(pci->dev, "iATU unroll: %s\n", - pci->iatu_unroll_enabled ? "enabled" : "disabled"); + if (pci->version >= 0x480A || (!pci->version && + dw_pcie_iatu_unroll_enabled(pci))) { + pci->iatu_unroll_enabled = true; + if (!pci->atu_base) + pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET; + } + dev_dbg(pci->dev, "iATU unroll: %s\n", pci->iatu_unroll_enabled ? + "enabled" : "disabled"); - if (pci->iatu_unroll_enabled && !pci->atu_base) - pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET; ret = of_property_read_u32(np, "num-lanes", &lanes); if (ret) diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index ea4b215b605d..4ab2e3dbd6bb 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -231,6 +231,7 @@ struct dw_pcie { struct pcie_port pp; struct dw_pcie_ep ep; const struct dw_pcie_ops *ops; + unsigned int version; }; #define to_dw_pcie_from_pp(port) container_of((port), struct dw_pcie, pp) From patchwork Mon Jan 14 13:24:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 1024529 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="oQwcW9+v"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43dZ6V3TJ3z9sD4 for ; Tue, 15 Jan 2019 00:28:18 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726858AbfANN0p (ORCPT ); Mon, 14 Jan 2019 08:26:45 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:37448 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726854AbfANN0n (ORCPT ); Mon, 14 Jan 2019 08:26:43 -0500 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x0EDPs7b098170; Mon, 14 Jan 2019 07:25:54 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1547472354; bh=GogJmhPjCHQln5mVKUVQZbQ+wSVFSwsYqqaCZro7fL4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=oQwcW9+vGGXoQFzkFFMkyS+/zrvRPAh6e8C6iKuoM321++ugdV9tsIdhwMx4bUefT q2c6YRMMK5tmUormImD1GnWa5OSED4Q1P9ROShpg0uhaRBPXB2zI1b+ETJyqCPIlw0 eOOzcDA/5QjxHbYmskQxV04UEJWa8F7ohOM13sac= Received: from DLEE109.ent.ti.com (dlee109.ent.ti.com [157.170.170.41]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x0EDPsSB088982 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 14 Jan 2019 07:25:54 -0600 Received: from DLEE100.ent.ti.com (157.170.170.30) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Mon, 14 Jan 2019 07:25:54 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Mon, 14 Jan 2019 07:25:54 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x0EDOoWY028516; Mon, 14 Jan 2019 07:25:49 -0600 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Rob Herring , Lorenzo Pieralisi CC: Kishon Vijay Abraham I , Jingoo Han , Bjorn Helgaas , Mark Rutland , Arnd Bergmann , Greg Kroah-Hartman , Murali Karicheri , Jesper Nilsson , , , , , , Subject: [PATCH 12/24] PCI: keystone: Prevent ARM32 specific code to be compiled for ARM64 Date: Mon, 14 Jan 2019 18:54:12 +0530 Message-ID: <20190114132424.6445-13-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190114132424.6445-1-kishon@ti.com> References: <20190114132424.6445-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org hook_fault_code is an ARM32 specific API for hooking into data abort. Since pci-keystone.c will be used for AM65X platforms which is an ARM64 platform, allow hook_fault_code to be compiled only for ARM32. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index d1ecf826dfe8..9d7cedd96505 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -693,6 +693,7 @@ static int ks_pcie_config_legacy_irq(struct keystone_pcie *ks_pcie) return ret; } +#ifdef CONFIG_ARM /* * When a PCI device does not exist during config cycles, keystone host gets a * bus error instead of returning 0xffffffff. This handler always returns 0 @@ -712,6 +713,7 @@ static int ks_pcie_fault(unsigned long addr, unsigned int fsr, return 0; } +#endif static int __init ks_pcie_init_id(struct keystone_pcie *ks_pcie) { @@ -761,12 +763,14 @@ static int __init ks_pcie_host_init(struct pcie_port *pp) if (ret < 0) return ret; +#ifdef CONFIG_ARM /* * PCIe access errors that result into OCP errors are caught by ARM as * "External aborts" */ hook_fault_code(17, ks_pcie_fault, SIGBUS, 0, "Asynchronous external abort"); +#endif ks_pcie_start_link(pci); dw_pcie_wait_for_link(pci); From patchwork Mon Jan 14 13:24:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 1024532 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="QeJjxbwR"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43dZ6b2yKRz9s9G for ; Tue, 15 Jan 2019 00:28:23 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726542AbfANN0j (ORCPT ); Mon, 14 Jan 2019 08:26:39 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:37386 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726788AbfANN00 (ORCPT ); Mon, 14 Jan 2019 08:26:26 -0500 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x0EDPxF2098180; Mon, 14 Jan 2019 07:25:59 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1547472359; bh=dX0AnoHumpKjN/Hxuc1DnDN/uBYu6jOtQe3dNmu6KNI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=QeJjxbwRlEW+xSMlQ8HyZ81VFQJCnXKOFFyaBXtwUl1aIoYPR5S8FNFNbFKkvb4Ny 5SehoVv98ILvTEByO/zjOjYEXOCOn/KW1jGdFHt2ke2DX3J802/zZcvj0f65HBAee9 Zm17cMuiDmVV52kHzbzUu/Si3sW0bFj4GdWsqEfo= Received: from DFLE112.ent.ti.com (dfle112.ent.ti.com [10.64.6.33]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x0EDPxEp012056 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 14 Jan 2019 07:25:59 -0600 Received: from DFLE107.ent.ti.com (10.64.6.28) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Mon, 14 Jan 2019 07:25:59 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Mon, 14 Jan 2019 07:25:59 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x0EDOoWZ028516; Mon, 14 Jan 2019 07:25:54 -0600 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Rob Herring , Lorenzo Pieralisi CC: Kishon Vijay Abraham I , Jingoo Han , Bjorn Helgaas , Mark Rutland , Arnd Bergmann , Greg Kroah-Hartman , Murali Karicheri , Jesper Nilsson , , , , , , Subject: [PATCH 13/24] dt-bindings: PCI: Add PCI RC dt binding documentation for AM654 Date: Mon, 14 Jan 2019 18:54:13 +0530 Message-ID: <20190114132424.6445-14-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190114132424.6445-1-kishon@ti.com> References: <20190114132424.6445-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add devicetree binding documentation for PCIe in RC mode present in AM654 SoC. Signed-off-by: Kishon Vijay Abraham I Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/pci/pci-keystone.txt | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/pci-keystone.txt b/Documentation/devicetree/bindings/pci/pci-keystone.txt index 8ee07197a063..5c60e911b8b1 100644 --- a/Documentation/devicetree/bindings/pci/pci-keystone.txt +++ b/Documentation/devicetree/bindings/pci/pci-keystone.txt @@ -11,7 +11,8 @@ described here as well as properties that are not applicable. Required Properties:- -compatibility: "ti,keystone-pcie" +compatibility: Should be "ti,keystone-pcie" for RC on Keystone2 SoC + Should be "ti,am654-pcie-rc" for RC on AM654x SoC reg: Three register ranges as listed in the reg-names property reg-names: "dbics" for the DesignWare PCIe registers, "app" for the TI specific application registers, "config" for the @@ -20,6 +21,9 @@ reg-names: "dbics" for the DesignWare PCIe registers, "app" for the pcie_msi_intc : Interrupt controller device node for MSI IRQ chip interrupt-cells: should be set to 1 interrupts: GIC interrupt lines connected to PCI MSI interrupt lines + (required if the compatible is "ti,keystone-pcie") +msi-map: As specified in Documentation/devicetree/bindings/pci/pci-msi.txt + (required if the compatible is "ti,am654-pcie-rc". ti,syscon-pcie-id : phandle to the device control module required to set device id and vendor id. From patchwork Mon Jan 14 13:24:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 1024514 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="IJ723G5k"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43dZ573fYJz9sBZ for ; Tue, 15 Jan 2019 00:27:07 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726948AbfANN04 (ORCPT ); Mon, 14 Jan 2019 08:26:56 -0500 Received: from lelv0142.ext.ti.com ([198.47.23.249]:40996 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726918AbfANN0v (ORCPT ); Mon, 14 Jan 2019 08:26:51 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x0EDQ43l041457; Mon, 14 Jan 2019 07:26:04 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1547472364; bh=OZSg3KxEAkBQw95faHATjuj/IFNC3Uemo5moPFtSIKo=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=IJ723G5k3K6h3SXYv+Z4a5ah7mB+U6PkRzzBF/H8xU74bFDWfIQEsqqtvykZWADM1 rdy2yWE/HaRTkdAp2XiWLI8QEJXHWPF5LWC3tTuZMbqCH7A2kcqI0Tl/KImXrGzqBP 0L7BiR3TyL5TVQtRQUBFTSEydZ9a9zJ6EQ9Rht4U= Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x0EDQ4rk057065 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 14 Jan 2019 07:26:04 -0600 Received: from DFLE106.ent.ti.com (10.64.6.27) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Mon, 14 Jan 2019 07:26:04 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Mon, 14 Jan 2019 07:26:03 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x0EDOoWa028516; Mon, 14 Jan 2019 07:25:59 -0600 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Rob Herring , Lorenzo Pieralisi CC: Kishon Vijay Abraham I , Jingoo Han , Bjorn Helgaas , Mark Rutland , Arnd Bergmann , Greg Kroah-Hartman , Murali Karicheri , Jesper Nilsson , , , , , , Subject: [PATCH 14/24] PCI: keystone: Add support for PCIe RC in AM654x Platforms Date: Mon, 14 Jan 2019 18:54:14 +0530 Message-ID: <20190114132424.6445-15-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190114132424.6445-1-kishon@ti.com> References: <20190114132424.6445-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add PCIe RC support for AM654x Platforms in pci-keystone.c Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/Kconfig | 2 +- drivers/pci/controller/dwc/pci-keystone.c | 124 +++++++++++++++++++--- 2 files changed, 113 insertions(+), 13 deletions(-) diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig index 548c58223868..0bb19e268a8a 100644 --- a/drivers/pci/controller/dwc/Kconfig +++ b/drivers/pci/controller/dwc/Kconfig @@ -104,7 +104,7 @@ config PCIE_SPEAR13XX config PCI_KEYSTONE bool "TI Keystone PCIe controller" - depends on ARCH_KEYSTONE || (ARM && COMPILE_TEST) + depends on ARCH_KEYSTONE || ARCH_K3 || ((ARM || ARM64) && COMPILE_TEST) depends on PCI_MSI_IRQ_DOMAIN select PCIE_DW_HOST help diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 9d7cedd96505..c2873339809a 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -88,8 +89,15 @@ #define KS_PCIE_SYSCLOCKOUTEN BIT(0) +#define AM654_PCIE_DEV_TYPE_MASK 0x3 + #define to_keystone_pcie(x) dev_get_drvdata((x)->dev) +struct ks_pcie_of_data { + const struct dw_pcie_host_ops *host_ops; + unsigned int version; +}; + struct keystone_pcie { struct dw_pcie *pci; /* PCI Device ID */ @@ -229,6 +237,16 @@ static int ks_pcie_msi_host_init(struct pcie_port *pp) return dw_pcie_allocate_domains(pp); } +static int ks_pcie_am654_msi_host_init(struct pcie_port *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct device *dev = pci->dev; + + dev_vdbg(dev, "dummy function so that DW core doesn't configure MSI\n"); + + return 0; +} + static void ks_pcie_enable_error_irq(struct keystone_pcie *ks_pcie) { ks_pcie_app_writel(ks_pcie, ERR_IRQ_ENABLE_SET, ERR_IRQ_ALL); @@ -325,6 +343,8 @@ static void ks_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie) u32 val; u32 num_viewport = ks_pcie->num_viewport; struct dw_pcie *pci = ks_pcie->pci; + struct device *dev = pci->dev; + struct device_node *np = dev->of_node; struct pcie_port *pp = &pci->pp; u64 start = pp->mem->start; u64 end = pp->mem->end; @@ -336,6 +356,9 @@ static void ks_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie) dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0); ks_pcie_clear_dbi_mode(ks_pcie); + if (of_device_is_compatible(np, "ti,am654-pcie-rc")) + return; + val = ilog2(OB_WIN_SIZE); ks_pcie_app_writel(ks_pcie, OB_SIZE, val); @@ -597,6 +620,8 @@ static int ks_pcie_config_msi_irq(struct keystone_pcie *ks_pcie) intc_np = of_get_child_by_name(np, "msi-interrupt-controller"); if (!intc_np) { + if (of_device_is_compatible(np, "ti,am654-pcie-rc")) + return 0; dev_WARN(dev, "msi-interrupt-controller node is absent\n"); return -EINVAL; } @@ -732,8 +757,10 @@ static int __init ks_pcie_init_id(struct keystone_pcie *ks_pcie) if (ret) return ret; + dw_pcie_dbi_ro_wr_en(pci); dw_pcie_writew_dbi(pci, PCI_VENDOR_ID, id & PCIE_VENDORID_MASK); dw_pcie_writew_dbi(pci, PCI_DEVICE_ID, id >> PCIE_DEVICEID_SHIFT); + dw_pcie_dbi_ro_wr_dis(pci); return 0; } @@ -786,6 +813,11 @@ static const struct dw_pcie_host_ops ks_pcie_host_ops = { .scan_bus = ks_pcie_v3_65_scan_bus, }; +static const struct dw_pcie_host_ops ks_pcie_am654_host_ops = { + .host_init = ks_pcie_host_init, + .msi_host_init = ks_pcie_am654_msi_host_init, +}; + static irqreturn_t ks_pcie_err_irq_handler(int irq, void *priv) { struct keystone_pcie *ks_pcie = priv; @@ -809,7 +841,6 @@ static int __init ks_pcie_add_pcie_port(struct keystone_pcie *ks_pcie, pp->va_cfg1_base = pp->va_cfg0_base; - pp->ops = &ks_pcie_host_ops; ret = dw_pcie_host_init(pp); if (ret) { dev_err(dev, "failed to initialize host\n"); @@ -819,14 +850,6 @@ static int __init ks_pcie_add_pcie_port(struct keystone_pcie *ks_pcie, return 0; } -static const struct of_device_id ks_pcie_of_match[] = { - { - .type = "pci", - .compatible = "ti,keystone-pcie", - }, - { }, -}; - static const struct dw_pcie_ops ks_pcie_dw_pcie_ops = { .start_link = ks_pcie_start_link, .stop_link = ks_pcie_stop_link, @@ -896,14 +919,66 @@ static int ks_pcie_set_mode(struct device *dev) return 0; } +static int ks_pcie_am654_set_mode(struct device *dev) +{ + struct device_node *np = dev->of_node; + struct regmap *syscon; + u32 val; + u32 mask; + int ret = 0; + + syscon = syscon_regmap_lookup_by_phandle(np, "ti,syscon-pcie-mode"); + if (IS_ERR(syscon)) + return 0; + + mask = AM654_PCIE_DEV_TYPE_MASK; + val = RC; + + ret = regmap_update_bits(syscon, 0, mask, val); + if (ret) { + dev_err(dev, "failed to set pcie mode\n"); + return ret; + } + + return 0; +} + +static const struct ks_pcie_of_data ks_pcie_rc_of_data = { + .host_ops = &ks_pcie_host_ops, + .version = 0x365A, +}; + +static const struct ks_pcie_of_data ks_pcie_am654_rc_of_data = { + .host_ops = &ks_pcie_am654_host_ops, + .version = 0x490A, +}; + +static const struct of_device_id ks_pcie_of_match[] = { + { + .type = "pci", + .data = &ks_pcie_rc_of_data, + .compatible = "ti,keystone-pcie", + }, + { + .data = &ks_pcie_am654_rc_of_data, + .compatible = "ti,am654-pcie-rc", + }, + { }, +}; + static int __init ks_pcie_probe(struct platform_device *pdev) { + const struct dw_pcie_host_ops *host_ops; struct device *dev = &pdev->dev; struct device_node *np = dev->of_node; + const struct ks_pcie_of_data *data; + const struct of_device_id *match; struct dw_pcie *pci; struct keystone_pcie *ks_pcie; struct device_link **link; + void __iomem *atu_base; struct resource *res; + unsigned int version; void __iomem *base; u32 num_viewport; struct phy **phy; @@ -913,6 +988,14 @@ static int __init ks_pcie_probe(struct platform_device *pdev) int irq; int i; + match = of_match_device(of_match_ptr(ks_pcie_of_match), dev); + data = (struct ks_pcie_of_data *)match->data; + if (!data) + return -EINVAL; + + version = data->version; + host_ops = data->host_ops; + ks_pcie = devm_kzalloc(dev, sizeof(*ks_pcie), GFP_KERNEL); if (!ks_pcie) return -ENOMEM; @@ -936,6 +1019,7 @@ static int __init ks_pcie_probe(struct platform_device *pdev) pci->dbi_base = base; pci->dev = dev; pci->ops = &ks_pcie_dw_pcie_ops; + pci->version = version; ret = of_property_read_u32(np, "num-viewport", &num_viewport); if (ret < 0) { @@ -1008,10 +1092,26 @@ static int __init ks_pcie_probe(struct platform_device *pdev) goto err_get_sync; } - ret = ks_pcie_set_mode(dev); - if (ret < 0) - goto err_get_sync; + if (pci->version >= 0x480A) { + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "atu"); + atu_base = devm_ioremap_resource(dev, res); + if (IS_ERR(atu_base)) { + ret = PTR_ERR(atu_base); + goto err_get_sync; + } + + pci->atu_base = atu_base; + + ret = ks_pcie_am654_set_mode(dev); + if (ret < 0) + goto err_get_sync; + } else { + ret = ks_pcie_set_mode(dev); + if (ret < 0) + goto err_get_sync; + } + pci->pp.ops = host_ops; ret = ks_pcie_add_pcie_port(ks_pcie, pdev); if (ret < 0) goto err_get_sync; From patchwork Mon Jan 14 13:24:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 1024513 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="fv7lvd0y"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43dZ4x5slJz9s9G for ; Tue, 15 Jan 2019 00:26:57 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726679AbfANN04 (ORCPT ); Mon, 14 Jan 2019 08:26:56 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:37530 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726570AbfANN0z (ORCPT ); Mon, 14 Jan 2019 08:26:55 -0500 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x0EDQ9U3098224; Mon, 14 Jan 2019 07:26:09 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1547472369; bh=4d1hv974DlQuBmZ/Ggs87YZnRdDcz6OLaZ5/NqWUvn4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=fv7lvd0yI0YqvB+Bmfx/l6qx2gCvEwKD1lzBoE69GFO9XpgTJIq9AiBzzNLKoSSNT Fati1EOsDVxi8Fvo/fZelkO2lr+A+tk+oMtcA+dbVVdb6VVjynLwcONmY805lEDa/b sEqMNS2SsfoWpF0c4338QThzH9rKao+kHIxVSbSU= Received: from DFLE106.ent.ti.com (dfle106.ent.ti.com [10.64.6.27]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x0EDQ9kF012402 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 14 Jan 2019 07:26:09 -0600 Received: from DFLE113.ent.ti.com (10.64.6.34) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Mon, 14 Jan 2019 07:26:08 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Mon, 14 Jan 2019 07:26:08 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x0EDOoWb028516; Mon, 14 Jan 2019 07:26:04 -0600 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Rob Herring , Lorenzo Pieralisi CC: Kishon Vijay Abraham I , Jingoo Han , Bjorn Helgaas , Mark Rutland , Arnd Bergmann , Greg Kroah-Hartman , Murali Karicheri , Jesper Nilsson , , , , , , Subject: [PATCH 15/24] PCI: keystone: Invoke phy_reset API before enabling PHY Date: Mon, 14 Jan 2019 18:54:15 +0530 Message-ID: <20190114132424.6445-16-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190114132424.6445-1-kishon@ti.com> References: <20190114132424.6445-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org SERDES connected to the PCIe controller in AM654 requires power on reset enable (POR_EN) to be set in the SERDES. The SERDES driver sets POR_EN in the reset ops and it has to be invoked before init or enable ops. In order for SERDES driver to set POR_EN, invoke phy_reset API in pci-keystone driver. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index c2873339809a..e2f4e7c01b5a 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -873,6 +873,10 @@ static int ks_pcie_enable_phy(struct keystone_pcie *ks_pcie) int num_lanes = ks_pcie->num_lanes; for (i = 0; i < num_lanes; i++) { + ret = phy_reset(ks_pcie->phy[i]); + if (ret < 0) + goto err_phy; + ret = phy_init(ks_pcie->phy[i]); if (ret < 0) goto err_phy; From patchwork Mon Jan 14 13:24:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 1024526 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="az+c5PAy"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43dZ6H6M2fz9s3q for ; Tue, 15 Jan 2019 00:28:07 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726909AbfANN0s (ORCPT ); Mon, 14 Jan 2019 08:26:48 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:37462 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726899AbfANN0s (ORCPT ); Mon, 14 Jan 2019 08:26:48 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x0EDQEa8098245; Mon, 14 Jan 2019 07:26:14 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1547472374; bh=JBZ+KApRI2tD19Gjs/0efSSSLgbMPMBQuRhTfDhOm2w=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=az+c5PAyuQYI/R4OJ6Yb4NImGUbk5jupD15MptWEu+9jq8Vjepl8fvI5GhZ1VDFtN 0JBWxlxcCdNaFAo0lsw1aXpSFqGOMvp4NY2uqZGX2+fQHS3qFXPyDTuI4BO1JRlt9B ieAwuUla1SUZN6P/xy1KzbzAtIDHBP37WeZD57bc= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x0EDQExh057326 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 14 Jan 2019 07:26:14 -0600 Received: from DFLE104.ent.ti.com (10.64.6.25) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Mon, 14 Jan 2019 07:26:13 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Mon, 14 Jan 2019 07:26:12 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x0EDOoWc028516; Mon, 14 Jan 2019 07:26:09 -0600 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Rob Herring , Lorenzo Pieralisi CC: Kishon Vijay Abraham I , Jingoo Han , Bjorn Helgaas , Mark Rutland , Arnd Bergmann , Greg Kroah-Hartman , Murali Karicheri , Jesper Nilsson , , , , , , Subject: [PATCH 16/24] PCI: endpoint: Add support to allocate aligned buffers to be mapped in BARs Date: Mon, 14 Jan 2019 18:54:16 +0530 Message-ID: <20190114132424.6445-17-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190114132424.6445-1-kishon@ti.com> References: <20190114132424.6445-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Modify pci_epf_alloc_space API to take alignment size as argument in order to argument in order to allocate aligned buffers to be mapped to BARs. Add 'align' parameter to epc_features which can be used by platform drivers to specifiy the BAR allocation alignment requirements and use this while invoking pci_epf_alloc_space. This is mainly required for Synopsys Designware PCIe core which masks the lower bits based on the BAR size (See "I/O and MEM Match Modes" section in DesignWare Cores PCI Express Controller Databook version 4.90a). Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/endpoint/functions/pci-epf-test.c | 5 +++-- drivers/pci/endpoint/pci-epf-core.c | 10 ++++++++-- include/linux/pci-epc.h | 2 ++ include/linux/pci-epf.h | 3 ++- 4 files changed, 15 insertions(+), 5 deletions(-) diff --git a/drivers/pci/endpoint/functions/pci-epf-test.c b/drivers/pci/endpoint/functions/pci-epf-test.c index 2e0fb231ce0c..faffae2551ed 100644 --- a/drivers/pci/endpoint/functions/pci-epf-test.c +++ b/drivers/pci/endpoint/functions/pci-epf-test.c @@ -438,7 +438,7 @@ static int pci_epf_test_alloc_space(struct pci_epf *epf) epc_features = epf_test->epc_features; base = pci_epf_alloc_space(epf, sizeof(struct pci_epf_test_reg), - test_reg_bar); + test_reg_bar, epc_features->align); if (!base) { dev_err(dev, "Failed to allocated register space\n"); return -ENOMEM; @@ -453,7 +453,8 @@ static int pci_epf_test_alloc_space(struct pci_epf *epf) if (!!(epc_features->reserved_bar & (1 << bar))) continue; - base = pci_epf_alloc_space(epf, bar_size[bar], bar); + base = pci_epf_alloc_space(epf, bar_size[bar], bar, + epc_features->align); if (!base) dev_err(dev, "Failed to allocate space for BAR%d\n", bar); diff --git a/drivers/pci/endpoint/pci-epf-core.c b/drivers/pci/endpoint/pci-epf-core.c index 8bfdcd291196..fb1306de8f40 100644 --- a/drivers/pci/endpoint/pci-epf-core.c +++ b/drivers/pci/endpoint/pci-epf-core.c @@ -109,10 +109,12 @@ EXPORT_SYMBOL_GPL(pci_epf_free_space); * pci_epf_alloc_space() - allocate memory for the PCI EPF register space * @size: the size of the memory that has to be allocated * @bar: the BAR number corresponding to the allocated register space + * @align: alignment size for the allocation region * * Invoke to allocate memory for the PCI EPF register space. */ -void *pci_epf_alloc_space(struct pci_epf *epf, size_t size, enum pci_barno bar) +void *pci_epf_alloc_space(struct pci_epf *epf, size_t size, enum pci_barno bar, + size_t align) { void *space; struct device *dev = epf->epc->dev.parent; @@ -120,7 +122,11 @@ void *pci_epf_alloc_space(struct pci_epf *epf, size_t size, enum pci_barno bar) if (size < 128) size = 128; - size = roundup_pow_of_two(size); + + if (align) + size = ALIGN(size, align); + else + size = roundup_pow_of_two(size); space = dma_alloc_coherent(dev, size, &phys_addr, GFP_KERNEL); if (!space) { diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h index c3ffa3917f88..f641badc2c61 100644 --- a/include/linux/pci-epc.h +++ b/include/linux/pci-epc.h @@ -109,6 +109,7 @@ struct pci_epc { * @reserved_bar: bitmap to indicate reserved BAR unavailable to function driver * @bar_fixed_64bit: bitmap to indicate fixed 64bit BARs * @bar_fixed_size: Array specifying the size supported by each BAR + * @align: alignment size required for BAR buffer allocation */ struct pci_epc_features { unsigned int linkup_notifier : 1; @@ -117,6 +118,7 @@ struct pci_epc_features { u8 reserved_bar; u8 bar_fixed_64bit; u64 bar_fixed_size[BAR_5 + 1]; + size_t align; }; #define to_pci_epc(device) container_of((device), struct pci_epc, dev) diff --git a/include/linux/pci-epf.h b/include/linux/pci-epf.h index ec02f58758c8..2d6f07556682 100644 --- a/include/linux/pci-epf.h +++ b/include/linux/pci-epf.h @@ -149,7 +149,8 @@ void pci_epf_destroy(struct pci_epf *epf); int __pci_epf_register_driver(struct pci_epf_driver *driver, struct module *owner); void pci_epf_unregister_driver(struct pci_epf_driver *driver); -void *pci_epf_alloc_space(struct pci_epf *epf, size_t size, enum pci_barno bar); +void *pci_epf_alloc_space(struct pci_epf *epf, size_t size, enum pci_barno bar, + size_t align); void pci_epf_free_space(struct pci_epf *epf, void *addr, enum pci_barno bar); int pci_epf_bind(struct pci_epf *epf); void pci_epf_unbind(struct pci_epf *epf); From patchwork Mon Jan 14 13:24:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 1024527 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="bgyT0zhx"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43dZ6Q5sCxz9sD4 for ; Tue, 15 Jan 2019 00:28:14 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726869AbfANN0p (ORCPT ); Mon, 14 Jan 2019 08:26:45 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:37452 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726653AbfANN0o (ORCPT ); Mon, 14 Jan 2019 08:26:44 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x0EDQIVD098267; Mon, 14 Jan 2019 07:26:18 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1547472378; bh=1cBzf8O7pgKPJLJpe2QIGf7wnuv4q+HWdzVaE+h4hbQ=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=bgyT0zhx5yihzelR3UnzYLsdRrwtvMLZBQv1133Pw15tSLJDry174Vqrccylk2Enf koOPPMuTnDtK7qMlQ+gJaVWzsENRihV3LeNXCLud6WVxwxMRLDBrR0s/BVhrLZkHVA 3Wu5aseWTX/8eIp+CssiQmY0bAqdW0Ov823EsLYo= Received: from DFLE111.ent.ti.com (dfle111.ent.ti.com [10.64.6.32]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x0EDQIYC057353 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 14 Jan 2019 07:26:18 -0600 Received: from DFLE100.ent.ti.com (10.64.6.21) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Mon, 14 Jan 2019 07:26:18 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Mon, 14 Jan 2019 07:26:18 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x0EDOoWd028516; Mon, 14 Jan 2019 07:26:14 -0600 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Rob Herring , Lorenzo Pieralisi CC: Kishon Vijay Abraham I , Jingoo Han , Bjorn Helgaas , Mark Rutland , Arnd Bergmann , Greg Kroah-Hartman , Murali Karicheri , Jesper Nilsson , , , , , , Subject: [PATCH 17/24] PCI: dwc: Add const qualifier to struct dw_pcie_ep_ops Date: Mon, 14 Jan 2019 18:54:17 +0530 Message-ID: <20190114132424.6445-18-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190114132424.6445-1-kishon@ti.com> References: <20190114132424.6445-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add const qualifier to struct dw_pcie_ep_ops member of struct dw_pcie_ep. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-dra7xx.c | 2 +- drivers/pci/controller/dwc/pcie-artpec6.c | 2 +- drivers/pci/controller/dwc/pcie-designware-plat.c | 2 +- drivers/pci/controller/dwc/pcie-designware.h | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-dra7xx.c b/drivers/pci/controller/dwc/pci-dra7xx.c index 15620cfa617b..b4fbb4be212f 100644 --- a/drivers/pci/controller/dwc/pci-dra7xx.c +++ b/drivers/pci/controller/dwc/pci-dra7xx.c @@ -401,7 +401,7 @@ dra7xx_pcie_get_features(struct dw_pcie_ep *ep) return &dra7xx_pcie_epc_features; } -static struct dw_pcie_ep_ops pcie_ep_ops = { +static const struct dw_pcie_ep_ops pcie_ep_ops = { .ep_init = dra7xx_pcie_ep_init, .raise_irq = dra7xx_pcie_raise_irq, .get_features = dra7xx_pcie_get_features, diff --git a/drivers/pci/controller/dwc/pcie-artpec6.c b/drivers/pci/controller/dwc/pcie-artpec6.c index dba83abfe764..d00252bd8fae 100644 --- a/drivers/pci/controller/dwc/pcie-artpec6.c +++ b/drivers/pci/controller/dwc/pcie-artpec6.c @@ -444,7 +444,7 @@ static int artpec6_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no, return 0; } -static struct dw_pcie_ep_ops pcie_ep_ops = { +static const struct dw_pcie_ep_ops pcie_ep_ops = { .ep_init = artpec6_pcie_ep_init, .raise_irq = artpec6_pcie_raise_irq, }; diff --git a/drivers/pci/controller/dwc/pcie-designware-plat.c b/drivers/pci/controller/dwc/pcie-designware-plat.c index 3be87126aef3..0852f42ad844 100644 --- a/drivers/pci/controller/dwc/pcie-designware-plat.c +++ b/drivers/pci/controller/dwc/pcie-designware-plat.c @@ -108,7 +108,7 @@ dw_plat_pcie_get_features(struct dw_pcie_ep *ep) return &dw_plat_pcie_epc_features; } -static struct dw_pcie_ep_ops pcie_ep_ops = { +static const struct dw_pcie_ep_ops pcie_ep_ops = { .ep_init = dw_plat_pcie_ep_init, .raise_irq = dw_plat_pcie_ep_raise_irq, .get_features = dw_plat_pcie_get_features, diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 4ab2e3dbd6bb..8a941f2fffcb 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -193,7 +193,7 @@ struct dw_pcie_ep_ops { struct dw_pcie_ep { struct pci_epc *epc; - struct dw_pcie_ep_ops *ops; + const struct dw_pcie_ep_ops *ops; phys_addr_t phys_base; size_t addr_size; size_t page_size; From patchwork Mon Jan 14 13:24:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 1024515 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="LgOlGy4N"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43dZ5B0Gdkz9sDT for ; Tue, 15 Jan 2019 00:27:10 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726700AbfANN1H (ORCPT ); Mon, 14 Jan 2019 08:27:07 -0500 Received: from lelv0142.ext.ti.com ([198.47.23.249]:41038 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726624AbfANN04 (ORCPT ); Mon, 14 Jan 2019 08:26:56 -0500 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x0EDQNdX041522; Mon, 14 Jan 2019 07:26:23 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1547472383; bh=jYEVHutp0v29B4vfiqJTI22HzuJxQ7SOmOLmjmfhfQ0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=LgOlGy4NgpIjpvhvjeFNp7k+EJqQaC1dStD2NaujHPGsfVGi23pgkpuDx/erK03sg doJ9gkfcp6JxCExzgpHNFAQP5N6B4UTHEFD4XihreaEcNP6b0y9OWxlln5wg8QdHJI KRCXx5OH1HjHTbr0/3UfrtrGuZqPxO6o3cFJDwJ4= Received: from DLEE113.ent.ti.com (dlee113.ent.ti.com [157.170.170.24]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x0EDQNPu089642 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 14 Jan 2019 07:26:23 -0600 Received: from DLEE104.ent.ti.com (157.170.170.34) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Mon, 14 Jan 2019 07:26:23 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Mon, 14 Jan 2019 07:26:23 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x0EDOoWe028516; Mon, 14 Jan 2019 07:26:19 -0600 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Rob Herring , Lorenzo Pieralisi CC: Kishon Vijay Abraham I , Jingoo Han , Bjorn Helgaas , Mark Rutland , Arnd Bergmann , Greg Kroah-Hartman , Murali Karicheri , Jesper Nilsson , , , , , , Subject: [PATCH 18/24] PCI: dwc: Fix dw_pcie_ep_find_capability to return correct capability offset Date: Mon, 14 Jan 2019 18:54:18 +0530 Message-ID: <20190114132424.6445-19-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190114132424.6445-1-kishon@ti.com> References: <20190114132424.6445-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org commit beb4641a787df79a ("PCI: dwc: Add MSI-X callbacks handler") while adding MSI-X callback handler, introduced dw_pcie_ep_find_capability and __dw_pcie_ep_find_next_cap for finding the MSI and MSIX capability. However if MSI or MSIX capability is the last capability (i.e there are no additional items in the capabilities list and the Next Capability Pointer is set to '0'), __dw_pcie_ep_find_next_cap will return '0' even though MSI or MSIX capability may be present. This is because of incorrect ordering of "next_cap_ptr" check. Fix it here. Fixes: beb4641a787df79a142 ("PCI: dwc: Add MSI-X callbacks handler") Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pcie-designware-ep.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index d5144781005b..cd51b008858c 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -46,16 +46,19 @@ static u8 __dw_pcie_ep_find_next_cap(struct dw_pcie *pci, u8 cap_ptr, u8 cap_id, next_cap_ptr; u16 reg; + if (!cap_ptr) + return 0; + reg = dw_pcie_readw_dbi(pci, cap_ptr); - next_cap_ptr = (reg & 0xff00) >> 8; cap_id = (reg & 0x00ff); - if (!next_cap_ptr || cap_id > PCI_CAP_ID_MAX) + if (cap_id > PCI_CAP_ID_MAX) return 0; if (cap_id == cap) return cap_ptr; + next_cap_ptr = (reg & 0xff00) >> 8; return __dw_pcie_ep_find_next_cap(pci, next_cap_ptr, cap); } @@ -67,9 +70,6 @@ static u8 dw_pcie_ep_find_capability(struct dw_pcie *pci, u8 cap) reg = dw_pcie_readw_dbi(pci, PCI_CAPABILITY_LIST); next_cap_ptr = (reg & 0x00ff); - if (!next_cap_ptr) - return 0; - return __dw_pcie_ep_find_next_cap(pci, next_cap_ptr, cap); } From patchwork Mon Jan 14 13:24:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 1024525 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="ZHlcraTR"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43dZ6G42Crz9sD4 for ; Tue, 15 Jan 2019 00:28:06 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726518AbfANN1p (ORCPT ); Mon, 14 Jan 2019 08:27:45 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:37472 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726911AbfANN0t (ORCPT ); Mon, 14 Jan 2019 08:26:49 -0500 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x0EDQSj6098291; Mon, 14 Jan 2019 07:26:28 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1547472388; bh=Qffs6RSDOTYhNf6TDkmKFW38qdsa/BRhYFbUVoB22J4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=ZHlcraTRgFvdLrDPcTUXknoZdwb94KBedKntzDrJTghFt1ZL3U8VoZstrwHkjwdQb ld6sRDqbBnE6CwS3GxUYm0ruMmCvGw9kpZMwrdCrUmajB09zV1h4lsCGq45VQ/Vpjr O7lUzvZ5mrPJaCFptBTabyfEtSywmWcqWd7mJ+QE= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x0EDQSVj012686 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 14 Jan 2019 07:26:28 -0600 Received: from DLEE107.ent.ti.com (157.170.170.37) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Mon, 14 Jan 2019 07:26:28 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Mon, 14 Jan 2019 07:26:28 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x0EDOoWf028516; Mon, 14 Jan 2019 07:26:23 -0600 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Rob Herring , Lorenzo Pieralisi CC: Kishon Vijay Abraham I , Jingoo Han , Bjorn Helgaas , Mark Rutland , Arnd Bergmann , Greg Kroah-Hartman , Murali Karicheri , Jesper Nilsson , , , , , , Subject: [PATCH 19/24] PCI: dwc: Add callbacks for accessing dbi2 address space Date: Mon, 14 Jan 2019 18:54:19 +0530 Message-ID: <20190114132424.6445-20-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190114132424.6445-1-kishon@ti.com> References: <20190114132424.6445-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Certain platforms like TI's AM654 doesn't have separate address space for dbi2 instead they are accessed using the same address space as dbi with some configuration bit set. In order to support such platforms, add callbacks for accessing dbi2 address space. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pcie-designware.c | 31 ++++++++++++++++++++ drivers/pci/controller/dwc/pcie-designware.h | 12 ++++++-- 2 files changed, 41 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 37506aba22fe..ccb68e6b6d54 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -89,6 +89,37 @@ void __dw_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg, dev_err(pci->dev, "Write DBI address failed\n"); } +u32 __dw_pcie_read_dbi2(struct dw_pcie *pci, void __iomem *base, u32 reg, + size_t size) +{ + int ret; + u32 val; + + if (pci->ops->read_dbi2) + return pci->ops->read_dbi2(pci, base, reg, size); + + ret = dw_pcie_read(base + reg, size, &val); + if (ret) + dev_err(pci->dev, "read DBI address failed\n"); + + return val; +} + +void __dw_pcie_write_dbi2(struct dw_pcie *pci, void __iomem *base, u32 reg, + size_t size, u32 val) +{ + int ret; + + if (pci->ops->write_dbi2) { + pci->ops->write_dbi2(pci, base, reg, size, val); + return; + } + + ret = dw_pcie_write(base + reg, size, val); + if (ret) + dev_err(pci->dev, "write DBI address failed\n"); +} + static u32 dw_pcie_readl_ob_unroll(struct dw_pcie *pci, u32 index, u32 reg) { u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index); diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 8a941f2fffcb..066ff5cf4eae 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -215,6 +215,10 @@ struct dw_pcie_ops { size_t size); void (*write_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg, size_t size, u32 val); + u32 (*read_dbi2)(struct dw_pcie *pcie, void __iomem *base, u32 reg, + size_t size); + void (*write_dbi2)(struct dw_pcie *pcie, void __iomem *base, u32 reg, + size_t size, u32 val); int (*link_up)(struct dw_pcie *pcie); int (*start_link)(struct dw_pcie *pcie); void (*stop_link)(struct dw_pcie *pcie); @@ -246,6 +250,10 @@ u32 __dw_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg, size_t size); void __dw_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg, size_t size, u32 val); +u32 __dw_pcie_read_dbi2(struct dw_pcie *pci, void __iomem *base, u32 reg, + size_t size); +void __dw_pcie_write_dbi2(struct dw_pcie *pci, void __iomem *base, u32 reg, + size_t size, u32 val); int dw_pcie_link_up(struct dw_pcie *pci); int dw_pcie_wait_for_link(struct dw_pcie *pci); void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, @@ -289,12 +297,12 @@ static inline u8 dw_pcie_readb_dbi(struct dw_pcie *pci, u32 reg) static inline void dw_pcie_writel_dbi2(struct dw_pcie *pci, u32 reg, u32 val) { - __dw_pcie_write_dbi(pci, pci->dbi_base2, reg, 0x4, val); + __dw_pcie_write_dbi2(pci, pci->dbi_base2, reg, 0x4, val); } static inline u32 dw_pcie_readl_dbi2(struct dw_pcie *pci, u32 reg) { - return __dw_pcie_read_dbi(pci, pci->dbi_base2, reg, 0x4); + return __dw_pcie_read_dbi2(pci, pci->dbi_base2, reg, 0x4); } static inline void dw_pcie_writel_atu(struct dw_pcie *pci, u32 reg, u32 val) From patchwork Mon Jan 14 13:24:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 1024520 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="Y1KwhfVk"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43dZ5f5DbYz9sBZ for ; Tue, 15 Jan 2019 00:27:34 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726990AbfANN1N (ORCPT ); Mon, 14 Jan 2019 08:27:13 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:35184 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726624AbfANN1M (ORCPT ); Mon, 14 Jan 2019 08:27:12 -0500 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id x0EDQXCi107005; Mon, 14 Jan 2019 07:26:33 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1547472393; bh=bw0Ut73XkbaUy4HNJPK+MOEGDGM+u+KTb6J5j94keH0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Y1KwhfVka4uJtVqH+UZHTB9MPmcv9JfFP6wAJu8GqYdjYmcd/CrnP73a/WEE8g4yI xXOIvQBTHY5Js79l9EAGvDCb+FwxMgyY/GR1Vm89mdYUAYQ1UuaMFrSkeDC3BEqtK6 VVG3jttxejlFOX4LnasxKwQKUfRlSIxtRZmS3tP0= Received: from DLEE114.ent.ti.com (dlee114.ent.ti.com [157.170.170.25]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x0EDQXC5012727 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 14 Jan 2019 07:26:33 -0600 Received: from DLEE107.ent.ti.com (157.170.170.37) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Mon, 14 Jan 2019 07:26:33 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Mon, 14 Jan 2019 07:26:33 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x0EDOoWg028516; Mon, 14 Jan 2019 07:26:28 -0600 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Rob Herring , Lorenzo Pieralisi CC: Kishon Vijay Abraham I , Jingoo Han , Bjorn Helgaas , Mark Rutland , Arnd Bergmann , Greg Kroah-Hartman , Murali Karicheri , Jesper Nilsson , , , , , , Subject: [PATCH 20/24] PCI: keystone: Add support for PCIe EP in AM654x Platforms Date: Mon, 14 Jan 2019 18:54:20 +0530 Message-ID: <20190114132424.6445-21-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190114132424.6445-1-kishon@ti.com> References: <20190114132424.6445-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add PCIe EP support for AM654x Platforms in pci-keystone.c Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/Kconfig | 23 ++- drivers/pci/controller/dwc/pci-keystone.c | 216 ++++++++++++++++++++-- 2 files changed, 223 insertions(+), 16 deletions(-) diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig index 0bb19e268a8a..ae3465fd194b 100644 --- a/drivers/pci/controller/dwc/Kconfig +++ b/drivers/pci/controller/dwc/Kconfig @@ -105,14 +105,33 @@ config PCIE_SPEAR13XX config PCI_KEYSTONE bool "TI Keystone PCIe controller" depends on ARCH_KEYSTONE || ARCH_K3 || ((ARM || ARM64) && COMPILE_TEST) - depends on PCI_MSI_IRQ_DOMAIN - select PCIE_DW_HOST help Say Y here if you want to enable PCI controller support on Keystone SoCs. The PCI controller on Keystone is based on DesignWare hardware and therefore the driver re-uses the DesignWare core functions to implement the driver. +if PCI_KEYSTONE + +config PCI_KEYSTONE_HOST + bool "PCI Keystone Host Mode" + depends on PCI_MSI_IRQ_DOMAIN + select PCIE_DW_HOST + default y + help + Enables support for the PCIe controller in the Keystone SoC to work in + host mode. + +config PCI_KEYSTONE_EP + bool "PCI Keystone Endpoint Mode" + depends on PCI_ENDPOINT + select PCIE_DW_EP + help + Enables support for the PCIe controller in the Keystone SoC to work in + endpoint mode. + +endif + config PCI_LAYERSCAPE bool "Freescale Layerscape PCIe controller" depends on OF && (ARM || ARCH_LAYERSCAPE || COMPILE_TEST) diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index e2f4e7c01b5a..adeb3565c11d 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -50,6 +50,12 @@ #define OB_ENABLEN BIT(0) #define OB_WIN_SIZE 8 /* 8MB */ +#define PCIE_LEGACY_IRQ_ENABLE_SET(n) (0x188 + (0x10 * ((n) - 1))) +#define PCIE_LEGACY_IRQ_ENABLE_CLR(n) (0x18c + (0x10 * ((n) - 1))) +#define PCIE_EP_IRQ_SET 0x64 +#define PCIE_EP_IRQ_CLR 0x68 +#define INT_ENABLE BIT(0) + /* IRQ register defines */ #define IRQ_EOI 0x050 @@ -90,11 +96,16 @@ #define KS_PCIE_SYSCLOCKOUTEN BIT(0) #define AM654_PCIE_DEV_TYPE_MASK 0x3 +#define AM654_WIN_SIZE SZ_64K + +#define APP_ADDR_SPACE_0 (16 * SZ_1K) #define to_keystone_pcie(x) dev_get_drvdata((x)->dev) struct ks_pcie_of_data { + enum dw_pcie_device_mode mode; const struct dw_pcie_host_ops *host_ops; + const struct dw_pcie_ep_ops *ep_ops; unsigned int version; }; @@ -850,12 +861,139 @@ static int __init ks_pcie_add_pcie_port(struct keystone_pcie *ks_pcie, return 0; } +static u32 ks_pcie_am654_read_dbi2(struct dw_pcie *pci, void __iomem *base, + u32 reg, size_t size) +{ + struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); + u32 val; + + ks_pcie_set_dbi_mode(ks_pcie); + dw_pcie_read(base + reg, size, &val); + ks_pcie_clear_dbi_mode(ks_pcie); + return val; +} + +static void ks_pcie_am654_write_dbi2(struct dw_pcie *pci, void __iomem *base, + u32 reg, size_t size, u32 val) +{ + struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); + + ks_pcie_set_dbi_mode(ks_pcie); + dw_pcie_write(base + reg, size, val); + ks_pcie_clear_dbi_mode(ks_pcie); +} + static const struct dw_pcie_ops ks_pcie_dw_pcie_ops = { .start_link = ks_pcie_start_link, .stop_link = ks_pcie_stop_link, .link_up = ks_pcie_link_up, + .read_dbi2 = ks_pcie_am654_read_dbi2, + .write_dbi2 = ks_pcie_am654_write_dbi2, }; +static void ks_pcie_am654_ep_init(struct dw_pcie_ep *ep) +{ + struct dw_pcie *pci = to_dw_pcie_from_ep(ep); + int flags; + + ep->page_size = AM654_WIN_SIZE; + flags = PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_32; + dw_pcie_writel_dbi2(pci, PCI_BASE_ADDRESS_0, APP_ADDR_SPACE_0 - 1); + dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, flags); +} + +static void ks_pcie_am654_raise_legacy_irq(struct keystone_pcie *ks_pcie) +{ + struct dw_pcie *pci = ks_pcie->pci; + u8 int_pin; + + int_pin = dw_pcie_readb_dbi(pci, PCI_INTERRUPT_PIN); + if (int_pin == 0 || int_pin > 4) + return; + + ks_pcie_app_writel(ks_pcie, PCIE_LEGACY_IRQ_ENABLE_SET(int_pin), + INT_ENABLE); + ks_pcie_app_writel(ks_pcie, PCIE_EP_IRQ_SET, INT_ENABLE); + mdelay(1); + ks_pcie_app_writel(ks_pcie, PCIE_EP_IRQ_CLR, INT_ENABLE); + ks_pcie_app_writel(ks_pcie, PCIE_LEGACY_IRQ_ENABLE_CLR(int_pin), + INT_ENABLE); +} + +static int ks_pcie_am654_raise_irq(struct dw_pcie_ep *ep, u8 func_no, + enum pci_epc_irq_type type, + u16 interrupt_num) +{ + struct dw_pcie *pci = to_dw_pcie_from_ep(ep); + struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); + + switch (type) { + case PCI_EPC_IRQ_LEGACY: + ks_pcie_am654_raise_legacy_irq(ks_pcie); + break; + case PCI_EPC_IRQ_MSI: + dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num); + break; + default: + dev_err(pci->dev, "UNKNOWN IRQ type\n"); + return -EINVAL; + } + + return 0; +} + +static const struct pci_epc_features ks_pcie_am654_epc_features = { + .linkup_notifier = false, + .msi_capable = true, + .msix_capable = true, + .reserved_bar = 1 << BAR_0 | 1 << BAR_1, + .bar_fixed_64bit = 1 << BAR_0, + .bar_fixed_size[2] = SZ_1M, + .bar_fixed_size[3] = SZ_64K, + .bar_fixed_size[4] = 256, + .bar_fixed_size[5] = SZ_1M, + .align = SZ_1M, +}; + +static const struct pci_epc_features* +ks_pcie_am654_get_features(struct dw_pcie_ep *ep) +{ + return &ks_pcie_am654_epc_features; +} + +static const struct dw_pcie_ep_ops ks_pcie_am654_ep_ops = { + .ep_init = ks_pcie_am654_ep_init, + .raise_irq = ks_pcie_am654_raise_irq, + .get_features = &ks_pcie_am654_get_features, +}; + +static int __init ks_pcie_add_pcie_ep(struct keystone_pcie *ks_pcie, + struct platform_device *pdev) +{ + int ret; + struct dw_pcie_ep *ep; + struct resource *res; + struct device *dev = &pdev->dev; + struct dw_pcie *pci = ks_pcie->pci; + + ep = &pci->ep; + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space"); + if (!res) + return -EINVAL; + + ep->phys_base = res->start; + ep->addr_size = resource_size(res); + + ret = dw_pcie_ep_init(ep); + if (ret) { + dev_err(dev, "failed to initialize endpoint\n"); + return ret; + } + + return 0; +} + static void ks_pcie_disable_phy(struct keystone_pcie *ks_pcie) { int num_lanes = ks_pcie->num_lanes; @@ -923,7 +1061,8 @@ static int ks_pcie_set_mode(struct device *dev) return 0; } -static int ks_pcie_am654_set_mode(struct device *dev) +static int ks_pcie_am654_set_mode(struct device *dev, + enum dw_pcie_device_mode mode) { struct device_node *np = dev->of_node; struct regmap *syscon; @@ -936,7 +1075,18 @@ static int ks_pcie_am654_set_mode(struct device *dev) return 0; mask = AM654_PCIE_DEV_TYPE_MASK; - val = RC; + + switch (mode) { + case DW_PCIE_RC_TYPE: + val = RC; + break; + case DW_PCIE_EP_TYPE: + val = EP; + break; + default: + dev_err(dev, "INVALID device type %d\n", mode); + return -EINVAL; + } ret = regmap_update_bits(syscon, 0, mask, val); if (ret) { @@ -954,6 +1104,13 @@ static const struct ks_pcie_of_data ks_pcie_rc_of_data = { static const struct ks_pcie_of_data ks_pcie_am654_rc_of_data = { .host_ops = &ks_pcie_am654_host_ops, + .mode = DW_PCIE_RC_TYPE, + .version = 0x490A, +}; + +static const struct ks_pcie_of_data ks_pcie_am654_ep_of_data = { + .ep_ops = &ks_pcie_am654_ep_ops, + .mode = DW_PCIE_EP_TYPE, .version = 0x490A, }; @@ -967,16 +1124,22 @@ static const struct of_device_id ks_pcie_of_match[] = { .data = &ks_pcie_am654_rc_of_data, .compatible = "ti,am654-pcie-rc", }, + { + .data = &ks_pcie_am654_ep_of_data, + .compatible = "ti,am654-pcie-ep", + }, { }, }; static int __init ks_pcie_probe(struct platform_device *pdev) { const struct dw_pcie_host_ops *host_ops; + const struct dw_pcie_ep_ops *ep_ops; struct device *dev = &pdev->dev; struct device_node *np = dev->of_node; const struct ks_pcie_of_data *data; const struct of_device_id *match; + enum dw_pcie_device_mode mode; struct dw_pcie *pci; struct keystone_pcie *ks_pcie; struct device_link **link; @@ -999,6 +1162,8 @@ static int __init ks_pcie_probe(struct platform_device *pdev) version = data->version; host_ops = data->host_ops; + ep_ops = data->ep_ops; + mode = data->mode; ks_pcie = devm_kzalloc(dev, sizeof(*ks_pcie), GFP_KERNEL); if (!ks_pcie) @@ -1021,16 +1186,11 @@ static int __init ks_pcie_probe(struct platform_device *pdev) return PTR_ERR(base); pci->dbi_base = base; + pci->dbi_base2 = base; pci->dev = dev; pci->ops = &ks_pcie_dw_pcie_ops; pci->version = version; - ret = of_property_read_u32(np, "num-viewport", &num_viewport); - if (ret < 0) { - dev_err(dev, "unable to read *num-viewport* property\n"); - return ret; - } - irq = platform_get_irq(pdev, 0); if (irq < 0) { dev_err(dev, "missing IRQ resource: %d\n", irq); @@ -1079,7 +1239,6 @@ static int __init ks_pcie_probe(struct platform_device *pdev) ks_pcie->pci = pci; ks_pcie->link = link; ks_pcie->num_lanes = num_lanes; - ks_pcie->num_viewport = num_viewport; ks_pcie->phy = phy; ret = ks_pcie_enable_phy(ks_pcie); @@ -1106,7 +1265,7 @@ static int __init ks_pcie_probe(struct platform_device *pdev) pci->atu_base = atu_base; - ret = ks_pcie_am654_set_mode(dev); + ret = ks_pcie_am654_set_mode(dev, mode); if (ret < 0) goto err_get_sync; } else { @@ -1115,10 +1274,39 @@ static int __init ks_pcie_probe(struct platform_device *pdev) goto err_get_sync; } - pci->pp.ops = host_ops; - ret = ks_pcie_add_pcie_port(ks_pcie, pdev); - if (ret < 0) - goto err_get_sync; + switch (mode) { + case DW_PCIE_RC_TYPE: + if (!IS_ENABLED(CONFIG_PCI_KEYSTONE_HOST)) { + ret = -ENODEV; + goto err_get_sync; + } + + ret = of_property_read_u32(np, "num-viewport", &num_viewport); + if (ret < 0) { + dev_err(dev, "unable to read *num-viewport* property\n"); + return ret; + } + + ks_pcie->num_viewport = num_viewport; + pci->pp.ops = host_ops; + ret = ks_pcie_add_pcie_port(ks_pcie, pdev); + if (ret < 0) + goto err_get_sync; + break; + case DW_PCIE_EP_TYPE: + if (!IS_ENABLED(CONFIG_PCI_KEYSTONE_EP)) { + ret = -ENODEV; + goto err_get_sync; + } + + pci->ep.ops = ep_ops; + ret = ks_pcie_add_pcie_ep(ks_pcie, pdev); + if (ret < 0) + goto err_get_sync; + break; + default: + dev_err(dev, "INVALID device type %d\n", mode); + } ks_pcie_enable_error_irq(ks_pcie); From patchwork Mon Jan 14 13:24:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 1024518 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="EiD2ok1L"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43dZ5Z3bx5z9sDL for ; Tue, 15 Jan 2019 00:27:29 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726699AbfANN1S (ORCPT ); Mon, 14 Jan 2019 08:27:18 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:37584 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726559AbfANN1R (ORCPT ); Mon, 14 Jan 2019 08:27:17 -0500 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x0EDQc6x098319; Mon, 14 Jan 2019 07:26:38 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1547472398; bh=WBTdWRfYLKWv54dEuesWhlPv+Ca+Oa1+3N9tCdOgMMQ=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=EiD2ok1L6yzy+FmC75cU6k4+yTVtgx09w/7qmefhAVIHquBjNjL85yvF4VQM/RG69 owmV21aQxFDSOw1jfbwF3NzIHgYRrZYzP1+SXZ7COZmWEWznnYpM7bSxwO++APcuVu NjB7RjSCavhu1EofazTRK4/ErdxF6Grh0Qj01iP4= Received: from DLEE109.ent.ti.com (dlee109.ent.ti.com [157.170.170.41]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x0EDQcBO012761 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 14 Jan 2019 07:26:38 -0600 Received: from DLEE114.ent.ti.com (157.170.170.25) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Mon, 14 Jan 2019 07:26:37 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Mon, 14 Jan 2019 07:26:38 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x0EDOoWh028516; Mon, 14 Jan 2019 07:26:33 -0600 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Rob Herring , Lorenzo Pieralisi CC: Kishon Vijay Abraham I , Jingoo Han , Bjorn Helgaas , Mark Rutland , Arnd Bergmann , Greg Kroah-Hartman , Murali Karicheri , Jesper Nilsson , , , , , , Subject: [PATCH 21/24] PCI: designware-ep: Configure RESBAR to advertise the smallest size Date: Mon, 14 Jan 2019 18:54:21 +0530 Message-ID: <20190114132424.6445-22-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190114132424.6445-1-kishon@ti.com> References: <20190114132424.6445-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Configure RESBAR capability to advertise the smallest size (1MB) for couple of reasons. A) Host side resource allocation of BAR fails for larger sizes. B) Endpoint function driver does not allocate memory for all supported sizes in RESBAR capability. If and when there is a usecase required to add more flexibility using RESBAR, this can be revisited. Signed-off-by: Kishon Vijay Abraham I --- .../pci/controller/dwc/pcie-designware-ep.c | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index cd51b008858c..47cc06bac91f 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -502,10 +502,32 @@ void dw_pcie_ep_exit(struct dw_pcie_ep *ep) pci_epc_mem_exit(epc); } +static unsigned int dw_pcie_ep_find_ext_capability(struct dw_pcie *pci, int cap) +{ + u32 header; + int pos = PCI_CFG_SPACE_SIZE; + + while (pos) { + header = dw_pcie_readl_dbi(pci, pos); + if (PCI_EXT_CAP_ID(header) == cap) + return pos; + + pos = PCI_EXT_CAP_NEXT(header); + if (!pos) + break; + } + + return 0; +} + int dw_pcie_ep_init(struct dw_pcie_ep *ep) { + int i; int ret; + u32 reg; void *addr; + unsigned int nbars; + unsigned int offset; struct pci_epc *epc; struct dw_pcie *pci = to_dw_pcie_from_ep(ep); struct device *dev = pci->dev; @@ -589,6 +611,18 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) ep->msix_cap = dw_pcie_ep_find_capability(pci, PCI_CAP_ID_MSIX); + offset = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_REBAR); + if (offset) { + reg = dw_pcie_readl_dbi(pci, offset + PCI_REBAR_CTRL); + nbars = (reg & PCI_REBAR_CTRL_NBAR_MASK) >> + PCI_REBAR_CTRL_NBAR_SHIFT; + + dw_pcie_dbi_ro_wr_en(pci); + for (i = 0; i < nbars; i++, offset += PCI_REBAR_CTRL) + dw_pcie_writel_dbi(pci, offset + PCI_REBAR_CAP, 0x0); + dw_pcie_dbi_ro_wr_dis(pci); + } + dw_pcie_setup(pci); return 0; From patchwork Mon Jan 14 13:24:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 1024522 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="tk77drck"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43dZ642zqRz9s3q for ; Tue, 15 Jan 2019 00:27:56 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726774AbfANN1s (ORCPT ); Mon, 14 Jan 2019 08:27:48 -0500 Received: from lelv0142.ext.ti.com ([198.47.23.249]:41154 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726717AbfANN1r (ORCPT ); Mon, 14 Jan 2019 08:27:47 -0500 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x0EDQh1v041581; Mon, 14 Jan 2019 07:26:43 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1547472403; bh=CF5ivThAeVhsXGcV5WpV6w68ilrQQqK8YE1SR4Z9I10=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=tk77drck6OKnLY9dkDBCKf0sySURytF9x0xxMOPFRCwcQZacNAStG107CmJDsQSmR r9+a5K2+EQ8KCsvpdbW4C/MY0hSXsdSyzqEbAPOAFj0g958OSBIGxdAPUCIUsSc3kt WtPG9Dy6s5YO1Q06AsX4zxT97WE4I625be1FHFCQ= Received: from DFLE100.ent.ti.com (dfle100.ent.ti.com [10.64.6.21]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x0EDQhtG089758 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 14 Jan 2019 07:26:43 -0600 Received: from DFLE113.ent.ti.com (10.64.6.34) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Mon, 14 Jan 2019 07:26:42 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Mon, 14 Jan 2019 07:26:42 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x0EDOoWi028516; Mon, 14 Jan 2019 07:26:38 -0600 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Rob Herring , Lorenzo Pieralisi CC: Kishon Vijay Abraham I , Jingoo Han , Bjorn Helgaas , Mark Rutland , Arnd Bergmann , Greg Kroah-Hartman , Murali Karicheri , Jesper Nilsson , , , , , , Subject: [PATCH 22/24] PCI: designware-ep: Use aligned ATU window for raising MSI interrupts Date: Mon, 14 Jan 2019 18:54:22 +0530 Message-ID: <20190114132424.6445-23-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190114132424.6445-1-kishon@ti.com> References: <20190114132424.6445-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Certain platforms like K2G reguires the outbound ATU window to be aligned. The alignment size is already present in mem->page_size. Use the alignment size present in mem->page_size to configre a aligned ATU window. In order to raise an interrupt, CPU has to write to address offset from the start of the window unlike before where writes were always to the beginning of the ATU window. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pcie-designware-ep.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index 47cc06bac91f..f557e83bc34c 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -397,6 +397,7 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no, { struct dw_pcie *pci = to_dw_pcie_from_ep(ep); struct pci_epc *epc = ep->epc; + unsigned int aligned_offset; u16 msg_ctrl, msg_data; u32 msg_addr_lower, msg_addr_upper, reg; u64 msg_addr; @@ -422,13 +423,15 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no, reg = ep->msi_cap + PCI_MSI_DATA_32; msg_data = dw_pcie_readw_dbi(pci, reg); } - msg_addr = ((u64) msg_addr_upper) << 32 | msg_addr_lower; + aligned_offset = msg_addr_lower & (epc->mem->page_size - 1); + msg_addr = ((u64)msg_addr_upper) << 32 | + (msg_addr_lower & ~aligned_offset); ret = dw_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys, msg_addr, epc->mem->page_size); if (ret) return ret; - writel(msg_data | (interrupt_num - 1), ep->msi_mem); + writel(msg_data | (interrupt_num - 1), ep->msi_mem + aligned_offset); dw_pcie_ep_unmap_addr(epc, func_no, ep->msi_mem_phys); From patchwork Mon Jan 14 13:24:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 1024523 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="hFhA8QE8"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43dZ6D50Kzz9sD4 for ; Tue, 15 Jan 2019 00:28:04 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726771AbfANN14 (ORCPT ); Mon, 14 Jan 2019 08:27:56 -0500 Received: from lelv0143.ext.ti.com ([198.47.23.248]:41344 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726717AbfANN1z (ORCPT ); Mon, 14 Jan 2019 08:27:55 -0500 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x0EDQmWa019648; Mon, 14 Jan 2019 07:26:48 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1547472408; bh=0PiaQYnV59ccfwEhn8gPR5j82jBP2sS0jMXzDzaA8TY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=hFhA8QE82uMeSb5OF7qMlUx6XubeLPJNUbOTu8pcgaQaL98xcm7YrnF8fMnDsopih 7trFXBk+ZF6gKvoVgNkgxThAyfJOGvhWTOXhA+L2cb8LCuqsAyoBQnprtQsrnsGoCv mUKcD/laa7eRygEsk9MHJAKduAPXVkBzQRUa1WBg= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x0EDQmfb095069 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 14 Jan 2019 07:26:48 -0600 Received: from DFLE101.ent.ti.com (10.64.6.22) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Mon, 14 Jan 2019 07:26:46 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Mon, 14 Jan 2019 07:26:47 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x0EDOoWj028516; Mon, 14 Jan 2019 07:26:43 -0600 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Rob Herring , Lorenzo Pieralisi CC: Kishon Vijay Abraham I , Jingoo Han , Bjorn Helgaas , Mark Rutland , Arnd Bergmann , Greg Kroah-Hartman , Murali Karicheri , Jesper Nilsson , , , , , , Subject: [PATCH 23/24] misc: pci_endpoint_test: Add support to test PCI EP in AM654x Date: Mon, 14 Jan 2019 18:54:23 +0530 Message-ID: <20190114132424.6445-24-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190114132424.6445-1-kishon@ti.com> References: <20190114132424.6445-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org TI's AM654x PCIe EP has a restriction that BAR_0 is mapped to application registers. "PCIe Inbound Address Translation" section in AM65x Sitara Processors TRM (SPRUID7 – April 2018) describes BAR0 is reserved. Configure pci_endpoint_test to use BAR_2 instead. Also set alignment to 64K since "PCIe Subsystem Address Translation" section in TRM indicates minimum ATU window size is 64K. Signed-off-by: Kishon Vijay Abraham I --- drivers/misc/pci_endpoint_test.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c index 896e2df9400f..6dfaeeaeec0a 100644 --- a/drivers/misc/pci_endpoint_test.c +++ b/drivers/misc/pci_endpoint_test.c @@ -75,6 +75,11 @@ #define PCI_ENDPOINT_TEST_IRQ_TYPE 0x24 #define PCI_ENDPOINT_TEST_IRQ_NUMBER 0x28 +#define PCI_DEVICE_ID_TI_AM654 0xb00c + +#define is_am654_pci_dev(pdev) \ + ((pdev)->device == PCI_DEVICE_ID_TI_AM654) + static DEFINE_IDA(pci_endpoint_test_ida); #define to_endpoint_test(priv) container_of((priv), struct pci_endpoint_test, \ @@ -588,6 +593,7 @@ static long pci_endpoint_test_ioctl(struct file *file, unsigned int cmd, int ret = -EINVAL; enum pci_barno bar; struct pci_endpoint_test *test = to_endpoint_test(file->private_data); + struct pci_dev *pdev = test->pdev; mutex_lock(&test->mutex); switch (cmd) { @@ -595,6 +601,8 @@ static long pci_endpoint_test_ioctl(struct file *file, unsigned int cmd, bar = arg; if (bar < 0 || bar > 5) goto ret; + if (is_am654_pci_dev(pdev) && bar == BAR_0) + goto ret; ret = pci_endpoint_test_bar(test, bar); break; case PCITEST_LEGACY_IRQ: @@ -785,10 +793,18 @@ static void pci_endpoint_test_remove(struct pci_dev *pdev) pci_disable_device(pdev); } +static const struct pci_endpoint_test_data am654_data = { + .test_reg_bar = BAR_2, + .alignment = SZ_64K, +}; + static const struct pci_device_id pci_endpoint_test_tbl[] = { { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA74x) }, { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA72x) }, { PCI_DEVICE(PCI_VENDOR_ID_SYNOPSYS, 0xedda) }, + { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_AM654), + .driver_data = (kernel_ulong_t)&am654_data + }, { } }; MODULE_DEVICE_TABLE(pci, pci_endpoint_test_tbl); From patchwork Mon Jan 14 13:24:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 1024519 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="x62GVg5Y"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43dZ5c3CXNz9sBZ for ; Tue, 15 Jan 2019 00:27:32 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726731AbfANN1R (ORCPT ); Mon, 14 Jan 2019 08:27:17 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:37566 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726680AbfANN1N (ORCPT ); Mon, 14 Jan 2019 08:27:13 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x0EDQqpT098392; Mon, 14 Jan 2019 07:26:52 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1547472412; bh=yRUr73ZiS5aNXYVmbXRtJ0JSqktNkC+89EIMn+yRODs=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=x62GVg5YvVaKS6/uQKvz32FziutO1EpLH1sHg6A/rpxXMq3mevZ1inmhKQVsln9/T zFWfOSPhII8wq3ipSpFNcWpkF1tuA5CniQ+QisLkL2tmYtu7bfsoCLQSabBooIlHQc Hw2bPkVvwVqx8Aq3vY5VNoXGdx96oEqWf/bcJGJQ= Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x0EDQqKK057603 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 14 Jan 2019 07:26:52 -0600 Received: from DFLE104.ent.ti.com (10.64.6.25) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Mon, 14 Jan 2019 07:26:52 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Mon, 14 Jan 2019 07:26:51 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x0EDOoWk028516; Mon, 14 Jan 2019 07:26:48 -0600 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Rob Herring , Lorenzo Pieralisi CC: Kishon Vijay Abraham I , Jingoo Han , Bjorn Helgaas , Mark Rutland , Arnd Bergmann , Greg Kroah-Hartman , Murali Karicheri , Jesper Nilsson , , , , , , Subject: [PATCH 24/24] misc: pci_endpoint_test: Fix test_reg_bar to be updated in pci_endpoint_test Date: Mon, 14 Jan 2019 18:54:24 +0530 Message-ID: <20190114132424.6445-25-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190114132424.6445-1-kishon@ti.com> References: <20190114132424.6445-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org commit 834b9051992580ac8fd3966d023b ("misc: pci_endpoint_test: Add support for PCI_ENDPOINT_TEST regs to be mapped to any BAR") while adding test_reg_bar in order to map PCI_ENDPOINT_TEST regs to be mapped to any BAR failed to update test_reg_bar in pci_endpoint_test. This results in test_reg_bar having invalid value when used outside probe. Fix it here. Fixes: 834b9051992580ac8fd3966d023b ("misc: pci_endpoint_test: Add support for PCI_ENDPOINT_TEST regs to be mapped to any BAR") Signed-off-by: Kishon Vijay Abraham I --- drivers/misc/pci_endpoint_test.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c index 6dfaeeaeec0a..46788fe854e4 100644 --- a/drivers/misc/pci_endpoint_test.c +++ b/drivers/misc/pci_endpoint_test.c @@ -670,6 +670,7 @@ static int pci_endpoint_test_probe(struct pci_dev *pdev, data = (struct pci_endpoint_test_data *)ent->driver_data; if (data) { test_reg_bar = data->test_reg_bar; + test->test_reg_bar = test_reg_bar; test->alignment = data->alignment; irq_type = data->irq_type; }