From patchwork Tue Jan 8 16:24:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 1022011 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=bootlin.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43YyLh6CBzz9sNB for ; Wed, 9 Jan 2019 03:26:20 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729290AbfAHQ0N (ORCPT ); Tue, 8 Jan 2019 11:26:13 -0500 Received: from mail.bootlin.com ([62.4.15.54]:44836 "EHLO mail.bootlin.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728238AbfAHQYs (ORCPT ); Tue, 8 Jan 2019 11:24:48 -0500 Received: by mail.bootlin.com (Postfix, from userid 110) id 68648209EF; Tue, 8 Jan 2019 17:24:45 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on mail.bootlin.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT shortcircuit=ham autolearn=disabled version=3.4.2 Received: from localhost.localdomain (aaubervilliers-681-1-45-241.w90-88.abo.wanadoo.fr [90.88.163.241]) by mail.bootlin.com (Postfix) with ESMTPSA id 08E24209C2; Tue, 8 Jan 2019 17:24:45 +0100 (CET) From: Miquel Raynal To: Gregory Clement , Jason Cooper , Andrew Lunn , Sebastian Hesselbarth , Thomas Petazzoni , Bjorn Helgaas Cc: , Rob Herring , Mark Rutland , Lorenzo Pieralisi , linux-pci@vger.kernel.org, , , Antoine Tenart , Maxime Chevallier , Nadav Haklai , Miquel Raynal Subject: [PATCH v3 01/15] PCI: aardvark: Enlarge PIO timeout Date: Tue, 8 Jan 2019 17:24:26 +0100 Message-Id: <20190108162441.5278-2-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190108162441.5278-1-miquel.raynal@bootlin.com> References: <20190108162441.5278-1-miquel.raynal@bootlin.com> MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org This delay has been proven to work until now, however, there is a reproducible way to fail the driver probe because of it. Adding the support for the PCIe gated peripheral clock that feeds the Aardvark IP defers the Aardvark driver probe at boot time. The probe functions calls pci_host_probe() at its end. This is where the timeout (sometimes) resides, leading to a kernel panic the next time a register is accessed. Here is the function call sequence: advk_pcie_probe() pci_host_probe() pci_scan_root_bus_bridge() pci_scan_child_bus_extend() pci_scan_bridge_extend() pci_scan_child_bus_extend() pci_scan_slot() pcie_aspm_init_link_state() pcie_aspm_cap_init() pcie_aspm_cap_init() is in charge of doing the initial ASPM state setup (PCIe Active-State Power Management). The logic at the top of the function is: 1/ Read upstream and downstream components' register state. 2/ Configure the common clock before checking latencies. 3/ Read again upstream and downstream component's register state. 4/ ... Experimentation shows that while 1/ always work, 3/ sometimes timeouts when reading the downstream components' register state. Each read operation is handled by the following sequence: pcie_capability_read_dword() pci_bus_read_config_dword() advk_pcie_rd_conf() advk_pcie_rd_conf() just configures a few registers and polls on the ISR bit before reading the value that has been retrieved through the interconnect. The polling timeout of the ISR bit is set to 1ms. While this value seems to fit most of the situations, in our case it is sometimes crossed when reading PCI_EXP_LNKCAP (PCI link capacities) from the downstream component. It has been measured that most of the time that the read lasts longer than 1ms, it rises ~24ms. In my tests, using twice this delay always works. The root cause and the reason why the timeout only appearing when the probe is delayed is unknown though. Signed-off-by: Miquel Raynal --- drivers/pci/controller/pci-aardvark.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index 750081c1cb48..18120e312ae1 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -175,7 +175,7 @@ (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \ PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where)) -#define PIO_TIMEOUT_MS 1 +#define PIO_TIMEOUT_MS 50 #define LINK_WAIT_MAX_RETRIES 10 #define LINK_WAIT_USLEEP_MIN 90000 From patchwork Tue Jan 8 16:24:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 1022010 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=bootlin.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43YyLZ4mmhz9sND for ; Wed, 9 Jan 2019 03:26:14 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729614AbfAHQ0H (ORCPT ); Tue, 8 Jan 2019 11:26:07 -0500 Received: from mail.bootlin.com ([62.4.15.54]:44849 "EHLO mail.bootlin.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728853AbfAHQYs (ORCPT ); Tue, 8 Jan 2019 11:24:48 -0500 Received: by mail.bootlin.com (Postfix, from userid 110) id C15AD20A08; Tue, 8 Jan 2019 17:24:45 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on mail.bootlin.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT, URIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.2 Received: from localhost.localdomain (aaubervilliers-681-1-45-241.w90-88.abo.wanadoo.fr [90.88.163.241]) by mail.bootlin.com (Postfix) with ESMTPSA id 608AB207A3; Tue, 8 Jan 2019 17:24:45 +0100 (CET) From: Miquel Raynal To: Gregory Clement , Jason Cooper , Andrew Lunn , Sebastian Hesselbarth , Thomas Petazzoni , Bjorn Helgaas Cc: , Rob Herring , Mark Rutland , Lorenzo Pieralisi , linux-pci@vger.kernel.org, , , Antoine Tenart , Maxime Chevallier , Nadav Haklai , Miquel Raynal Subject: [PATCH v3 02/15] PCI: aardvark: Configure more registers in the configuration helper Date: Tue, 8 Jan 2019 17:24:27 +0100 Message-Id: <20190108162441.5278-3-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190108162441.5278-1-miquel.raynal@bootlin.com> References: <20190108162441.5278-1-miquel.raynal@bootlin.com> MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Mimic U-Boot configuration to be sure all hardware registers are set properly. This will be needed for future S2RAM operation. Signed-off-by: Miquel Raynal --- drivers/pci/controller/pci-aardvark.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index 18120e312ae1..0f50163ae072 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -100,6 +100,8 @@ #define PCIE_CORE_CTRL2_STRICT_ORDER_ENABLE BIT(5) #define PCIE_CORE_CTRL2_OB_WIN_ENABLE BIT(6) #define PCIE_CORE_CTRL2_MSI_ENABLE BIT(10) +#define PCIE_PHY_REFCLK (CONTROL_BASE_ADDR + 0x14) +#define PCIE_PHY_REFCLK_BUF_CTRL 0x1342 #define PCIE_MSG_LOG_REG (CONTROL_BASE_ADDR + 0x30) #define PCIE_ISR0_REG (CONTROL_BASE_ADDR + 0x40) #define PCIE_MSG_PM_PME_MASK BIT(7) @@ -243,6 +245,9 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie) { u32 reg; + /* Set HW Reference Clock Buffer Control */ + advk_writel(pcie, PCIE_PHY_REFCLK_BUF_CTRL, PCIE_PHY_REFCLK); + /* Set to Direct mode */ reg = advk_readl(pcie, CTRL_CONFIG_REG); reg &= ~(CTRL_MODE_MASK << CTRL_MODE_SHIFT); @@ -274,6 +279,15 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie) PCIE_CORE_CTRL2_TD_ENABLE; advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); + /* Set PCIe Device Control and Status 1 PF0 register */ + reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE | + PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE; + advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG); + + /* Program PCIe Control 2 to disable strict ordering */ + reg = PCIE_CORE_CTRL2_RESERVED | PCIE_CORE_CTRL2_TD_ENABLE; + advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); + /* Set GEN2 */ reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); reg &= ~PCIE_GEN_SEL_MSK; From patchwork Tue Jan 8 16:24:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 1022008 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=bootlin.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43YyLJ4wRwz9sCr for ; Wed, 9 Jan 2019 03:26:00 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729300AbfAHQYt (ORCPT ); Tue, 8 Jan 2019 11:24:49 -0500 Received: from mail.bootlin.com ([62.4.15.54]:44858 "EHLO mail.bootlin.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729107AbfAHQYs (ORCPT ); Tue, 8 Jan 2019 11:24:48 -0500 Received: by mail.bootlin.com (Postfix, from userid 110) id 21D5B20A0D; Tue, 8 Jan 2019 17:24:46 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on mail.bootlin.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT, URIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.2 Received: from localhost.localdomain (aaubervilliers-681-1-45-241.w90-88.abo.wanadoo.fr [90.88.163.241]) by mail.bootlin.com (Postfix) with ESMTPSA id BAA02209C2; Tue, 8 Jan 2019 17:24:45 +0100 (CET) From: Miquel Raynal To: Gregory Clement , Jason Cooper , Andrew Lunn , Sebastian Hesselbarth , Thomas Petazzoni , Bjorn Helgaas Cc: , Rob Herring , Mark Rutland , Lorenzo Pieralisi , linux-pci@vger.kernel.org, , , Antoine Tenart , Maxime Chevallier , Nadav Haklai , Miquel Raynal Subject: [PATCH v3 03/15] PCI: aardvark: Add clock support Date: Tue, 8 Jan 2019 17:24:28 +0100 Message-Id: <20190108162441.5278-4-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190108162441.5278-1-miquel.raynal@bootlin.com> References: <20190108162441.5278-1-miquel.raynal@bootlin.com> MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The IP relies on a gated clock. When we will add S2RAM support, this clock will need to be resumed before any PCIe registers are accessed. Add support for this clock. Signed-off-by: Miquel Raynal --- drivers/pci/controller/pci-aardvark.c | 29 +++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index 0f50163ae072..b1b8897d2d28 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -8,6 +8,7 @@ * Author: Hezi Shahmoon */ +#include #include #include #include @@ -187,6 +188,7 @@ struct advk_pcie { struct platform_device *pdev; + struct clk *clk; void __iomem *base; struct list_head resources; struct irq_domain *irq_domain; @@ -973,6 +975,29 @@ static int advk_pcie_parse_request_of_pci_ranges(struct advk_pcie *pcie) return err; } +static int advk_pcie_setup_clk(struct advk_pcie *pcie) +{ + struct device *dev = &pcie->pdev->dev; + int ret; + + pcie->clk = devm_clk_get(dev, NULL); + if (IS_ERR(pcie->clk) && (PTR_ERR(pcie->clk) == -EPROBE_DEFER)) + return PTR_ERR(pcie->clk); + + /* Old bindings miss the clock handle */ + if (IS_ERR(pcie->clk)) { + dev_warn(dev, "Clock unavailable (%ld)\n", PTR_ERR(pcie->clk)); + pcie->clk = NULL; + return 0; + } + + ret = clk_prepare_enable(pcie->clk); + if (ret) + dev_err(dev, "Clock initialization failed (%d)\n", ret); + + return ret; +} + static int advk_pcie_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -1008,6 +1033,10 @@ static int advk_pcie_probe(struct platform_device *pdev) return ret; } + ret = advk_pcie_setup_clk(pcie); + if (ret) + return ret; + advk_pcie_setup_hw(pcie); advk_sw_pci_bridge_init(pcie); From patchwork Tue Jan 8 16:24:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 1022009 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=bootlin.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43YyLK52Rsz9sN8 for ; Wed, 9 Jan 2019 03:26:01 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729597AbfAHQ0A (ORCPT ); Tue, 8 Jan 2019 11:26:00 -0500 Received: from mail.bootlin.com ([62.4.15.54]:44868 "EHLO mail.bootlin.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729157AbfAHQYs (ORCPT ); Tue, 8 Jan 2019 11:24:48 -0500 Received: by mail.bootlin.com (Postfix, from userid 110) id 760FC20A11; Tue, 8 Jan 2019 17:24:46 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on mail.bootlin.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT, URIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.2 Received: from localhost.localdomain (aaubervilliers-681-1-45-241.w90-88.abo.wanadoo.fr [90.88.163.241]) by mail.bootlin.com (Postfix) with ESMTPSA id 1DA7C207A3; Tue, 8 Jan 2019 17:24:46 +0100 (CET) From: Miquel Raynal To: Gregory Clement , Jason Cooper , Andrew Lunn , Sebastian Hesselbarth , Thomas Petazzoni , Bjorn Helgaas Cc: , Rob Herring , Mark Rutland , Lorenzo Pieralisi , linux-pci@vger.kernel.org, , , Antoine Tenart , Maxime Chevallier , Nadav Haklai , Miquel Raynal Subject: [PATCH v3 04/15] PCI: aardvark: Add PHY support Date: Tue, 8 Jan 2019 17:24:29 +0100 Message-Id: <20190108162441.5278-5-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190108162441.5278-1-miquel.raynal@bootlin.com> References: <20190108162441.5278-1-miquel.raynal@bootlin.com> MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The IP needs its PHY to be properly configured to work. While the PHY is usually already configured by the bootloader, we will need this feature when adding S2RAM support. Take care of registering and configuring the PHY from the driver itself. Suggested-by: Grzegorz Jaszczyk Signed-off-by: Miquel Raynal --- drivers/pci/controller/pci-aardvark.c | 62 +++++++++++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index b1b8897d2d28..27ec79defa57 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include @@ -203,6 +204,7 @@ struct advk_pcie { u16 msi_msg; int root_bus_nr; struct pci_bridge_emul bridge; + struct phy *phy; }; static inline void advk_writel(struct advk_pcie *pcie, u32 val, u64 reg) @@ -998,6 +1000,62 @@ static int advk_pcie_setup_clk(struct advk_pcie *pcie) return ret; } +static void __maybe_unused advk_pcie_disable_phy(struct advk_pcie *pcie) +{ + phy_power_off(pcie->phy); + phy_exit(pcie->phy); +} + +static int advk_pcie_enable_phy(struct advk_pcie *pcie) +{ + int ret; + + if (!pcie->phy) + return 0; + + ret = phy_init(pcie->phy); + if (ret) + return ret; + + ret = phy_set_mode(pcie->phy, PHY_MODE_PCIE); + if (ret) { + phy_exit(pcie->phy); + return ret; + } + + ret = phy_power_on(pcie->phy); + if (ret) { + phy_exit(pcie->phy); + return ret; + } + + return 0; +} + +static int advk_pcie_setup_phy(struct advk_pcie *pcie) +{ + struct device *dev = &pcie->pdev->dev; + struct device_node *node = dev->of_node; + int ret = 0; + + pcie->phy = devm_of_phy_get(dev, node, NULL); + if (IS_ERR(pcie->phy) && (PTR_ERR(pcie->phy) == -EPROBE_DEFER)) + return PTR_ERR(pcie->phy); + + /* Old bindings miss the PHY handle */ + if (IS_ERR(pcie->phy)) { + dev_warn(dev, "PHY unavailable (%ld)\n", PTR_ERR(pcie->phy)); + pcie->phy = NULL; + return 0; + } + + ret = advk_pcie_enable_phy(pcie); + if (ret) + dev_err(dev, "Failed to initialize PHY (%d)\n", ret); + + return ret; +} + static int advk_pcie_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -1037,6 +1095,10 @@ static int advk_pcie_probe(struct platform_device *pdev) if (ret) return ret; + ret = advk_pcie_setup_phy(pcie); + if (ret) + return ret; + advk_pcie_setup_hw(pcie); advk_sw_pci_bridge_init(pcie); From patchwork Tue Jan 8 16:24:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 1021999 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=bootlin.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43YyKm1YQXz9sCr for ; Wed, 9 Jan 2019 03:25:32 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729381AbfAHQYu (ORCPT ); Tue, 8 Jan 2019 11:24:50 -0500 Received: from mail.bootlin.com ([62.4.15.54]:44884 "EHLO mail.bootlin.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728211AbfAHQYu (ORCPT ); Tue, 8 Jan 2019 11:24:50 -0500 Received: by mail.bootlin.com (Postfix, from userid 110) id CFCE720A13; Tue, 8 Jan 2019 17:24:46 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on mail.bootlin.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT, URIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.2 Received: from localhost.localdomain (aaubervilliers-681-1-45-241.w90-88.abo.wanadoo.fr [90.88.163.241]) by mail.bootlin.com (Postfix) with ESMTPSA id 74101209C2; Tue, 8 Jan 2019 17:24:46 +0100 (CET) From: Miquel Raynal To: Gregory Clement , Jason Cooper , Andrew Lunn , Sebastian Hesselbarth , Thomas Petazzoni , Bjorn Helgaas Cc: , Rob Herring , Mark Rutland , Lorenzo Pieralisi , linux-pci@vger.kernel.org, , , Antoine Tenart , Maxime Chevallier , Nadav Haklai , Miquel Raynal Subject: [PATCH v3 05/15] PCI: aardvark: Add PCIe warm reset support Date: Tue, 8 Jan 2019 17:24:30 +0100 Message-Id: <20190108162441.5278-6-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190108162441.5278-1-miquel.raynal@bootlin.com> References: <20190108162441.5278-1-miquel.raynal@bootlin.com> MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Make use of the 'warm reset' register to ensure every peace of hardware (core, phy, endpoint card) are in a known state before doing the hardware setup. The Aardvark IP can trigger a reset signal upon hot reset or link failure that will only reach the components on the board without affecting the entire device (eg. only the endpoint card). This line is multiplexed on MPPs so if it is not used as PCI reset and multiplexed for instance as a GPIO, the signals produced by the PCIe IP during the warm reset operation won't affect the state of the line. As usual, hardware designers can implement a card reset wired to a GPIO. Support for such reset GPIO will be added in another patch. Signed-off-by: Miquel Raynal --- drivers/pci/controller/pci-aardvark.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index 27ec79defa57..cfe48e553bca 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -139,6 +139,10 @@ #define CTRL_MODE_MASK 0x1 #define PCIE_CORE_MODE_DIRECT 0x0 #define PCIE_CORE_MODE_COMMAND 0x1 +#define CTRL_WARM_RESET_REG (CTRL_CORE_BASE_ADDR + 0x4) +#define CTRL_PCIE_CORE_WARM_RESET BIT(0) +#define CTRL_PHY_CORE_WARM_RESET BIT(1) +#define CTRL_PERSTN_GPIO_EN BIT(3) /* PCIe Central Interrupts Registers */ #define CENTRAL_INT_BASE_ADDR 0x1b000 @@ -249,6 +253,19 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie) { u32 reg; + /* Warm reset */ + reg = advk_readl(pcie, CTRL_WARM_RESET_REG); + reg |= CTRL_PCIE_CORE_WARM_RESET | CTRL_PHY_CORE_WARM_RESET | + CTRL_PERSTN_GPIO_EN; + advk_writel(pcie, reg, CTRL_WARM_RESET_REG); + reg = advk_readl(pcie, CTRL_WARM_RESET_REG); + mdelay(1); + reg &= ~(CTRL_PCIE_CORE_WARM_RESET | CTRL_PHY_CORE_WARM_RESET | + CTRL_PERSTN_GPIO_EN); + advk_writel(pcie, reg, CTRL_WARM_RESET_REG); + reg = advk_readl(pcie, CTRL_WARM_RESET_REG); + mdelay(10); + /* Set HW Reference Clock Buffer Control */ advk_writel(pcie, PCIE_PHY_REFCLK_BUF_CTRL, PCIE_PHY_REFCLK); From patchwork Tue Jan 8 16:24:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 1022002 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=bootlin.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43YyKt5wk2z9sN8 for ; Wed, 9 Jan 2019 03:25:38 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729365AbfAHQYu (ORCPT ); Tue, 8 Jan 2019 11:24:50 -0500 Received: from mail.bootlin.com ([62.4.15.54]:44886 "EHLO mail.bootlin.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729284AbfAHQYu (ORCPT ); Tue, 8 Jan 2019 11:24:50 -0500 Received: by mail.bootlin.com (Postfix, from userid 110) id 36B2920A14; Tue, 8 Jan 2019 17:24:47 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on mail.bootlin.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT, URIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.2 Received: from localhost.localdomain (aaubervilliers-681-1-45-241.w90-88.abo.wanadoo.fr [90.88.163.241]) by mail.bootlin.com (Postfix) with ESMTPSA id CAFB6207A3; Tue, 8 Jan 2019 17:24:46 +0100 (CET) From: Miquel Raynal To: Gregory Clement , Jason Cooper , Andrew Lunn , Sebastian Hesselbarth , Thomas Petazzoni , Bjorn Helgaas Cc: , Rob Herring , Mark Rutland , Lorenzo Pieralisi , linux-pci@vger.kernel.org, , , Antoine Tenart , Maxime Chevallier , Nadav Haklai , Miquel Raynal Subject: [PATCH v3 06/15] PCI: aardvark: Add external reset GPIO support Date: Tue, 8 Jan 2019 17:24:31 +0100 Message-Id: <20190108162441.5278-7-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190108162441.5278-1-miquel.raynal@bootlin.com> References: <20190108162441.5278-1-miquel.raynal@bootlin.com> MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add support for a possible external reset GPIO wired to the PCIe endpoint card. Asserting/deasserting the reset line is done during the warm reset because the warm reset operation already triggers the internal reset line that may also reset the endpoint card (if muxed). Signed-off-by: Miquel Raynal --- drivers/pci/controller/pci-aardvark.c | 50 +++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index cfe48e553bca..3fb14e37eb59 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -10,6 +10,7 @@ #include #include +#include #include #include #include @@ -19,6 +20,7 @@ #include #include #include +#include #include #include "../pci.h" @@ -209,6 +211,7 @@ struct advk_pcie { int root_bus_nr; struct pci_bridge_emul bridge; struct phy *phy; + struct gpio_desc *reset_gpio; }; static inline void advk_writel(struct advk_pcie *pcie, u32 val, u64 reg) @@ -249,6 +252,12 @@ static int advk_pcie_wait_for_link(struct advk_pcie *pcie) return -ETIMEDOUT; } +static void advk_pcie_card_reset_assert(struct advk_pcie *pcie, bool status) +{ + if (pcie->reset_gpio) + gpiod_set_value_cansleep(pcie->reset_gpio, status); +} + static void advk_pcie_setup_hw(struct advk_pcie *pcie) { u32 reg; @@ -257,11 +266,13 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie) reg = advk_readl(pcie, CTRL_WARM_RESET_REG); reg |= CTRL_PCIE_CORE_WARM_RESET | CTRL_PHY_CORE_WARM_RESET | CTRL_PERSTN_GPIO_EN; + advk_pcie_card_reset_assert(pcie, 1); advk_writel(pcie, reg, CTRL_WARM_RESET_REG); reg = advk_readl(pcie, CTRL_WARM_RESET_REG); mdelay(1); reg &= ~(CTRL_PCIE_CORE_WARM_RESET | CTRL_PHY_CORE_WARM_RESET | CTRL_PERSTN_GPIO_EN); + advk_pcie_card_reset_assert(pcie, 0); advk_writel(pcie, reg, CTRL_WARM_RESET_REG); reg = advk_readl(pcie, CTRL_WARM_RESET_REG); mdelay(10); @@ -1073,6 +1084,41 @@ static int advk_pcie_setup_phy(struct advk_pcie *pcie) return ret; } +static int advk_pcie_setup_reset_gpio(struct advk_pcie *pcie) +{ + struct device *dev = &pcie->pdev->dev; + enum of_gpio_flags of_flags; + unsigned long gpio_flags; + int gpio_nb; + int ret; + + gpio_nb = of_get_named_gpio_flags(dev->of_node, "reset-gpios", 0, + &of_flags); + if (gpio_nb == -EPROBE_DEFER) + return gpio_nb; + + /* No all boards use an external GPIO for card reset */ + if (!gpio_is_valid(gpio_nb)) + return 0; + + if (of_flags & OF_GPIO_ACTIVE_LOW) + gpio_flags = GPIOF_ACTIVE_LOW | + GPIOF_OUT_INIT_LOW; + else + gpio_flags = GPIOF_OUT_INIT_HIGH; + + ret = devm_gpio_request_one(dev, gpio_nb, gpio_flags, + "pcie-aardvark-card-reset"); + if (ret) { + dev_err(dev, "Failed to retrieve reset GPIO (%d)\n", ret); + return ret; + } + + pcie->reset_gpio = gpio_to_desc(gpio_nb); + + return 0; +} + static int advk_pcie_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -1116,6 +1162,10 @@ static int advk_pcie_probe(struct platform_device *pdev) if (ret) return ret; + ret = advk_pcie_setup_reset_gpio(pcie); + if (ret) + return ret; + advk_pcie_setup_hw(pcie); advk_sw_pci_bridge_init(pcie); From patchwork Tue Jan 8 16:24:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 1022005 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=bootlin.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43YyL73rYDz9sN8 for ; Wed, 9 Jan 2019 03:25:51 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729555AbfAHQZo (ORCPT ); Tue, 8 Jan 2019 11:25:44 -0500 Received: from mail.bootlin.com ([62.4.15.54]:44893 "EHLO mail.bootlin.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729288AbfAHQYu (ORCPT ); Tue, 8 Jan 2019 11:24:50 -0500 Received: by mail.bootlin.com (Postfix, from userid 110) id 8E83B20A16; Tue, 8 Jan 2019 17:24:47 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on mail.bootlin.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT, URIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.2 Received: from localhost.localdomain (aaubervilliers-681-1-45-241.w90-88.abo.wanadoo.fr [90.88.163.241]) by mail.bootlin.com (Postfix) with ESMTPSA id 2E93E209C2; Tue, 8 Jan 2019 17:24:47 +0100 (CET) From: Miquel Raynal To: Gregory Clement , Jason Cooper , Andrew Lunn , Sebastian Hesselbarth , Thomas Petazzoni , Bjorn Helgaas Cc: , Rob Herring , Mark Rutland , Lorenzo Pieralisi , linux-pci@vger.kernel.org, , , Antoine Tenart , Maxime Chevallier , Nadav Haklai , Miquel Raynal Subject: [PATCH v3 07/15] PCI: aardvark: Add suspend to RAM support Date: Tue, 8 Jan 2019 17:24:32 +0100 Message-Id: <20190108162441.5278-8-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190108162441.5278-1-miquel.raynal@bootlin.com> References: <20190108162441.5278-1-miquel.raynal@bootlin.com> MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add suspend and resume callbacks. The priority of these are "_noirq()", to workaround early access to the registers done by the PCI core through the ->read()/->write() callbacks at resume time. Signed-off-by: Miquel Raynal --- drivers/pci/controller/pci-aardvark.c | 45 ++++++++++++++++++++++++++- 1 file changed, 44 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index 3fb14e37eb59..999bbe27761a 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -1028,7 +1028,7 @@ static int advk_pcie_setup_clk(struct advk_pcie *pcie) return ret; } -static void __maybe_unused advk_pcie_disable_phy(struct advk_pcie *pcie) +static void advk_pcie_disable_phy(struct advk_pcie *pcie) { phy_power_off(pcie->phy); phy_exit(pcie->phy); @@ -1119,6 +1119,47 @@ static int advk_pcie_setup_reset_gpio(struct advk_pcie *pcie) return 0; } +static int __maybe_unused advk_pcie_suspend(struct device *dev) +{ + struct advk_pcie *pcie = dev_get_drvdata(dev); + + advk_pcie_disable_phy(pcie); + + clk_disable_unprepare(pcie->clk); + + return 0; +} + +static int __maybe_unused advk_pcie_resume(struct device *dev) +{ + struct advk_pcie *pcie = dev_get_drvdata(dev); + int ret; + + ret = clk_prepare_enable(pcie->clk); + if (ret) + return ret; + + ret = advk_pcie_enable_phy(pcie); + if (ret) + return ret; + + advk_pcie_setup_hw(pcie); + + advk_sw_pci_bridge_init(pcie); + + return 0; +} + +/* + * The PCI core will try to reconfigure the bus quite early in the resume path. + * We must use the _noirq() alternatives to ensure the controller is ready when + * the core uses the ->read()/->write() callbacks. + */ +static const struct dev_pm_ops advk_pcie_dev_pm_ops = { + SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(advk_pcie_suspend, + advk_pcie_resume) +}; + static int advk_pcie_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -1133,6 +1174,7 @@ static int advk_pcie_probe(struct platform_device *pdev) pcie = pci_host_bridge_priv(bridge); pcie->pdev = pdev; + platform_set_drvdata(pdev, pcie); res = platform_get_resource(pdev, IORESOURCE_MEM, 0); pcie->base = devm_ioremap_resource(dev, res); @@ -1210,6 +1252,7 @@ static struct platform_driver advk_pcie_driver = { .driver = { .name = "advk-pcie", .of_match_table = advk_pcie_of_match_table, + .pm = &advk_pcie_dev_pm_ops, /* Driver unloading/unbinding currently not supported */ .suppress_bind_attrs = true, }, From patchwork Tue Jan 8 16:24:33 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 1022004 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=bootlin.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43YyL161L7z9sND for ; Wed, 9 Jan 2019 03:25:45 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729535AbfAHQZi (ORCPT ); Tue, 8 Jan 2019 11:25:38 -0500 Received: from mail.bootlin.com ([62.4.15.54]:44894 "EHLO mail.bootlin.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729289AbfAHQYu (ORCPT ); Tue, 8 Jan 2019 11:24:50 -0500 Received: by mail.bootlin.com (Postfix, from userid 110) id E64BC20A1D; Tue, 8 Jan 2019 17:24:47 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on mail.bootlin.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT, URIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.2 Received: from localhost.localdomain (aaubervilliers-681-1-45-241.w90-88.abo.wanadoo.fr [90.88.163.241]) by mail.bootlin.com (Postfix) with ESMTPSA id 86DFD207A3; Tue, 8 Jan 2019 17:24:47 +0100 (CET) From: Miquel Raynal To: Gregory Clement , Jason Cooper , Andrew Lunn , Sebastian Hesselbarth , Thomas Petazzoni , Bjorn Helgaas Cc: , Rob Herring , Mark Rutland , Lorenzo Pieralisi , linux-pci@vger.kernel.org, , , Antoine Tenart , Maxime Chevallier , Nadav Haklai , Miquel Raynal Subject: [PATCH v3 08/15] dt-bindings: PCI: aardvark: Describe the clocks property Date: Tue, 8 Jan 2019 17:24:33 +0100 Message-Id: <20190108162441.5278-9-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190108162441.5278-1-miquel.raynal@bootlin.com> References: <20190108162441.5278-1-miquel.raynal@bootlin.com> MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Describe the missing gated clock feeding the PCIe IP. Signed-off-by: Miquel Raynal Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/pci/aardvark-pci.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/aardvark-pci.txt b/Documentation/devicetree/bindings/pci/aardvark-pci.txt index 310ef7145c47..9d19ebfea189 100644 --- a/Documentation/devicetree/bindings/pci/aardvark-pci.txt +++ b/Documentation/devicetree/bindings/pci/aardvark-pci.txt @@ -12,6 +12,7 @@ contain the following properties: - #size-cells: set to <2> - device_type: set to "pci" - ranges: ranges for the PCI memory and I/O regions + - clocks: the clock feeding the IP - #interrupt-cells: set to <1> - msi-controller: indicates that the PCIe controller can itself handle MSI interrupts @@ -37,6 +38,7 @@ Example: #address-cells = <3>; #size-cells = <2>; bus-range = <0x00 0xff>; + clocks = <&sb_periph_clk 13>; interrupts = ; #interrupt-cells = <1>; msi-controller; From patchwork Tue Jan 8 16:24:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 1022007 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=bootlin.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43YyLG4vgpz9sCr for ; Wed, 9 Jan 2019 03:25:58 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729579AbfAHQZv (ORCPT ); Tue, 8 Jan 2019 11:25:51 -0500 Received: from mail.bootlin.com ([62.4.15.54]:44897 "EHLO mail.bootlin.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729317AbfAHQYu (ORCPT ); Tue, 8 Jan 2019 11:24:50 -0500 Received: by mail.bootlin.com (Postfix, from userid 110) id 4498920A24; Tue, 8 Jan 2019 17:24:48 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on mail.bootlin.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT, URIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.2 Received: from localhost.localdomain (aaubervilliers-681-1-45-241.w90-88.abo.wanadoo.fr [90.88.163.241]) by mail.bootlin.com (Postfix) with ESMTPSA id DEDF2209C2; Tue, 8 Jan 2019 17:24:47 +0100 (CET) From: Miquel Raynal To: Gregory Clement , Jason Cooper , Andrew Lunn , Sebastian Hesselbarth , Thomas Petazzoni , Bjorn Helgaas Cc: , Rob Herring , Mark Rutland , Lorenzo Pieralisi , linux-pci@vger.kernel.org, , , Antoine Tenart , Maxime Chevallier , Nadav Haklai , Miquel Raynal Subject: [PATCH v3 09/15] dt-bindings: PCI: aardvark: Describe the PHY property Date: Tue, 8 Jan 2019 17:24:34 +0100 Message-Id: <20190108162441.5278-10-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190108162441.5278-1-miquel.raynal@bootlin.com> References: <20190108162441.5278-1-miquel.raynal@bootlin.com> MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Document the possibility to reference a PHY. Signed-off-by: Miquel Raynal Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/pci/aardvark-pci.txt | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/aardvark-pci.txt b/Documentation/devicetree/bindings/pci/aardvark-pci.txt index 9d19ebfea189..a440f182ccf8 100644 --- a/Documentation/devicetree/bindings/pci/aardvark-pci.txt +++ b/Documentation/devicetree/bindings/pci/aardvark-pci.txt @@ -21,6 +21,10 @@ contain the following properties: define the mapping of the PCIe interface to interrupt numbers. - bus-range: PCI bus numbers covered +The following are optional properties: + + - phys: the PCIe PHY handle + In addition, the Device Tree describing an Aardvark PCIe controller must include a sub-node that describes the legacy interrupt controller built into the PCIe controller. This sub-node must have the following @@ -50,6 +54,7 @@ Example: <0 0 0 2 &pcie_intc 1>, <0 0 0 3 &pcie_intc 2>, <0 0 0 4 &pcie_intc 3>; + phys = <&comphy1 0>; pcie_intc: interrupt-controller { interrupt-controller; #interrupt-cells = <1>; From patchwork Tue Jan 8 16:24:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 1022001 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=bootlin.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43YyKt00nqz9sND for ; Wed, 9 Jan 2019 03:25:37 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729169AbfAHQZa (ORCPT ); Tue, 8 Jan 2019 11:25:30 -0500 Received: from mail.bootlin.com ([62.4.15.54]:44901 "EHLO mail.bootlin.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729334AbfAHQYu (ORCPT ); Tue, 8 Jan 2019 11:24:50 -0500 Received: by mail.bootlin.com (Postfix, from userid 110) id A197920A2A; Tue, 8 Jan 2019 17:24:48 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on mail.bootlin.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT, URIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.2 Received: from localhost.localdomain (aaubervilliers-681-1-45-241.w90-88.abo.wanadoo.fr [90.88.163.241]) by mail.bootlin.com (Postfix) with ESMTPSA id 4218F207A3; Tue, 8 Jan 2019 17:24:48 +0100 (CET) From: Miquel Raynal To: Gregory Clement , Jason Cooper , Andrew Lunn , Sebastian Hesselbarth , Thomas Petazzoni , Bjorn Helgaas Cc: , Rob Herring , Mark Rutland , Lorenzo Pieralisi , linux-pci@vger.kernel.org, , , Antoine Tenart , Maxime Chevallier , Nadav Haklai , Miquel Raynal Subject: [PATCH v3 10/15] dt-bindings: PCI: aardvark: Describe the PCIe endpoint card reset pins Date: Tue, 8 Jan 2019 17:24:35 +0100 Message-Id: <20190108162441.5278-11-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190108162441.5278-1-miquel.raynal@bootlin.com> References: <20190108162441.5278-1-miquel.raynal@bootlin.com> MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org A line might be used by the PCIe IP to reset the endpoint card upon: - platform reset, - hot reset, - link failure. Describe the properties needed in this case (optional). Signed-off-by: Miquel Raynal Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/pci/aardvark-pci.txt | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/aardvark-pci.txt b/Documentation/devicetree/bindings/pci/aardvark-pci.txt index a440f182ccf8..8b7f048705ec 100644 --- a/Documentation/devicetree/bindings/pci/aardvark-pci.txt +++ b/Documentation/devicetree/bindings/pci/aardvark-pci.txt @@ -24,6 +24,9 @@ contain the following properties: The following are optional properties: - phys: the PCIe PHY handle + - pinctrl-names: must be "default". + - pinctrl-0: pin control group to be used to mux the PCIe endpoint card + reset line so that it will be automatically driven by the PCIe IP. In addition, the Device Tree describing an Aardvark PCIe controller must include a sub-node that describes the legacy interrupt controller @@ -55,6 +58,8 @@ Example: <0 0 0 3 &pcie_intc 2>, <0 0 0 4 &pcie_intc 3>; phys = <&comphy1 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_card_reset_pins &pcie_clkreq_pins>; pcie_intc: interrupt-controller { interrupt-controller; #interrupt-cells = <1>; From patchwork Tue Jan 8 16:24:36 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 1021997 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=bootlin.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43YyKk5blbz9sCr for ; Wed, 9 Jan 2019 03:25:30 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729343AbfAHQZS (ORCPT ); Tue, 8 Jan 2019 11:25:18 -0500 Received: from mail.bootlin.com ([62.4.15.54]:44906 "EHLO mail.bootlin.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729344AbfAHQYv (ORCPT ); Tue, 8 Jan 2019 11:24:51 -0500 Received: by mail.bootlin.com (Postfix, from userid 110) id 042A320A2F; Tue, 8 Jan 2019 17:24:49 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on mail.bootlin.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT, URIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.2 Received: from localhost.localdomain (aaubervilliers-681-1-45-241.w90-88.abo.wanadoo.fr [90.88.163.241]) by mail.bootlin.com (Postfix) with ESMTPSA id 9AA20209C2; Tue, 8 Jan 2019 17:24:48 +0100 (CET) From: Miquel Raynal To: Gregory Clement , Jason Cooper , Andrew Lunn , Sebastian Hesselbarth , Thomas Petazzoni , Bjorn Helgaas Cc: , Rob Herring , Mark Rutland , Lorenzo Pieralisi , linux-pci@vger.kernel.org, , , Antoine Tenart , Maxime Chevallier , Nadav Haklai , Miquel Raynal Subject: [PATCH v3 11/15] dt-bindings: PCI: aardvark: Describe the reset-gpios property Date: Tue, 8 Jan 2019 17:24:36 +0100 Message-Id: <20190108162441.5278-12-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190108162441.5278-1-miquel.raynal@bootlin.com> References: <20190108162441.5278-1-miquel.raynal@bootlin.com> MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org A GPIO might be used to reset the PCI IP. Describe the property needed in this case. Signed-off-by: Miquel Raynal Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/pci/aardvark-pci.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/aardvark-pci.txt b/Documentation/devicetree/bindings/pci/aardvark-pci.txt index 8b7f048705ec..b47d6d608ae1 100644 --- a/Documentation/devicetree/bindings/pci/aardvark-pci.txt +++ b/Documentation/devicetree/bindings/pci/aardvark-pci.txt @@ -27,6 +27,8 @@ The following are optional properties: - pinctrl-names: must be "default". - pinctrl-0: pin control group to be used to mux the PCIe endpoint card reset line so that it will be automatically driven by the PCIe IP. + - reset-gpios: GPIO to reset the device (alternative to the above + entries that represent a pin controlled by the PCI IP itself). In addition, the Device Tree describing an Aardvark PCIe controller must include a sub-node that describes the legacy interrupt controller From patchwork Tue Jan 8 16:24:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 1021996 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=bootlin.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43YyKj2MdGz9sCr for ; Wed, 9 Jan 2019 03:25:29 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729502AbfAHQZT (ORCPT ); Tue, 8 Jan 2019 11:25:19 -0500 Received: from mail.bootlin.com ([62.4.15.54]:44913 "EHLO mail.bootlin.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729364AbfAHQYv (ORCPT ); Tue, 8 Jan 2019 11:24:51 -0500 Received: by mail.bootlin.com (Postfix, from userid 110) id 6DA8B20A31; Tue, 8 Jan 2019 17:24:49 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on mail.bootlin.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT, URIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.2 Received: from localhost.localdomain (aaubervilliers-681-1-45-241.w90-88.abo.wanadoo.fr [90.88.163.241]) by mail.bootlin.com (Postfix) with ESMTPSA id 0076C207A3; Tue, 8 Jan 2019 17:24:48 +0100 (CET) From: Miquel Raynal To: Gregory Clement , Jason Cooper , Andrew Lunn , Sebastian Hesselbarth , Thomas Petazzoni , Bjorn Helgaas Cc: , Rob Herring , Mark Rutland , Lorenzo Pieralisi , linux-pci@vger.kernel.org, , , Antoine Tenart , Maxime Chevallier , Nadav Haklai , Miquel Raynal Subject: [PATCH v3 12/15] ARM64: dts: marvell: armada-37xx: declare PCIe clock Date: Tue, 8 Jan 2019 17:24:37 +0100 Message-Id: <20190108162441.5278-13-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190108162441.5278-1-miquel.raynal@bootlin.com> References: <20190108162441.5278-1-miquel.raynal@bootlin.com> MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The PCIe IP is fed by a gated clock. Signed-off-by: Miquel Raynal --- arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi index 65bf774516ec..f6f8d2b3b2c1 100644 --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi @@ -414,6 +414,7 @@ #address-cells = <3>; #size-cells = <2>; bus-range = <0x00 0xff>; + clocks = <&sb_periph_clk 13>; interrupts = ; #interrupt-cells = <1>; msi-parent = <&pcie0>; From patchwork Tue Jan 8 16:24:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 1021992 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=bootlin.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43YyKV1wcnz9sN8 for ; Wed, 9 Jan 2019 03:25:18 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729229AbfAHQZL (ORCPT ); Tue, 8 Jan 2019 11:25:11 -0500 Received: from mail.bootlin.com ([62.4.15.54]:44918 "EHLO mail.bootlin.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729370AbfAHQYv (ORCPT ); Tue, 8 Jan 2019 11:24:51 -0500 Received: by mail.bootlin.com (Postfix, from userid 110) id CE1D620A32; Tue, 8 Jan 2019 17:24:49 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on mail.bootlin.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT, URIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.2 Received: from localhost.localdomain (aaubervilliers-681-1-45-241.w90-88.abo.wanadoo.fr [90.88.163.241]) by mail.bootlin.com (Postfix) with ESMTPSA id 62428209C2; Tue, 8 Jan 2019 17:24:49 +0100 (CET) From: Miquel Raynal To: Gregory Clement , Jason Cooper , Andrew Lunn , Sebastian Hesselbarth , Thomas Petazzoni , Bjorn Helgaas Cc: , Rob Herring , Mark Rutland , Lorenzo Pieralisi , linux-pci@vger.kernel.org, , , Antoine Tenart , Maxime Chevallier , Nadav Haklai , Miquel Raynal Subject: [PATCH v3 13/15] ARM64: dts: marvell: armada-3720-espressobin: declare PCIe PHY Date: Tue, 8 Jan 2019 17:24:38 +0100 Message-Id: <20190108162441.5278-14-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190108162441.5278-1-miquel.raynal@bootlin.com> References: <20190108162441.5278-1-miquel.raynal@bootlin.com> MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The PCIe node is wired to the second PHY of the COMPHY IP. Suggested-by: Grzegorz Jaszczyk Signed-off-by: Miquel Raynal --- arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts index 094994a9c68e..c5c72902c647 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts @@ -46,6 +46,7 @@ /* J9 */ &pcie0 { status = "okay"; + phys = <&comphy1 0>; }; /* J6 */ From patchwork Tue Jan 8 16:24:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 1021989 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=bootlin.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43YyKR3bPMz9sNL for ; Wed, 9 Jan 2019 03:25:15 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729290AbfAHQYx (ORCPT ); Tue, 8 Jan 2019 11:24:53 -0500 Received: from mail.bootlin.com ([62.4.15.54]:44886 "EHLO mail.bootlin.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729377AbfAHQYw (ORCPT ); Tue, 8 Jan 2019 11:24:52 -0500 Received: by mail.bootlin.com (Postfix, from userid 110) id 2F86320A58; Tue, 8 Jan 2019 17:24:50 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on mail.bootlin.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT, URIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.2 Received: from localhost.localdomain (aaubervilliers-681-1-45-241.w90-88.abo.wanadoo.fr [90.88.163.241]) by mail.bootlin.com (Postfix) with ESMTPSA id C36C3207A3; Tue, 8 Jan 2019 17:24:49 +0100 (CET) From: Miquel Raynal To: Gregory Clement , Jason Cooper , Andrew Lunn , Sebastian Hesselbarth , Thomas Petazzoni , Bjorn Helgaas Cc: , Rob Herring , Mark Rutland , Lorenzo Pieralisi , linux-pci@vger.kernel.org, , , Antoine Tenart , Maxime Chevallier , Nadav Haklai , Miquel Raynal Subject: [PATCH v3 14/15] ARM64: dts: marvell: armada-37xx: declare PCIe reset pin Date: Tue, 8 Jan 2019 17:24:39 +0100 Message-Id: <20190108162441.5278-15-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190108162441.5278-1-miquel.raynal@bootlin.com> References: <20190108162441.5278-1-miquel.raynal@bootlin.com> MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org One pin can be muxed as PCIe endpoint card reset. Signed-off-by: Miquel Raynal --- arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi index f6f8d2b3b2c1..91c0ec9c382b 100644 --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi @@ -295,6 +295,15 @@ function = "mii"; }; + pcie_reset_pins: pcie-reset-pins { + groups = "pcie1"; + function = "pcie"; + }; + + pcie_clkreq_pins: pcie-clkreq-pins { + groups = "pcie1_clkreq"; + function = "pcie"; + }; }; eth0: ethernet@30000 { From patchwork Tue Jan 8 16:24:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 1021990 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=bootlin.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43YyKT2WcTz9sNL for ; Wed, 9 Jan 2019 03:25:17 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729423AbfAHQYw (ORCPT ); Tue, 8 Jan 2019 11:24:52 -0500 Received: from mail.bootlin.com ([62.4.15.54]:44884 "EHLO mail.bootlin.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729388AbfAHQYv (ORCPT ); Tue, 8 Jan 2019 11:24:51 -0500 Received: by mail.bootlin.com (Postfix, from userid 110) id 8846D209D7; Tue, 8 Jan 2019 17:24:50 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on mail.bootlin.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT, URIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.2 Received: from localhost.localdomain (aaubervilliers-681-1-45-241.w90-88.abo.wanadoo.fr [90.88.163.241]) by mail.bootlin.com (Postfix) with ESMTPSA id 286BF209C2; Tue, 8 Jan 2019 17:24:50 +0100 (CET) From: Miquel Raynal To: Gregory Clement , Jason Cooper , Andrew Lunn , Sebastian Hesselbarth , Thomas Petazzoni , Bjorn Helgaas Cc: , Rob Herring , Mark Rutland , Lorenzo Pieralisi , linux-pci@vger.kernel.org, , , Antoine Tenart , Maxime Chevallier , Nadav Haklai , Miquel Raynal Subject: [PATCH v3 15/15] ARM64: dts: marvell: armada-3720-espressobin: declare PCIe warm reset pin Date: Tue, 8 Jan 2019 17:24:40 +0100 Message-Id: <20190108162441.5278-16-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190108162441.5278-1-miquel.raynal@bootlin.com> References: <20190108162441.5278-1-miquel.raynal@bootlin.com> MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Ensure the PCIe endpoint card reset that is toggled by the PCIe controller itself is muxed correctly on the EspressoBin. Signed-off-by: Miquel Raynal --- arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts index c5c72902c647..f19c1ecd5703 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts @@ -47,6 +47,8 @@ &pcie0 { status = "okay"; phys = <&comphy1 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>; }; /* J6 */