From patchwork Wed Jan 2 14:09:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Henry Chen X-Patchwork-Id: 1019995 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=mediatek.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43VCdZ6820z9s9G for ; Thu, 3 Jan 2019 01:11:14 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726939AbfABOLC (ORCPT ); Wed, 2 Jan 2019 09:11:02 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:9274 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1729067AbfABOKf (ORCPT ); Wed, 2 Jan 2019 09:10:35 -0500 X-UUID: 25e44eb602514f53bf918fff357437a8-20190102 X-UUID: 25e44eb602514f53bf918fff357437a8-20190102 Received: from mtkcas08.mediatek.inc [(172.21.101.126)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1262923212; Wed, 02 Jan 2019 22:10:28 +0800 Received: from mtkcas09.mediatek.inc (172.21.101.178) by mtkmbs03n2.mediatek.inc (172.21.101.182) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 2 Jan 2019 22:10:26 +0800 Received: from mtkslt205.mediatek.inc (10.21.15.75) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Wed, 2 Jan 2019 22:10:26 +0800 From: Henry Chen To: Viresh Kumar , Stephen Boyd , Rob Herring , Matthias Brugger , Ulf Hansson CC: Mark Rutland , Fan Chen , Weiyi Lu , James Liao , Kees Cook , , , , , , Henry Chen Subject: [RFC RESEND PATCH 1/7] dt-bindings: soc: Add DVFSRC driver bindings Date: Wed, 2 Jan 2019 22:09:52 +0800 Message-ID: <1546438198-1677-2-git-send-email-henryc.chen@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1546438198-1677-1-git-send-email-henryc.chen@mediatek.com> References: <1546438198-1677-1-git-send-email-henryc.chen@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 218B0A421E84B4284B0CE4A8316AB19826A2E0BC71E3BCB0664419FF9E97905C2000:8 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Document the binding for enabling DVFSRC on MediaTek SoC. Signed-off-by: Henry Chen --- .../devicetree/bindings/soc/mediatek/dvfsrc.txt | 26 ++++++++++++++++++++++ include/dt-bindings/soc/mtk,dvfsrc.h | 18 +++++++++++++++ 2 files changed, 44 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/mediatek/dvfsrc.txt create mode 100644 include/dt-bindings/soc/mtk,dvfsrc.h diff --git a/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.txt b/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.txt new file mode 100644 index 0000000..402c885 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.txt @@ -0,0 +1,26 @@ +MediaTek DVFSRC Driver + +The Dynamic Voltage and Frequency Scaling Resource Collector (DVFSRC) is a +HW module which is used to collect all the requests from both software and +hardware and turn into the decision of minimum operating voltage and minimum +DRAM frequency to fulfill those requests. + +Required Properties: +- compatible: Should be one of the following + - "mediatek,mt8183-dvfsrc": For MT8183 SoC +- reg: Address range of the DVFSRC unit +- dram_type: Refer to for the + different dram type support. +- clock-names: Must include the following entries: + "dvfsrc": DVFSRC module clock +- clocks: Must contain an entry for each entry in clock-names. + +Example: + + dvfsrc_top@10012000 { + compatible = "mediatek,mt8183-dvfsrc"; + reg = <0 0x10012000 0 0x1000>; + clocks = <&infracfg CLK_INFRA_DVFSRC>; + clock-names = "dvfsrc"; + dram_type = ; + }; diff --git a/include/dt-bindings/soc/mtk,dvfsrc.h b/include/dt-bindings/soc/mtk,dvfsrc.h new file mode 100644 index 0000000..60b3497 --- /dev/null +++ b/include/dt-bindings/soc/mtk,dvfsrc.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (c) 2018 MediaTek Inc. + */ + +#ifndef _DT_BINDINGS_POWER_MTK_DVFSRC_H +#define _DT_BINDINGS_POWER_MTK_DVFSRC_H + +#define MT8183_DVFSRC_OPP_LP4 0 +#define MT8183_DVFSRC_OPP_LP4X 1 +#define MT8183_DVFSRC_OPP_LP3 2 + +#define MT8183_DVFSRC_LEVEL_1 1 +#define MT8183_DVFSRC_LEVEL_2 2 +#define MT8183_DVFSRC_LEVEL_3 3 +#define MT8183_DVFSRC_LEVEL_4 4 + +#endif /* _DT_BINDINGS_POWER_MTK_DVFSRC_H */ From patchwork Wed Jan 2 14:09:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Henry Chen X-Patchwork-Id: 1019994 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=mediatek.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43VCdM2rY2z9sDn for ; Thu, 3 Jan 2019 01:11:03 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729385AbfABOKf (ORCPT ); Wed, 2 Jan 2019 09:10:35 -0500 Received: from mailgw01.mediatek.com ([210.61.82.183]:36811 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1729089AbfABOKf (ORCPT ); Wed, 2 Jan 2019 09:10:35 -0500 X-UUID: 19e28fa6221b4e99b9fb31dc42cd8311-20190102 X-UUID: 19e28fa6221b4e99b9fb31dc42cd8311-20190102 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 252567244; Wed, 02 Jan 2019 22:10:28 +0800 Received: from mtkcas09.mediatek.inc (172.21.101.178) by mtkmbs03n1.mediatek.inc (172.21.101.181) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 2 Jan 2019 22:10:26 +0800 Received: from mtkslt205.mediatek.inc (10.21.15.75) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Wed, 2 Jan 2019 22:10:26 +0800 From: Henry Chen To: Viresh Kumar , Stephen Boyd , Rob Herring , Matthias Brugger , Ulf Hansson CC: Mark Rutland , Fan Chen , Weiyi Lu , James Liao , Kees Cook , , , , , , Henry Chen Subject: [RFC RESEND PATCH 2/7] dt-bindings: soc: Add opp table on scpsys bindings Date: Wed, 2 Jan 2019 22:09:53 +0800 Message-ID: <1546438198-1677-3-git-send-email-henryc.chen@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1546438198-1677-1-git-send-email-henryc.chen@mediatek.com> References: <1546438198-1677-1-git-send-email-henryc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add opp table on scpsys dt-bindings for Mediatek SoC. Signed-off-by: Henry Chen --- Documentation/devicetree/bindings/opp/mtk-opp.txt | 24 +++++++++++++ .../devicetree/bindings/soc/mediatek/scpsys.txt | 42 ++++++++++++++++++++++ 2 files changed, 66 insertions(+) create mode 100644 Documentation/devicetree/bindings/opp/mtk-opp.txt diff --git a/Documentation/devicetree/bindings/opp/mtk-opp.txt b/Documentation/devicetree/bindings/opp/mtk-opp.txt new file mode 100644 index 0000000..036be1c --- /dev/null +++ b/Documentation/devicetree/bindings/opp/mtk-opp.txt @@ -0,0 +1,24 @@ +Mediatek OPP bindings to descibe OPP nodes with level values + +OPP tables for devices on Mediatek platforms require an additional +platform specific level value to be specified. +This value is passed on to the mediatek Power Management Unit by the +CPU, which then takes the necessary actions to set a voltage rail +to an appropriate voltage based on the value passed. + +The bindings are based on top of the operating-points-v2 bindings +described in Documentation/devicetree/bindings/opp/opp.txt +Additional properties are described below. + +* OPP Table Node + +Required properties: +- compatible: Allow OPPs to express their compatibility. It should be: + "operating-points-v2-mtk-level" + +* OPP Node + +Required properties: +- mtk,level: On Mediatek platforms an OPP node can describe a positive value +representing a level that's communicated with a our power management hardware +which then translates it into a certain voltage on a voltage rail. diff --git a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt index b4728ce..299b526 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt +++ b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt @@ -63,6 +63,10 @@ Optional properties: - mfg_2d-supply: Power supply for the mfg_2d power domain - mfg-supply: Power supply for the mfg power domain +- operating-points-v2: Phandle to the OPP table for the Power domain. + Refer to Documentation/devicetree/bindings/power/power_domain.txt + and Documentation/devicetree/bindings/opp/mtk-opp.txt for more details + Example: scpsys: scpsys@10006000 { @@ -75,6 +79,27 @@ Example: <&topckgen CLK_TOP_VENC_SEL>, <&topckgen CLK_TOP_VENC_LT_SEL>; clock-names = "mfg", "mm", "venc", "venc_lt"; + operating-points-v2 = <&dvfsrc_opp_table>; + + dvfsrc_opp_table: opp-table { + compatible = "operating-points-v2-mtk-level"; + + dvfsrc_vol_min: opp1 { + mtk,level = ; + }; + + dvfsrc_freq_medium: opp2 { + mtk,level = ; + }; + + dvfsrc_freq_max: opp3 { + mtk,level = ; + }; + + dvfsrc_vol_max: opp4 { + mtk,level = ; + }; + }; }; Example consumer: @@ -82,4 +107,21 @@ Example consumer: afe: mt8173-afe-pcm@11220000 { compatible = "mediatek,mt8173-afe-pcm"; power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>; + operating-points-v2 = <&aud_opp_table>; + }; + + aud_opp_table: aud-opp-table { + compatible = "operating-points-v2"; + opp1 { + opp-hz = /bits/ 64 <793000000>; + required-opps = <&dvfsrc_vol_min>; + }; + opp2 { + opp-hz = /bits/ 64 <910000000>; + required-opps = <&dvfsrc_vol_max>; + }; + opp3 { + opp-hz = /bits/ 64 <1014000000>; + required-opps = <&dvfsrc_vol_max>; + }; };