From patchwork Wed Dec 5 07:12:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rick Chen X-Patchwork-Id: 1008032 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="p8+/open"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 438qgX6wqGz9s47 for ; Wed, 5 Dec 2018 18:12:40 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 93EE5C22485; Wed, 5 Dec 2018 07:12:39 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 86378C21D65; Wed, 5 Dec 2018 07:12:35 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 41141C21D65; Wed, 5 Dec 2018 07:12:33 +0000 (UTC) Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) by lists.denx.de (Postfix) with ESMTPS id E5F45C21C4A for ; Wed, 5 Dec 2018 07:12:32 +0000 (UTC) Received: by mail-wm1-f46.google.com with SMTP id c126so11692865wmh.0 for ; Tue, 04 Dec 2018 23:12:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:from:date:message-id:subject:to:cc; bh=rkk1giacpMD+KrYjYZxsTDIod3hIIjZnn2/HJvrtQOs=; b=p8+/openFXliSixU6TO1gZZQIHWRCc29Zpe0yeUJZrLZotAy6dFXvwfvrNBdyuP+S+ rdPaNWkEsNTIfDRljtGp6stAAOqY1G/2Ncm8Wb/t4nHY+CDy9ea+hK1biF3s0yYsDhpz bMmsRcF8D8SXBdW6fJ5oBzioDvO/SAb4xRV3dDwU8PplFxDcZnNalKPHWXKL3TrjKK3s otEVPOxCgP1n/q2mGY/Lp6/BGRsDZc7VVnTUgjy1spds0ZmkujJCP3H9yRtwYyIrZiXT Wuld3gBTw/HrRI4kElL4YnkcGL0lQp6rRNgV8LI4eQVcT5AuzUSnMRPbhFktXIocCJsX HSYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:from:date:message-id:subject:to:cc; bh=rkk1giacpMD+KrYjYZxsTDIod3hIIjZnn2/HJvrtQOs=; b=CHphOzb4I3ELQLFu+zJRO0B5AIlZ84LgIAWs31rgb3vz/LNDr2TUoGNyT8vGZpQCFP Gx+eyU7hdZAd1NkZ0Hdp3IWi/6ITqBM1BOvj1PNaHAP1zYLr/0sGhhchjTNYtVjZktfs nK9SSV59NCuGMb0t4j/H5u/l5BfyyAiKodm1LmCoIXFoAE83fUHvx+mnh1pRDV+cDxpQ V52eEWUm/GGoVxRxoOcYhNMn9cItXyhe9RAvmVrdsvKm5+GLUUCHc1J+KE2OvlNyzY46 9d1XCth3o1P48mExB6/GUtyoYSFeJmUk7esjxZOJL/Q4bzR5Rn52Dpidcv36UgdZbBSu GXfg== X-Gm-Message-State: AA+aEWZbFqu2UKhsCTj0F0dbnnOwe+DWZ/Iz37BwVTzRS3EMe6wWkmvH nu9TMiiJT7/IOAT54mV/D1e2wykxowdELoUNasmJlX8r X-Google-Smtp-Source: AFSGD/WFGAtMHUe7Z7lwwZWJh6z2Hm0qCdCPIDI/M242cu3CpIvqUiwVd/fMG8Aml8XUYuVfjjPtzRwR6fYQDbbZ8Rs= X-Received: by 2002:a1c:3489:: with SMTP id b131mr14623339wma.44.1543993952527; Tue, 04 Dec 2018 23:12:32 -0800 (PST) MIME-Version: 1.0 From: Rick Chen Date: Wed, 5 Dec 2018 15:12:29 +0800 Message-ID: To: Tom Rini Cc: U-Boot Mailing List Subject: [U-Boot] Please pull u-boot-riscv X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Hi Tom, Please pull some riscv update: 1. Fix BBL may be corrupted problem. 2. Support U-Boot run in S-mode. https://travis-ci.org/rickchen36/u-boot-riscv/builds/463646974 Thanks Rick The following changes since commit 2e2a2a5d4f0c2e2642326d9000ce1f1553632e6a: Merge branch 'master' of git://git.denx.de/u-boot-sh (2018-12-04 19:22:31 -0500) are available in the Git repository at: git://git.denx.de/u-boot-riscv.git for you to fetch changes up to 48cbf6246052de10d35b616b5efb2f783904a49d: riscv: ax25-ae350: Pass dtb address to u-boot with a1 register (2018-12-05 14:14:16 +0800) ---------------------------------------------------------------- Anup Patel (3): riscv: Add kconfig option to run U-Boot in S-mode riscv: qemu: Use different SYS_TEXT_BASE for S-mode riscv: Add S-mode defconfigs for QEMU virt machine Rick Chen (1): riscv: ax25-ae350: Pass dtb address to u-boot with a1 register arch/riscv/Kconfig | 5 +++++ arch/riscv/cpu/start.S | 25 +++++++++++++++---------- arch/riscv/include/asm/encoding.h | 6 ++++++ arch/riscv/lib/interrupts.c | 31 ++++++++++++++++++++++--------- board/AndesTech/ax25-ae350/ax25-ae350.c | 3 ++- board/emulation/qemu-riscv/Kconfig | 3 ++- board/emulation/qemu-riscv/MAINTAINERS | 2 ++ configs/qemu-riscv32_smode_defconfig | 10 ++++++++++ configs/qemu-riscv64_smode_defconfig | 11 +++++++++++ 9 files changed, 75 insertions(+), 21 deletions(-) create mode 100644 configs/qemu-riscv32_smode_defconfig create mode 100644 configs/qemu-riscv64_smode_defconfig