From patchwork Tue Dec 4 09:25:30 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 1007491 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="eV0vFeu+"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 438GhT4fbhz9s55 for ; Tue, 4 Dec 2018 20:26:33 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725834AbeLDJ0d (ORCPT ); Tue, 4 Dec 2018 04:26:33 -0500 Received: from hqemgate16.nvidia.com ([216.228.121.65]:4042 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725767AbeLDJ0d (ORCPT ); Tue, 4 Dec 2018 04:26:33 -0500 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 04 Dec 2018 01:26:33 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Tue, 04 Dec 2018 01:26:30 -0800 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Tue, 04 Dec 2018 01:26:30 -0800 Received: from HQMAIL103.nvidia.com (172.20.187.11) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 4 Dec 2018 09:26:30 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Tue, 4 Dec 2018 09:26:30 +0000 Received: from josephl-linux.nvidia.com (Not Verified[10.19.108.132]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 04 Dec 2018 01:26:30 -0800 From: Joseph Lo To: Thierry Reding , Peter De Schrijver , Jonathan Hunter CC: , , , , Joseph Lo Subject: [PATCH 01/19] dt-bindings: clock: tegra124-dfll: Update DFLL binding for PWM regulator Date: Tue, 4 Dec 2018 17:25:30 +0800 Message-ID: <20181204092548.3038-2-josephl@nvidia.com> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181204092548.3038-1-josephl@nvidia.com> References: <20181204092548.3038-1-josephl@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1543915593; bh=tJnc+qAFHVRJa54L5yE057fC3CXa15Vw8eOrB3IE/70=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=eV0vFeu+TMsgfnsvP9cwRRu6LPbfFF11pHcAOmgI95zB4Xw7PJWjX1AOwP9Lf33Dg 42RAUoOQben7XGhrCSgS6ZeKYwm4gl0sMQteVq6iQePH1sxhLHPG5MHV4SVQuPjt/s 90/LBNGtFu5e0qOWKMd1JmXC8jbC4FE9UMljXELKJsG4s3fH1pR+aZbj93KCRV1DJd t7XK7bAdQ1MyGH1Zrd7ee7NA/Tzd5LNv0Tya1JRIptpKUWT7qoz53MiUL20uJ+/e5o crPnd7Z+RCCs34wejaKAj8oOxtY30LChUBFp2F+Yi4Ux9jflAa5r1x8ZI3mlOGgIpi /ZuZEh/Bicxhg== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Peter De Schrijver Add new properties to configure the DFLL PWM regulator support. Also add an example and make the I2C clock only required when I2C support is used. Cc: devicetree@vger.kernel.org Signed-off-by: Peter De Schrijver Signed-off-by: Joseph Lo --- .../bindings/clock/nvidia,tegra124-dfll.txt | 73 ++++++++++++++++++- 1 file changed, 71 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt index dff236f524a7..8c97600d2bad 100644 --- a/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt +++ b/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt @@ -8,7 +8,6 @@ the fast CPU cluster. It consists of a free-running voltage controlled oscillator connected to the CPU voltage rail (VDD_CPU), and a closed loop control module that will automatically adjust the VDD_CPU voltage by communicating with an off-chip PMIC either via an I2C bus or via PWM signals. -Currently only the I2C mode is supported by these bindings. Required properties: - compatible : should be "nvidia,tegra124-dfll" @@ -45,10 +44,28 @@ Required properties for the control loop parameters: Optional properties for the control loop parameters: - nvidia,cg-scale: Boolean value, see the field DFLL_PARAMS_CG_SCALE in the TRM. +Optional properties for mode selection: +- nvidia,pwm-to-pmic: Use PWM to control regulator rather then I2C. + Required properties for I2C mode: - nvidia,i2c-fs-rate: I2C transfer rate, if using full speed mode. -Example: +Required properties for PWM mode: +- nvidia,pwm-period: period of PWM square wave in microseconds. +- nvidia,init-uv: Regulator voltage in micro volts when PWM control is disabled. +- nvidia,align-offset-uv: Regulator voltage in micro volts when PWM control is + enabled and PWM output is low. +- nvidia,align-step-uv: Voltage increase in micro volts corresponding to a + 1/33th increase in duty cycle. Eg the voltage for 2/33th + duty cycle would be: + nvidia,align-offset-uv + nvidia,align-step-uv * 2. +- pinctrl-0: I/O pad configuration when PWM control is enabled. +- pinctrl-1: I/O pad configuration when PWM control is disabled. +- pinctrl-names: must include the following entries: + - dvfs_pwm_enable: I/O pad configuration when PWM control is enabled. + - dvfs_pwm_disable: I/O pad configuration when PWM control is disabled. + +Example for I2C: clock@70110000 { compatible = "nvidia,tegra124-dfll"; @@ -76,3 +93,55 @@ clock@70110000 { nvidia,i2c-fs-rate = <400000>; }; + +Example for PWM: + +clock@70110000 { + compatible = "nvidia,tegra124-dfll"; + reg = <0 0x70110000 0 0x100>, /* DFLL control */ + <0 0x70110000 0 0x100>, /* I2C output control */ + <0 0x70110100 0 0x100>, /* Integrated I2C controller */ + <0 0x70110200 0 0x100>; /* Look-up table RAM */ + interrupts = ; + clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>, + <&tegra_car TEGRA210_CLK_DFLL_REF>, + <&tegra_car TEGRA124_CLK_I2C5>;; + clock-names = "soc", "ref", "i2c"; + resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>; + reset-names = "dvco"; + #clock-cells = <0>; + clock-output-names = "dfllCPU_out"; + nvidia,pwm-to-pmic; + nvidia,init-uv = <1000000>; + nvidia,align-step-uv = <19200>; /* 19.2mV */ + nvidia,align-offset-uv = <708000>; /* 708mV */ + nvidia,sample-rate = <25000>; + nvidia,droop-ctrl = <0x00000f00>; + nvidia,force-mode = <1>; + nvidia,cf = <6>; + nvidia,ci = <0>; + nvidia,cg = <2>; + nvidia,pwm-period = <2500>; /* 2.5us */ + pinctrl-names = "dvfs_pwm_enable", "dvfs_pwm_disable"; + pinctrl-0 = <&dvfs_pwm_active_state>; + pinctrl-1 = <&dvfs_pwm_inactive_state>; +}; + +/* pinmux nodes added for completeness. Binding doc can be found in: + * Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.txt + */ + +pinmux: pinmux@700008d4 { + dvfs_pwm_active_state: dvfs_pwm_active { + dvfs_pwm_pbb1 { + nvidia,pins = "dvfs_pwm_pbb1"; + nvidia,tristate = ; + }; + }; + dvfs_pwm_inactive_state: dvfs_pwm_inactive { + dvfs_pwm_pbb1 { + nvidia,pins = "dvfs_pwm_pbb1"; + nvidia,tristate = ; + }; + }; +}; From patchwork Tue Dec 4 09:25:31 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 1007493 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="eFM3SH/p"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 438GhY3PQHz9s55 for ; Tue, 4 Dec 2018 20:26:37 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725863AbeLDJ0g (ORCPT ); Tue, 4 Dec 2018 04:26:36 -0500 Received: from hqemgate16.nvidia.com ([216.228.121.65]:4045 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725767AbeLDJ0g (ORCPT ); Tue, 4 Dec 2018 04:26:36 -0500 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 04 Dec 2018 01:26:37 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Tue, 04 Dec 2018 01:26:35 -0800 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Tue, 04 Dec 2018 01:26:35 -0800 Received: from HQMAIL102.nvidia.com (172.18.146.10) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 4 Dec 2018 09:26:34 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL102.nvidia.com (172.18.146.10) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Tue, 4 Dec 2018 09:26:34 +0000 Received: from josephl-linux.nvidia.com (Not Verified[10.19.108.132]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 04 Dec 2018 01:26:34 -0800 From: Joseph Lo To: Thierry Reding , Peter De Schrijver , Jonathan Hunter CC: , , , Joseph Lo , Subject: [PATCH 02/19] dt-bindings: clock: tegra124-dfll: add Tegra210 support Date: Tue, 4 Dec 2018 17:25:31 +0800 Message-ID: <20181204092548.3038-3-josephl@nvidia.com> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181204092548.3038-1-josephl@nvidia.com> References: <20181204092548.3038-1-josephl@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1543915597; bh=c0gDJI0oagMAfW/bVTl/FY193pIwoFOy3oJkr8g4I14=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=eFM3SH/plzlnauZ0/4IHgLk4dAjZZkrD1IY0W9PrG5a8kOrd9+C+RmkZOZKZT9Y56 +mnuwypoffFbjTh9yYmV47mX5SG0Xb4J4MPoqHjLOQk5iVdP9szVAlqUkTWO2102fQ MzT73SvwyWxk4LyLbflrHTuiWN7p7TlOw7W+/8zhDR34z6FjmI46wf0bZ9au7mZExF VLU2QXrZVXYRqmTJrXX4+sNhR2YdOTN/f7cDrbdGGCL5rC5ZwXfmBGjImBBm7PQgM6 MatPM14skGSUfqZ4AN/DC5cMcA507uCBcWUFM2NCUJ4KUEWodWhuPn0i+FaxYIm/dE FHLF/++V7JCww== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Add Tegra210 support for DFLL clock. Cc: devicetree@vger.kernel.org Signed-off-by: Joseph Lo Acked-by: Jon Hunter --- .../devicetree/bindings/clock/nvidia,tegra124-dfll.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt index 8c97600d2bad..4bd44dd7ec1e 100644 --- a/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt +++ b/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt @@ -10,7 +10,9 @@ control module that will automatically adjust the VDD_CPU voltage by communicating with an off-chip PMIC either via an I2C bus or via PWM signals. Required properties: -- compatible : should be "nvidia,tegra124-dfll" +- compatible : should be one of: + - "nvidia,tegra124-dfll": for Tegra124 + - "nvidia,tegra210-dfll": for Tegra210 - reg : Defines the following set of registers, in the order listed: - registers for the DFLL control logic. - registers for the I2C output logic. From patchwork Tue Dec 4 09:25:32 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 1007495 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="MWmWUeLM"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 438Ghb0QX9z9s55 for ; Tue, 4 Dec 2018 20:26:39 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725898AbeLDJ0i (ORCPT ); Tue, 4 Dec 2018 04:26:38 -0500 Received: from hqemgate15.nvidia.com ([216.228.121.64]:19013 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725767AbeLDJ0i (ORCPT ); Tue, 4 Dec 2018 04:26:38 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 04 Dec 2018 01:26:37 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 04 Dec 2018 01:26:37 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 04 Dec 2018 01:26:37 -0800 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 4 Dec 2018 09:26:37 +0000 Received: from HQMAIL104.nvidia.com (172.18.146.11) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 4 Dec 2018 09:26:37 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Tue, 4 Dec 2018 09:26:37 +0000 Received: from josephl-linux.nvidia.com (Not Verified[10.19.108.132]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 04 Dec 2018 01:26:37 -0800 From: Joseph Lo To: Thierry Reding , Peter De Schrijver , Jonathan Hunter CC: , , , Joseph Lo , Subject: [PATCH 03/19] dt-bindings: cpufreq: tegra124: remove vdd-cpu-supply from required properties Date: Tue, 4 Dec 2018 17:25:32 +0800 Message-ID: <20181204092548.3038-4-josephl@nvidia.com> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181204092548.3038-1-josephl@nvidia.com> References: <20181204092548.3038-1-josephl@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1543915597; bh=oFIUZWNHCCdRz1ARKQmaqsrWbGyaFWNHECgg1sdJOzw=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=MWmWUeLMSozARm1Uh/eFiwrEKCMONzIJLK4HVQPoWo8ObYJR4js9otJVfrUz34MWk gXggvN8v17DrI+OerRoh1grI8vEoRAPsId5TFJz5m/lyIxa8vTLRGqX4PeNsdduojZ oRMvc8u8/JG/vKxP6iasl7g+A8YWm91+Z2ubMqyY4GEHQh9X38FbhHEPuYkAiE/l6M d5bKVHxBhMXMfV8lp9q7l43hAzQzjU1FF//jNy44b5xxcSrf2khjHIEfKtPapBNbh5 sj4K+5lMFWqcsH9fk2ZjhQOg7N2mXVQseNGpOLlYa1zT07gJnvAQv0pPnsOiyEndMz +QgEk0QN+gAOQ== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org The Tegra124 cpufreq driver works only with DFLL clock, which is a hardware-based frequency/voltage controller. The driver doesn't need to control the regulator itself. Hence remove that. Cc: devicetree@vger.kernel.org Signed-off-by: Joseph Lo Acked-by: Jon Hunter --- .../devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt | 2 -- 1 file changed, 2 deletions(-) diff --git a/Documentation/devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt b/Documentation/devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt index b1669fbfb740..031545a29caf 100644 --- a/Documentation/devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt +++ b/Documentation/devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt @@ -13,7 +13,6 @@ Required properties: - pll_x: Fast PLL clocksource. - pll_p: Auxiliary PLL used during fast PLL rate changes. - dfll: Fast DFLL clocksource that also automatically scales CPU voltage. -- vdd-cpu-supply: Regulator for CPU voltage Optional properties: - clock-latency: Specify the possible maximum transition latency for clock, @@ -37,7 +36,6 @@ cpus { <&dfll>; clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll"; clock-latency = <300000>; - vdd-cpu-supply: <&vdd_cpu>; }; <...> From patchwork Tue Dec 4 09:25:33 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 1007497 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="DfOXvGWc"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 438Ghj05rlz9s55 for ; Tue, 4 Dec 2018 20:26:45 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725767AbeLDJ0o (ORCPT ); Tue, 4 Dec 2018 04:26:44 -0500 Received: from hqemgate14.nvidia.com ([216.228.121.143]:3702 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725613AbeLDJ0o (ORCPT ); Tue, 4 Dec 2018 04:26:44 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 04 Dec 2018 01:26:43 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 04 Dec 2018 01:26:43 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 04 Dec 2018 01:26:43 -0800 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 4 Dec 2018 09:26:43 +0000 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 4 Dec 2018 09:26:43 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Tue, 4 Dec 2018 09:26:43 +0000 Received: from josephl-linux.nvidia.com (Not Verified[10.19.108.132]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 04 Dec 2018 01:26:42 -0800 From: Joseph Lo To: Thierry Reding , Peter De Schrijver , Jonathan Hunter CC: , , , Joseph Lo , Subject: [PATCH 04/19] dt-bindings: cpufreq: tegra124: remove cpu_lp clock from required properties Date: Tue, 4 Dec 2018 17:25:33 +0800 Message-ID: <20181204092548.3038-5-josephl@nvidia.com> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181204092548.3038-1-josephl@nvidia.com> References: <20181204092548.3038-1-josephl@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1543915603; bh=54g5O/FurZ7yAebuCOYdiwAgQkde0TtC+CkjFgnQVFE=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=DfOXvGWcihAgLs5UMlV47NcmboOeIgNGbkG6gDHmvCT1aQqDSHjjPLEnTGCcPM8Vr jHjQrE9WUWY8RN173/6tfSyiuZZf26+ETAjt4/JbwGYXVKpFRN+XSbBw8X2QmiIJ9a hpytdXSY8FKiVLCm8Q5dCOfWeyGjncP9S3s1KI3MWx0+PTWBGqWZt15W7gIc7CBbFb y1r2i7d5uYIyJ1foaVRW/BBXosg6fLJIk/l7heO+2OwhrkP8j5pHyOfAWH0NK0Xafs np+h733ECR3LJlYE+3FaYclwLlCWDcCBheK3FgofBtlmTCTlcZ14UZE/sQNnRzzbLE 2U1lfutqT0C0Q== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org The cpu_lp clock property is only needed when the CPUfreq driver supports CPU cluster switching. But it was not a design for this driver and it didn't handle that as well. So removing this property. Cc: devicetree@vger.kernel.org Signed-off-by: Joseph Lo Acked-by: Jon Hunter --- .../devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt b/Documentation/devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt index 031545a29caf..03196d5ea515 100644 --- a/Documentation/devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt +++ b/Documentation/devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt @@ -9,7 +9,6 @@ Required properties: See ../clocks/clock-bindings.txt for details. - clock-names: Must include the following entries: - cpu_g: Clock mux for the fast CPU cluster. - - cpu_lp: Clock mux for the low-power CPU cluster. - pll_x: Fast PLL clocksource. - pll_p: Auxiliary PLL used during fast PLL rate changes. - dfll: Fast DFLL clocksource that also automatically scales CPU voltage. @@ -30,11 +29,10 @@ cpus { reg = <0>; clocks = <&tegra_car TEGRA124_CLK_CCLK_G>, - <&tegra_car TEGRA124_CLK_CCLK_LP>, <&tegra_car TEGRA124_CLK_PLL_X>, <&tegra_car TEGRA124_CLK_PLL_P>, <&dfll>; - clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll"; + clock-names = "cpu_g", "pll_x", "pll_p", "dfll"; clock-latency = <300000>; }; From patchwork Tue Dec 4 09:25:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 1007499 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="jAQyYAVO"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 438Ghn1m4bz9s55 for ; Tue, 4 Dec 2018 20:26:49 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725834AbeLDJ0s (ORCPT ); Tue, 4 Dec 2018 04:26:48 -0500 Received: from hqemgate16.nvidia.com ([216.228.121.65]:4057 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725613AbeLDJ0s (ORCPT ); Tue, 4 Dec 2018 04:26:48 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 04 Dec 2018 01:26:48 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 04 Dec 2018 01:26:46 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 04 Dec 2018 01:26:46 -0800 Received: from HQMAIL108.nvidia.com (172.18.146.13) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 4 Dec 2018 09:26:46 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Tue, 4 Dec 2018 09:26:46 +0000 Received: from josephl-linux.nvidia.com (Not Verified[10.19.108.132]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 04 Dec 2018 01:26:45 -0800 From: Joseph Lo To: Thierry Reding , Peter De Schrijver , Jonathan Hunter CC: , , , Joseph Lo Subject: [PATCH 05/19] clk: tegra: dfll: registration for multiple SoCs Date: Tue, 4 Dec 2018 17:25:34 +0800 Message-ID: <20181204092548.3038-6-josephl@nvidia.com> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181204092548.3038-1-josephl@nvidia.com> References: <20181204092548.3038-1-josephl@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1543915608; bh=3+hDQSHosfLUjNyQx+ccH8i9y/yEj2CwPulL2jsrTsA=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=jAQyYAVOFItt/U2XSPwrT1k4qQtLBDKwk3jKeXxIuLvBazFDtbh87b/fz+PA6MdDp mw/oydZdch0VaZFHdpKSz24oUOslDKvtfLv2vcAmHwJSunTWBKT5NDlgsjZCDKecLY CFJdS78tOrCBEu6iJUqrgrge7Ttv9naRzGjbWAciQ/onQIWQBVn9fUctmZRPvhKjrn /WT9yHm3PRwJIdXGupXTNJAYaFieuWC3qgRRfTjlMM2mkAm+WuJ8bH4v1kmeNylDuv YT5yKhAG7m1EQq8/nW+l6TcCuE4UMuJRh3ss3k8prcHboh+YcQpmV2eFW5AJy2z7Nk Y/SZ+3JYxedpw== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Peter De Schrijver In a future patch, support for the DFLL in Tegra210 will be introduced. This requires support for more than 1 set of CVB and CPU max frequency tables. Signed-off-by: Peter De Schrijver Signed-off-by: Joseph Lo Acked-by: Jon Hunter --- drivers/clk/tegra/clk-tegra124-dfll-fcpu.c | 45 ++++++++++++++++------ 1 file changed, 34 insertions(+), 11 deletions(-) diff --git a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c b/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c index 269d3595758b..1a2cc113e5c8 100644 --- a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c +++ b/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c @@ -1,7 +1,7 @@ /* * Tegra124 DFLL FCPU clock source driver * - * Copyright (C) 2012-2014 NVIDIA Corporation. All rights reserved. + * Copyright (C) 2012-2018 NVIDIA Corporation. All rights reserved. * * Aleksandr Frid * Paul Walmsley @@ -21,6 +21,7 @@ #include #include #include +#include #include #include @@ -28,8 +29,15 @@ #include "clk-dfll.h" #include "cvb.h" +struct dfll_fcpu_data { + const unsigned long *cpu_max_freq_table; + unsigned int cpu_max_freq_table_size; + const struct cvb_table *cpu_cvb_tables; + unsigned int cpu_cvb_tables_size; +}; + /* Maximum CPU frequency, indexed by CPU speedo id */ -static const unsigned long cpu_max_freq_table[] = { +static const unsigned long tegra124_cpu_max_freq_table[] = { [0] = 2014500000UL, [1] = 2320500000UL, [2] = 2116500000UL, @@ -82,16 +90,36 @@ static const struct cvb_table tegra124_cpu_cvb_tables[] = { }, }; +static const struct dfll_fcpu_data tegra124_dfll_fcpu_data = { + .cpu_max_freq_table = tegra124_cpu_max_freq_table, + .cpu_max_freq_table_size = ARRAY_SIZE(tegra124_cpu_max_freq_table), + .cpu_cvb_tables = tegra124_cpu_cvb_tables, + .cpu_cvb_tables_size = ARRAY_SIZE(tegra124_cpu_cvb_tables) +}; + +static const struct of_device_id tegra124_dfll_fcpu_of_match[] = { + { + .compatible = "nvidia,tegra124-dfll", + .data = &tegra124_dfll_fcpu_data, + }, + { }, +}; + static int tegra124_dfll_fcpu_probe(struct platform_device *pdev) { int process_id, speedo_id, speedo_value, err; struct tegra_dfll_soc_data *soc; + const struct dfll_fcpu_data *fcpu_data; + + fcpu_data = of_device_get_match_data(&pdev->dev); + if (!fcpu_data) + return -ENODEV; process_id = tegra_sku_info.cpu_process_id; speedo_id = tegra_sku_info.cpu_speedo_id; speedo_value = tegra_sku_info.cpu_speedo_value; - if (speedo_id >= ARRAY_SIZE(cpu_max_freq_table)) { + if (speedo_id >= fcpu_data->cpu_max_freq_table_size) { dev_err(&pdev->dev, "unknown max CPU freq for speedo_id=%d\n", speedo_id); return -ENODEV; @@ -107,10 +135,10 @@ static int tegra124_dfll_fcpu_probe(struct platform_device *pdev) return -ENODEV; } - soc->max_freq = cpu_max_freq_table[speedo_id]; + soc->max_freq = fcpu_data->cpu_max_freq_table[speedo_id]; - soc->cvb = tegra_cvb_add_opp_table(soc->dev, tegra124_cpu_cvb_tables, - ARRAY_SIZE(tegra124_cpu_cvb_tables), + soc->cvb = tegra_cvb_add_opp_table(soc->dev, fcpu_data->cpu_cvb_tables, + fcpu_data->cpu_cvb_tables_size, process_id, speedo_id, speedo_value, soc->max_freq); if (IS_ERR(soc->cvb)) { @@ -142,11 +170,6 @@ static int tegra124_dfll_fcpu_remove(struct platform_device *pdev) return 0; } -static const struct of_device_id tegra124_dfll_fcpu_of_match[] = { - { .compatible = "nvidia,tegra124-dfll", }, - { }, -}; - static const struct dev_pm_ops tegra124_dfll_pm_ops = { SET_RUNTIME_PM_OPS(tegra_dfll_runtime_suspend, tegra_dfll_runtime_resume, NULL) From patchwork Tue Dec 4 09:25:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 1007500 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="ItgtNHa1"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 438Ghp3WCpz9s55 for ; Tue, 4 Dec 2018 20:26:50 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725949AbeLDJ0u (ORCPT ); Tue, 4 Dec 2018 04:26:50 -0500 Received: from hqemgate15.nvidia.com ([216.228.121.64]:19027 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725613AbeLDJ0u (ORCPT ); Tue, 4 Dec 2018 04:26:50 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 04 Dec 2018 01:26:48 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 04 Dec 2018 01:26:48 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 04 Dec 2018 01:26:48 -0800 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 4 Dec 2018 09:26:48 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Tue, 4 Dec 2018 09:26:48 +0000 Received: from josephl-linux.nvidia.com (Not Verified[10.19.108.132]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 04 Dec 2018 01:26:48 -0800 From: Joseph Lo To: Thierry Reding , Peter De Schrijver , Jonathan Hunter CC: , , , Joseph Lo Subject: [PATCH 06/19] clk: tegra: dfll: CVB calculation alignment with the regulator Date: Tue, 4 Dec 2018 17:25:35 +0800 Message-ID: <20181204092548.3038-7-josephl@nvidia.com> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181204092548.3038-1-josephl@nvidia.com> References: <20181204092548.3038-1-josephl@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1543915608; bh=+XcDnjn2X0MQX5PdnSMI4QdykdpfPcxcaejusl4gSmA=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=ItgtNHa183FzHlT47ji8sSAFeueDt4NKhf9BG/VB7PWajWoDw2CsMpDOlrM6wyuzT oEU43wj3SBpBF53V5LtOlRAnDqRUCqLahYb+64NDuq6+fv0adEoyeBmgandcpr9p9J CIJLM7mNxAkKDk+wcsmWBA+d7asK8T5Lfrs+dnqyEnKL6DHVOt0Tn8L4rmqnIHIoCc 91dHVSGZRb/f1YPHimvsQ7gFWYq1MqcPkifcLmRm8XjF5Qc6xtNkr72rviFqovRCMO /AeiHKSnPCTTQTjt84vS8yZqieA7/+GhXKEbwxDeS7rv1wMUfCzb2GGg1kVTkC+47i SYjkYqVi68iHg== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org The CVB table contains calibration data for the CPU DFLL based on process charaterization. The regulator step and offset parameters depend on the regulator supplying vdd-cpu , not on the specific Tegra SKU. When using a PWM controlled regulator, the voltage step and offset are determined by the regulator type in use. This is specified in DT. When using an I2C controlled regulator, we can retrieve them from CPU regulator or DT (if specified). Then pass this information to the CVB table calculation function. Based on the work done of "Peter De Schrijver " and "Alex Frid ". Signed-off-by: Joseph Lo --- drivers/clk/tegra/clk-dfll.h | 6 +- drivers/clk/tegra/clk-tegra124-dfll-fcpu.c | 65 ++++++++++++++++++++-- drivers/clk/tegra/cvb.c | 12 ++-- drivers/clk/tegra/cvb.h | 6 +- 4 files changed, 75 insertions(+), 14 deletions(-) diff --git a/drivers/clk/tegra/clk-dfll.h b/drivers/clk/tegra/clk-dfll.h index 83352c8078f2..ecc43cb9b6f1 100644 --- a/drivers/clk/tegra/clk-dfll.h +++ b/drivers/clk/tegra/clk-dfll.h @@ -1,6 +1,6 @@ /* * clk-dfll.h - prototypes and macros for the Tegra DFLL clocksource driver - * Copyright (C) 2013 NVIDIA Corporation. All rights reserved. + * Copyright (C) 2013-2018 NVIDIA Corporation. All rights reserved. * * Aleksandr Frid * Paul Walmsley @@ -22,11 +22,14 @@ #include #include +#include "cvb.h" + /** * struct tegra_dfll_soc_data - SoC-specific hooks/integration for the DFLL driver * @dev: struct device * that holds the OPP table for the DFLL * @max_freq: maximum frequency supported on this SoC * @cvb: CPU frequency table for this SoC + * @alignment: parameters of the regulator step and offset * @init_clock_trimmers: callback to initialize clock trimmers * @set_clock_trimmers_high: callback to tune clock trimmers for high voltage * @set_clock_trimmers_low: callback to tune clock trimmers for low voltage @@ -35,6 +38,7 @@ struct tegra_dfll_soc_data { struct device *dev; unsigned long max_freq; const struct cvb_table *cvb; + struct rail_alignment alignment; void (*init_clock_trimmers)(void); void (*set_clock_trimmers_high)(void); diff --git a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c b/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c index 1a2cc113e5c8..071a5c674832 100644 --- a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c +++ b/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include "clk.h" @@ -50,9 +51,6 @@ static const struct cvb_table tegra124_cpu_cvb_tables[] = { .process_id = -1, .min_millivolts = 900, .max_millivolts = 1260, - .alignment = { - .step_uv = 10000, /* 10mV */ - }, .speedo_scale = 100, .voltage_scale = 1000, .entries = { @@ -105,11 +103,43 @@ static const struct of_device_id tegra124_dfll_fcpu_of_match[] = { { }, }; +static void get_alignment_from_dt(struct device *dev, + struct rail_alignment *align) +{ + align->step_uv = 0; + align->offset_uv = 0; + + if (of_property_read_u32(dev->of_node, "nvidia,align-step-uv", + &align->step_uv)) + align->step_uv = 0; + + if (of_property_read_u32(dev->of_node, + "nvidia,align-offset-uv", &align->offset_uv)) + align->offset_uv = 0; +} + +static int get_alignment_from_regulator(struct device *dev, + struct rail_alignment *align) +{ + struct regulator *reg = devm_regulator_get(dev, "vdd-cpu"); + + if (IS_ERR(reg)) + return PTR_ERR(reg); + + align->offset_uv = regulator_list_voltage(reg, 0); + align->step_uv = regulator_get_linear_step(reg); + + devm_regulator_put(reg); + + return 0; +} + static int tegra124_dfll_fcpu_probe(struct platform_device *pdev) { int process_id, speedo_id, speedo_value, err; struct tegra_dfll_soc_data *soc; const struct dfll_fcpu_data *fcpu_data; + struct rail_alignment align; fcpu_data = of_device_get_match_data(&pdev->dev); if (!fcpu_data) @@ -135,12 +165,37 @@ static int tegra124_dfll_fcpu_probe(struct platform_device *pdev) return -ENODEV; } + get_alignment_from_dt(&pdev->dev, &align); + if (of_property_read_bool(pdev->dev.of_node, "nvidia,pwm-to-pmic") + && (!align.step_uv || !align.offset_uv)) { + dev_info(&pdev->dev, "Missing required align data in DT"); + return -EINVAL; + } else { + if (!align.step_uv) { + dev_info(&pdev->dev, + "no align data in DT, try from vdd-cpu\n"); + err = get_alignment_from_regulator(&pdev->dev, &align); + if (err == -EPROBE_DEFER) { + dev_info(&pdev->dev, + "defer probe to get vdd-cpu\n"); + return -EPROBE_DEFER; + } + } + } + + if (!align.step_uv) { + dev_err(&pdev->dev, "missing step uv\n"); + return -EINVAL; + } + soc->max_freq = fcpu_data->cpu_max_freq_table[speedo_id]; soc->cvb = tegra_cvb_add_opp_table(soc->dev, fcpu_data->cpu_cvb_tables, fcpu_data->cpu_cvb_tables_size, - process_id, speedo_id, speedo_value, - soc->max_freq); + &align, process_id, speedo_id, + speedo_value, soc->max_freq); + soc->alignment = align; + if (IS_ERR(soc->cvb)) { dev_err(&pdev->dev, "couldn't add OPP table: %ld\n", PTR_ERR(soc->cvb)); diff --git a/drivers/clk/tegra/cvb.c b/drivers/clk/tegra/cvb.c index da9e8e7b5ce5..81dcb97a9e0a 100644 --- a/drivers/clk/tegra/cvb.c +++ b/drivers/clk/tegra/cvb.c @@ -1,7 +1,7 @@ /* * Utility functions for parsing Tegra CVB voltage tables * - * Copyright (C) 2012-2014 NVIDIA Corporation. All rights reserved. + * Copyright (C) 2012-2018 NVIDIA Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -62,9 +62,9 @@ static int round_voltage(int mv, const struct rail_alignment *align, int up) } static int build_opp_table(struct device *dev, const struct cvb_table *table, + struct rail_alignment *align, int speedo_value, unsigned long max_freq) { - const struct rail_alignment *align = &table->alignment; int i, ret, dfll_mv, min_mv, max_mv; min_mv = round_voltage(table->min_millivolts, align, UP); @@ -109,8 +109,9 @@ static int build_opp_table(struct device *dev, const struct cvb_table *table, */ const struct cvb_table * tegra_cvb_add_opp_table(struct device *dev, const struct cvb_table *tables, - size_t count, int process_id, int speedo_id, - int speedo_value, unsigned long max_freq) + size_t count, struct rail_alignment *align, + int process_id, int speedo_id, int speedo_value, + unsigned long max_freq) { size_t i; int ret; @@ -124,7 +125,8 @@ tegra_cvb_add_opp_table(struct device *dev, const struct cvb_table *tables, if (table->process_id != -1 && table->process_id != process_id) continue; - ret = build_opp_table(dev, table, speedo_value, max_freq); + ret = build_opp_table(dev, table, align, speedo_value, + max_freq); return ret ? ERR_PTR(ret) : table; } diff --git a/drivers/clk/tegra/cvb.h b/drivers/clk/tegra/cvb.h index c1f077993b2a..bcf15a089b93 100644 --- a/drivers/clk/tegra/cvb.h +++ b/drivers/clk/tegra/cvb.h @@ -49,7 +49,6 @@ struct cvb_table { int min_millivolts; int max_millivolts; - struct rail_alignment alignment; int speedo_scale; int voltage_scale; @@ -59,8 +58,9 @@ struct cvb_table { const struct cvb_table * tegra_cvb_add_opp_table(struct device *dev, const struct cvb_table *cvb_tables, - size_t count, int process_id, int speedo_id, - int speedo_value, unsigned long max_freq); + size_t count, struct rail_alignment *align, + int process_id, int speedo_id, int speedo_value, + unsigned long max_freq); void tegra_cvb_remove_opp_table(struct device *dev, const struct cvb_table *table, unsigned long max_freq); From patchwork Tue Dec 4 09:25:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 1007502 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="L9vlxOku"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 438Ght37NZz9s55 for ; Tue, 4 Dec 2018 20:26:54 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725863AbeLDJ0y (ORCPT ); Tue, 4 Dec 2018 04:26:54 -0500 Received: from hqemgate14.nvidia.com ([216.228.121.143]:3711 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725613AbeLDJ0x (ORCPT ); Tue, 4 Dec 2018 04:26:53 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 04 Dec 2018 01:26:50 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 04 Dec 2018 01:26:51 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 04 Dec 2018 01:26:51 -0800 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 4 Dec 2018 09:26:51 +0000 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 4 Dec 2018 09:26:50 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Tue, 4 Dec 2018 09:26:50 +0000 Received: from josephl-linux.nvidia.com (Not Verified[10.19.108.132]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 04 Dec 2018 01:26:50 -0800 From: Joseph Lo To: Thierry Reding , Peter De Schrijver , Jonathan Hunter CC: , , , Joseph Lo Subject: [PATCH 07/19] clk: tegra: dfll: support PWM regulator control Date: Tue, 4 Dec 2018 17:25:36 +0800 Message-ID: <20181204092548.3038-8-josephl@nvidia.com> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181204092548.3038-1-josephl@nvidia.com> References: <20181204092548.3038-1-josephl@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1543915610; bh=iWxR/nHONSVgEB5XNYnmDTnYUzAYU2I31qQw63bW12c=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=L9vlxOkujMtnPqZg00gtzPjkfiuCyCy+Je+KIbEtmgYVuLT7U2Ty2H7eo0ZYSkPDL KKfwdOk3aKyScGxgLKbj1n4Pw9gA8El509AdXc6RrdL7up4NlyNdALTTCsYCusPmh7 0cwdMwL1C32VozrM4x0mX+UV3HvoP6tPmnyodmz+pZk5YZj/OMOotR2iR6CuilH4Ko YakHWjhSNNFqCCxkDMw1Scb2HUp6xW6QxJYY7CaAzRIIduNRd2PdqRvr+TlOo2x35V Yd+tY8p6ho8Jucv1amZHD8KN8rv94Bznxjb/1WYtg3knZNXpl2S8eP3+C4i12apjSZ 0m5VWHswfDSRQ== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org The DFLL hardware supports two modes (I2C and PWM) for voltage control when requesting a frequency. In this patch, we introduce PWM mode support. To support that, we re-organize the LUT for unifying the table for both cases of I2C and PWM mode. And generate that based on regulator info. For the PWM-based regulator, we get this info from DT. And do the same as the case of I2C LUT, which can help to map the PMIC voltage ID and voltages that the regulator supported. The other parts are the support code for initializing the DFLL hardware to support PWM mode. Also, the register debugfs file is slightly reworked to only show the i2c registers when I2C mode is in use. Based on the work of Peter De Schrijver . Signed-off-by: Joseph Lo --- drivers/clk/tegra/clk-dfll.c | 431 ++++++++++++++++++++++++++++++----- 1 file changed, 368 insertions(+), 63 deletions(-) diff --git a/drivers/clk/tegra/clk-dfll.c b/drivers/clk/tegra/clk-dfll.c index 609e363dabf8..c294a2989f31 100644 --- a/drivers/clk/tegra/clk-dfll.c +++ b/drivers/clk/tegra/clk-dfll.c @@ -1,7 +1,7 @@ /* * clk-dfll.c - Tegra DFLL clock source common code * - * Copyright (C) 2012-2014 NVIDIA Corporation. All rights reserved. + * Copyright (C) 2012-2018 NVIDIA Corporation. All rights reserved. * * Aleksandr Frid * Paul Walmsley @@ -47,6 +47,7 @@ #include #include #include +#include #include #include #include @@ -243,6 +244,12 @@ enum dfll_tune_range { DFLL_TUNE_LOW = 1, }; + +enum tegra_dfll_pmu_if { + TEGRA_DFLL_PMU_I2C = 0, + TEGRA_DFLL_PMU_PWM = 1, +}; + /** * struct dfll_rate_req - target DFLL rate request data * @rate: target frequency, after the postscaling @@ -294,16 +301,25 @@ struct tegra_dfll { u32 ci; u32 cg; bool cg_scale; + u32 reg_init_uV; /* I2C interface parameters */ u32 i2c_fs_rate; u32 i2c_reg; u32 i2c_slave_addr; - /* i2c_lut array entries are regulator framework selectors */ - unsigned i2c_lut[MAX_DFLL_VOLTAGES]; - int i2c_lut_size; - u8 lut_min, lut_max, lut_safe; + /* lut array entries are regulator framework selectors or PWM values*/ + unsigned lut[MAX_DFLL_VOLTAGES]; + unsigned lut_uv[MAX_DFLL_VOLTAGES]; + int lut_size; + u8 lut_bottom, lut_min, lut_max, lut_safe; + + /* PWM interface */ + enum tegra_dfll_pmu_if pmu_if; + unsigned long pwm_rate; + struct pinctrl *pwm_pin; + struct pinctrl_state *pwm_enable_state; + struct pinctrl_state *pwm_disable_state; }; #define clk_hw_to_dfll(_hw) container_of(_hw, struct tegra_dfll, dfll_clk_hw) @@ -489,6 +505,34 @@ static void dfll_set_mode(struct tegra_dfll *td, dfll_wmb(td); } +/* + * DVCO rate control + */ + +static unsigned long get_dvco_rate_below(struct tegra_dfll *td, u8 out_min) +{ + struct dev_pm_opp *opp; + unsigned long rate, prev_rate; + int uv, min_uv; + + min_uv = td->lut_uv[out_min]; + for (rate = 0, prev_rate = 0; ; rate++) { + opp = dev_pm_opp_find_freq_ceil(td->soc->dev, &rate); + if (IS_ERR(opp)) + break; + + uv = dev_pm_opp_get_voltage(opp); + dev_pm_opp_put(opp); + + if (uv && uv > min_uv) + return prev_rate; + + prev_rate = rate; + } + + return prev_rate; +} + /* * DFLL-to-I2C controller interface */ @@ -518,6 +562,118 @@ static int dfll_i2c_set_output_enabled(struct tegra_dfll *td, bool enable) return 0; } + +/* + * DFLL-to-PWM controller interface + */ + +/** + * dfll_pwm_set_output_enabled - enable/disable PWM voltage requests + * @td: DFLL instance + * @enable: whether to enable or disable the PWM voltage requests + * + * Set the master enable control for PWM control value updates. If disabled, + * then the PWM signal is not driven. Also configure the PWM output pad + * to the appropriate state. + */ +static int dfll_pwm_set_output_enabled(struct tegra_dfll *td, bool enable) +{ + int ret; + u32 val, div; + + if (enable) { + ret = pinctrl_select_state(td->pwm_pin, td->pwm_enable_state); + if (ret < 0) { + dev_err(td->dev, "setting enable state failed\n"); + return -EINVAL; + } + val = dfll_readl(td, DFLL_OUTPUT_CFG); + val &= ~DFLL_OUTPUT_CFG_PWM_DIV_MASK; + div = DIV_ROUND_UP(td->ref_rate, td->pwm_rate); + val |= (div << DFLL_OUTPUT_CFG_PWM_DIV_SHIFT) + & DFLL_OUTPUT_CFG_PWM_DIV_MASK; + dfll_writel(td, val, DFLL_OUTPUT_CFG); + dfll_wmb(td); + + val |= DFLL_OUTPUT_CFG_PWM_ENABLE; + dfll_writel(td, val, DFLL_OUTPUT_CFG); + dfll_wmb(td); + } else { + ret = pinctrl_select_state(td->pwm_pin, td->pwm_disable_state); + if (ret < 0) + dev_warn(td->dev, "setting disable state failed\n"); + + val = dfll_readl(td, DFLL_OUTPUT_CFG); + val &= ~DFLL_OUTPUT_CFG_PWM_ENABLE; + dfll_writel(td, val, DFLL_OUTPUT_CFG); + dfll_wmb(td); + } + + return 0; +} + +/** + * dfll_set_force_output_value - set fixed value for force output + * @td: DFLL instance + * @out_val: value to force output + * + * Set the fixed value for force output, DFLL will output this value when + * force output is enabled. + */ +static u32 dfll_set_force_output_value(struct tegra_dfll *td, u8 out_val) +{ + u32 val = dfll_readl(td, DFLL_OUTPUT_FORCE); + + val = (val & DFLL_OUTPUT_FORCE_ENABLE) | (out_val & OUT_MASK); + dfll_writel(td, val, DFLL_OUTPUT_FORCE); + dfll_wmb(td); + + return dfll_readl(td, DFLL_OUTPUT_FORCE); +} + +/** + * dfll_set_force_output_enabled - enable/disable force output + * @td: DFLL instance + * @enable: whether to enable or disable the force output + * + * Set the enable control for fouce output with fixed value. + */ +static void dfll_set_force_output_enabled(struct tegra_dfll *td, bool enable) +{ + u32 val = dfll_readl(td, DFLL_OUTPUT_FORCE); + + if (enable) + val |= DFLL_OUTPUT_FORCE_ENABLE; + else + val &= ~DFLL_OUTPUT_FORCE_ENABLE; + + dfll_writel(td, val, DFLL_OUTPUT_FORCE); + dfll_wmb(td); +} + +/** + * dfll_force_output - force output a fixed value + * @td: DFLL instance + * @out_sel: value to force output + * + * Set the fixed value for force output, DFLL will output this value. + */ +static int dfll_force_output(struct tegra_dfll *td, unsigned int out_sel) +{ + u32 val; + + if (out_sel > OUT_MASK) + return -EINVAL; + + val = dfll_set_force_output_value(td, out_sel); + if ((td->mode < DFLL_CLOSED_LOOP) && + !(val & DFLL_OUTPUT_FORCE_ENABLE)) { + dfll_set_force_output_enabled(td, true); + } + + return 0; +} + /** * dfll_load_lut - load the voltage lookup table * @td: struct tegra_dfll * @@ -539,7 +695,7 @@ static void dfll_load_i2c_lut(struct tegra_dfll *td) lut_index = i; val = regulator_list_hardware_vsel(td->vdd_reg, - td->i2c_lut[lut_index]); + td->lut[lut_index]); __raw_writel(val, td->lut_base + i * 4); } @@ -594,24 +750,41 @@ static void dfll_init_out_if(struct tegra_dfll *td) { u32 val; - td->lut_min = 0; - td->lut_max = td->i2c_lut_size - 1; - td->lut_safe = td->lut_min + 1; + td->lut_min = td->lut_bottom; + td->lut_max = td->lut_size - 1; + td->lut_safe = td->lut_min + (td->lut_min < td->lut_max ? 1 : 0); + + /* clear DFLL_OUTPUT_CFG before setting new value */ + dfll_writel(td, 0, DFLL_OUTPUT_CFG); + dfll_wmb(td); - dfll_i2c_writel(td, 0, DFLL_OUTPUT_CFG); val = (td->lut_safe << DFLL_OUTPUT_CFG_SAFE_SHIFT) | - (td->lut_max << DFLL_OUTPUT_CFG_MAX_SHIFT) | - (td->lut_min << DFLL_OUTPUT_CFG_MIN_SHIFT); - dfll_i2c_writel(td, val, DFLL_OUTPUT_CFG); - dfll_i2c_wmb(td); + (td->lut_max << DFLL_OUTPUT_CFG_MAX_SHIFT) | + (td->lut_min << DFLL_OUTPUT_CFG_MIN_SHIFT); + dfll_writel(td, val, DFLL_OUTPUT_CFG); + dfll_wmb(td); dfll_writel(td, 0, DFLL_OUTPUT_FORCE); dfll_i2c_writel(td, 0, DFLL_INTR_EN); dfll_i2c_writel(td, DFLL_INTR_MAX_MASK | DFLL_INTR_MIN_MASK, DFLL_INTR_STS); - dfll_load_i2c_lut(td); - dfll_init_i2c_if(td); + if (td->pmu_if == TEGRA_DFLL_PMU_PWM) { + int vinit = td->reg_init_uV; + int vstep = td->soc->alignment.step_uv; + int vmin = td->lut_uv[0]; + + /* set initial voltage */ + if ((vinit >= vmin) && vstep) { + unsigned int vsel; + + vsel = DIV_ROUND_UP((vinit - vmin), vstep); + dfll_force_output(td, vsel); + } + } else { + dfll_load_i2c_lut(td); + dfll_init_i2c_if(td); + } } /* @@ -640,8 +813,8 @@ static int find_lut_index_for_rate(struct tegra_dfll *td, unsigned long rate) uv = dev_pm_opp_get_voltage(opp); dev_pm_opp_put(opp); - for (i = 0; i < td->i2c_lut_size; i++) { - if (regulator_list_voltage(td->vdd_reg, td->i2c_lut[i]) == uv) + for (i = td->lut_bottom; i < td->lut_size; i++) { + if (regulator_list_voltage(td->vdd_reg, td->lut[i]) == uv) return i; } @@ -863,9 +1036,14 @@ static int dfll_lock(struct tegra_dfll *td) return -EINVAL; } - dfll_i2c_set_output_enabled(td, true); + if (td->pmu_if == TEGRA_DFLL_PMU_PWM) + dfll_pwm_set_output_enabled(td, true); + else + dfll_i2c_set_output_enabled(td, true); + dfll_set_mode(td, DFLL_CLOSED_LOOP); dfll_set_frequency_request(td, req); + dfll_set_force_output_enabled(td, false); return 0; default: @@ -889,7 +1067,10 @@ static int dfll_unlock(struct tegra_dfll *td) case DFLL_CLOSED_LOOP: dfll_set_open_loop_config(td); dfll_set_mode(td, DFLL_OPEN_LOOP); - dfll_i2c_set_output_enabled(td, false); + if (td->pmu_if == TEGRA_DFLL_PMU_PWM) + dfll_pwm_set_output_enabled(td, false); + else + dfll_i2c_set_output_enabled(td, false); return 0; case DFLL_OPEN_LOOP: @@ -1171,15 +1352,17 @@ static int attr_registers_show(struct seq_file *s, void *data) seq_printf(s, "[0x%02x] = 0x%08x\n", offs, dfll_i2c_readl(td, offs)); - seq_puts(s, "\nINTEGRATED I2C CONTROLLER REGISTERS:\n"); - offs = DFLL_I2C_CLK_DIVISOR; - seq_printf(s, "[0x%02x] = 0x%08x\n", offs, - __raw_readl(td->i2c_controller_base + offs)); - - seq_puts(s, "\nLUT:\n"); - for (offs = 0; offs < 4 * MAX_DFLL_VOLTAGES; offs += 4) + if (td->pmu_if == TEGRA_DFLL_PMU_I2C) { + seq_puts(s, "\nINTEGRATED I2C CONTROLLER REGISTERS:\n"); + offs = DFLL_I2C_CLK_DIVISOR; seq_printf(s, "[0x%02x] = 0x%08x\n", offs, - __raw_readl(td->lut_base + offs)); + __raw_readl(td->i2c_controller_base + offs)); + + seq_puts(s, "\nLUT:\n"); + for (offs = 0; offs < 4 * MAX_DFLL_VOLTAGES; offs += 4) + seq_printf(s, "[0x%02x] = 0x%08x\n", offs, + __raw_readl(td->lut_base + offs)); + } return 0; } @@ -1387,9 +1570,61 @@ static int find_vdd_map_entry_min(struct tegra_dfll *td, int uV) return -EINVAL; } +/* + * dfll_build_pwm_lut - build the PWM regulator lookup table + * @td: DFLL instance + * @v_max: Vmax from OPP table + * + * Look-up table in h/w is ignored when PWM is used as DFLL interface to PMIC. + * In this case closed loop output is controlling duty cycle directly. The s/w + * look-up that maps PWM duty cycle to voltage is still built by this function. + */ +static int dfll_build_pwm_lut(struct tegra_dfll *td, int v_max) +{ + int i, reg_volt; + unsigned long rate; + u8 lut_bottom = MAX_DFLL_VOLTAGES; + int v_min = td->soc->cvb->min_millivolts * 1000; + + for (i = 0; i < MAX_DFLL_VOLTAGES; i++) { + reg_volt = td->lut_uv[i]; + + /* since opp voltage is exact mv */ + reg_volt = (reg_volt / 1000) * 1000; + if (reg_volt > v_max) + break; + + td->lut[i] = i; + if ((lut_bottom == MAX_DFLL_VOLTAGES) && (reg_volt >= v_min)) + lut_bottom = i; + } + + /* determine voltage boundaries */ + td->lut_size = i; + if ((lut_bottom == MAX_DFLL_VOLTAGES) || + (lut_bottom + 1 >= td->lut_size)) { + dev_err(td->dev, "no voltage above DFLL minimum %d mV\n", + td->soc->cvb->min_millivolts); + return -EINVAL; + } + td->lut_bottom = lut_bottom; + + /* determine rate boundaries */ + rate = get_dvco_rate_below(td, td->lut_bottom); + if (!rate) { + dev_err(td->dev, "no opp below DFLL minimum voltage %d mV\n", + td->soc->cvb->min_millivolts); + return -EINVAL; + } + td->dvco_rate_min = rate; + + return 0; +} + /** * dfll_build_i2c_lut - build the I2C voltage register lookup table * @td: DFLL instance + * @v_max: Vmax from OPP table * * The DFLL hardware has 33 bytes of look-up table RAM that must be filled with * PMIC voltage register values that span the entire DFLL operating range. @@ -1397,33 +1632,26 @@ static int find_vdd_map_entry_min(struct tegra_dfll *td, int uV) * the soc-specific platform driver (td->soc->opp_dev) and the PMIC * register-to-voltage mapping queried from the regulator framework. * - * On success, fills in td->i2c_lut and returns 0, or -err on failure. + * On success, fills in td->lut and returns 0, or -err on failure. */ -static int dfll_build_i2c_lut(struct tegra_dfll *td) +static int dfll_build_i2c_lut(struct tegra_dfll *td, int v_max) { + unsigned long rate; int ret = -EINVAL; - int j, v, v_max, v_opp; + int j, v, v_opp; int selector; - unsigned long rate; - struct dev_pm_opp *opp; int lut; - rate = ULONG_MAX; - opp = dev_pm_opp_find_freq_floor(td->soc->dev, &rate); - if (IS_ERR(opp)) { - dev_err(td->dev, "couldn't get vmax opp, empty opp table?\n"); - goto out; - } - v_max = dev_pm_opp_get_voltage(opp); - dev_pm_opp_put(opp); - v = td->soc->cvb->min_millivolts * 1000; lut = find_vdd_map_entry_exact(td, v); if (lut < 0) goto out; - td->i2c_lut[0] = lut; + td->lut[0] = lut; + td->lut_bottom = 0; for (j = 1, rate = 0; ; rate++) { + struct dev_pm_opp *opp; + opp = dev_pm_opp_find_freq_ceil(td->soc->dev, &rate); if (IS_ERR(opp)) break; @@ -1442,32 +1670,58 @@ static int dfll_build_i2c_lut(struct tegra_dfll *td) selector = find_vdd_map_entry_min(td, v); if (selector < 0) goto out; - if (selector != td->i2c_lut[j - 1]) - td->i2c_lut[j++] = selector; + if (selector != td->lut[j - 1]) + td->lut[j++] = selector; } v = (j == MAX_DFLL_VOLTAGES - 1) ? v_max : v_opp; selector = find_vdd_map_entry_exact(td, v); if (selector < 0) goto out; - if (selector != td->i2c_lut[j - 1]) - td->i2c_lut[j++] = selector; + if (selector != td->lut[j - 1]) + td->lut[j++] = selector; if (v >= v_max) break; } - td->i2c_lut_size = j; + td->lut_size = j; if (!td->dvco_rate_min) dev_err(td->dev, "no opp above DFLL minimum voltage %d mV\n", td->soc->cvb->min_millivolts); - else + else { ret = 0; + for (j = 0; j < td->lut_size; j++) + td->lut_uv[j] = + regulator_list_voltage(td->vdd_reg, + td->lut[j]); + } out: return ret; } +static int dfll_build_lut(struct tegra_dfll *td) +{ + unsigned long rate; + struct dev_pm_opp *opp; + int v_max; + + rate = ULONG_MAX; + opp = dev_pm_opp_find_freq_floor(td->soc->dev, &rate); + if (IS_ERR(opp)) { + dev_err(td->dev, "couldn't get vmax opp, empty opp table?\n"); + return -EINVAL; + } + v_max = dev_pm_opp_get_voltage(opp); + dev_pm_opp_put(opp); + + if (td->pmu_if == TEGRA_DFLL_PMU_PWM) + return dfll_build_pwm_lut(td, v_max); + else + return dfll_build_i2c_lut(td, v_max); +} + /** * read_dt_param - helper function for reading required parameters from the DT * @td: DFLL instance @@ -1526,11 +1780,55 @@ static int dfll_fetch_i2c_params(struct tegra_dfll *td) } td->i2c_reg = vsel_reg; - ret = dfll_build_i2c_lut(td); - if (ret) { - dev_err(td->dev, "couldn't build I2C LUT\n"); + return 0; +} + +static int dfll_fetch_pwm_params(struct tegra_dfll *td) +{ + int ret, i; + u32 pwm_period; + + if (!td->soc->alignment.step_uv || !td->soc->alignment.offset_uv) { + dev_err(td->dev, + "Missing step or alignment info for PWM regulator"); + return -EINVAL; + } + for (i = 0; i < MAX_DFLL_VOLTAGES; i++) + td->lut_uv[i] = td->soc->alignment.offset_uv + + i * td->soc->alignment.step_uv; + + ret = read_dt_param(td, "nvidia,init-uv", &td->reg_init_uV); + if (!ret) { + dev_err(td->dev, "couldn't get initialized voltage\n"); + return ret; + } + + ret = read_dt_param(td, "nvidia,pwm-period", &pwm_period); + if (!ret) { + dev_err(td->dev, "couldn't get PWM period\n"); return ret; } + td->pwm_rate = (NSEC_PER_SEC / pwm_period) * (MAX_DFLL_VOLTAGES - 1); + + td->pwm_pin = devm_pinctrl_get(td->dev); + if (IS_ERR(td->pwm_pin)) { + dev_err(td->dev, "DT: missing pinctrl device\n"); + return PTR_ERR(td->pwm_pin); + } + + td->pwm_enable_state = pinctrl_lookup_state(td->pwm_pin, + "dvfs_pwm_enable"); + if (IS_ERR(td->pwm_enable_state)) { + dev_err(td->dev, "DT: missing pwm enabled state\n"); + return PTR_ERR(td->pwm_enable_state); + } + + td->pwm_disable_state = pinctrl_lookup_state(td->pwm_pin, + "dvfs_pwm_disable"); + if (IS_ERR(td->pwm_disable_state)) { + dev_err(td->dev, "DT: missing pwm disabled state\n"); + return PTR_ERR(td->pwm_disable_state); + } return 0; } @@ -1597,16 +1895,6 @@ int tegra_dfll_register(struct platform_device *pdev, td->soc = soc; - td->vdd_reg = devm_regulator_get(td->dev, "vdd-cpu"); - if (IS_ERR(td->vdd_reg)) { - ret = PTR_ERR(td->vdd_reg); - if (ret != -EPROBE_DEFER) - dev_err(td->dev, "couldn't get vdd_cpu regulator: %d\n", - ret); - - return ret; - } - td->dvco_rst = devm_reset_control_get(td->dev, "dvco"); if (IS_ERR(td->dvco_rst)) { dev_err(td->dev, "couldn't get dvco reset\n"); @@ -1619,10 +1907,27 @@ int tegra_dfll_register(struct platform_device *pdev, return ret; } - ret = dfll_fetch_i2c_params(td); + if (of_property_read_bool(td->dev->of_node, "nvidia,pwm-to-pmic")) { + td->pmu_if = TEGRA_DFLL_PMU_PWM; + ret = dfll_fetch_pwm_params(td); + } else { + td->vdd_reg = devm_regulator_get(td->dev, "vdd-cpu"); + if (IS_ERR(td->vdd_reg)) { + dev_err(td->dev, "couldn't get vdd_cpu regulator\n"); + return PTR_ERR(td->vdd_reg); + } + td->pmu_if = TEGRA_DFLL_PMU_I2C; + ret = dfll_fetch_i2c_params(td); + } if (ret) return ret; + ret = dfll_build_lut(td); + if (ret) { + dev_err(td->dev, "couldn't build LUT\n"); + return ret; + } + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!mem) { dev_err(td->dev, "no control register resource\n"); From patchwork Tue Dec 4 09:25:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 1007503 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="FOn/aDwe"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 438Ghv34zkz9s7W for ; Tue, 4 Dec 2018 20:26:55 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725613AbeLDJ0y (ORCPT ); Tue, 4 Dec 2018 04:26:54 -0500 Received: from hqemgate15.nvidia.com ([216.228.121.64]:19034 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725898AbeLDJ0y (ORCPT ); Tue, 4 Dec 2018 04:26:54 -0500 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 04 Dec 2018 01:26:53 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Tue, 04 Dec 2018 01:26:53 -0800 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Tue, 04 Dec 2018 01:26:53 -0800 Received: from HQMAIL102.nvidia.com (172.18.146.10) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 4 Dec 2018 09:26:53 +0000 Received: from HQMAIL103.nvidia.com (172.20.187.11) by HQMAIL102.nvidia.com (172.18.146.10) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 4 Dec 2018 09:26:53 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Tue, 4 Dec 2018 09:26:53 +0000 Received: from josephl-linux.nvidia.com (Not Verified[10.19.108.132]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 04 Dec 2018 01:26:52 -0800 From: Joseph Lo To: Thierry Reding , Peter De Schrijver , Jonathan Hunter CC: , , , Joseph Lo Subject: [PATCH 08/19] clk: tegra: dfll: round down voltages based on alignment Date: Tue, 4 Dec 2018 17:25:37 +0800 Message-ID: <20181204092548.3038-9-josephl@nvidia.com> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181204092548.3038-1-josephl@nvidia.com> References: <20181204092548.3038-1-josephl@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1543915613; bh=76SiM3Sn+CKXxnGOoZ1qarCkO2okk2A7hMW12Zz3zNE=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=FOn/aDweCHSUq4A7eXN0Yk2jGGZuW62H+EQFkH+DDwDH5uBaAQG79+zraSc/jGvID QBN/uHeV4cV4PrFnnD1zSP+X1M4kpSFWmK1Ztx3HNbi08v1pYp/f++9jUfT063RO3C IjkLf/ZMCbsp55yBjb+IMQPzIAcEt3tHJqC59qhCpkk5FMQAYwPLF19scRQb3X9LGo EkWfxNFuXx6lZAyiUdbpghNAk/AobUyl6Cf1yhqf018/sv1NYIPuOyAMV0t5zq4Njn MUQ4xTcT8qyComwN/Rca5/DxBwWPJ5m3fIoXomiIZ4O6u1y4U8tqQBM/yddob/PCO0 BjeIXETy4Ta0g== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org When generating the OPP table, the voltages are round down with the alignment from the regulator. The alignment should be applied for voltages look up as well. Based on the work of Penny Chiu . Signed-off-by: Joseph Lo --- drivers/clk/tegra/clk-dfll.c | 26 +++++++++++++++----------- 1 file changed, 15 insertions(+), 11 deletions(-) diff --git a/drivers/clk/tegra/clk-dfll.c b/drivers/clk/tegra/clk-dfll.c index c294a2989f31..4a943c136d4d 100644 --- a/drivers/clk/tegra/clk-dfll.c +++ b/drivers/clk/tegra/clk-dfll.c @@ -804,17 +804,17 @@ static void dfll_init_out_if(struct tegra_dfll *td) static int find_lut_index_for_rate(struct tegra_dfll *td, unsigned long rate) { struct dev_pm_opp *opp; - int i, uv; + int i, align_volt; opp = dev_pm_opp_find_freq_ceil(td->soc->dev, &rate); if (IS_ERR(opp)) return PTR_ERR(opp); - uv = dev_pm_opp_get_voltage(opp); + align_volt = dev_pm_opp_get_voltage(opp) / td->soc->alignment.step_uv; dev_pm_opp_put(opp); for (i = td->lut_bottom; i < td->lut_size; i++) { - if (regulator_list_voltage(td->vdd_reg, td->lut[i]) == uv) + if ((td->lut_uv[i] / td->soc->alignment.step_uv) >= align_volt) return i; } @@ -1532,15 +1532,17 @@ static int dfll_init(struct tegra_dfll *td) */ static int find_vdd_map_entry_exact(struct tegra_dfll *td, int uV) { - int i, n_voltages, reg_uV; + int i, n_voltages, reg_volt, align_volt; + align_volt = uV / td->soc->alignment.step_uv; n_voltages = regulator_count_voltages(td->vdd_reg); for (i = 0; i < n_voltages; i++) { - reg_uV = regulator_list_voltage(td->vdd_reg, i); - if (reg_uV < 0) + reg_volt = regulator_list_voltage(td->vdd_reg, i) / + td->soc->alignment.step_uv; + if (reg_volt < 0) break; - if (uV == reg_uV) + if (align_volt == reg_volt) return i; } @@ -1554,15 +1556,17 @@ static int find_vdd_map_entry_exact(struct tegra_dfll *td, int uV) * */ static int find_vdd_map_entry_min(struct tegra_dfll *td, int uV) { - int i, n_voltages, reg_uV; + int i, n_voltages, reg_volt, align_volt; + align_volt = uV / td->soc->alignment.step_uv; n_voltages = regulator_count_voltages(td->vdd_reg); for (i = 0; i < n_voltages; i++) { - reg_uV = regulator_list_voltage(td->vdd_reg, i); - if (reg_uV < 0) + reg_volt = regulator_list_voltage(td->vdd_reg, i) / + td->soc->alignment.step_uv; + if (reg_volt < 0) break; - if (uV <= reg_uV) + if (align_volt <= reg_volt) return i; } From patchwork Tue Dec 4 09:25:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 1007505 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="hqrgY54Q"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 438Ghz4xlnz9s7W for ; Tue, 4 Dec 2018 20:26:59 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725978AbeLDJ07 (ORCPT ); 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Tue, 04 Dec 2018 01:26:54 -0800 From: Joseph Lo To: Thierry Reding , Peter De Schrijver , Jonathan Hunter CC: , , , Joseph Lo Subject: [PATCH 09/19] clk: tegra: dfll: add CVB tables for Tegra210 Date: Tue, 4 Dec 2018 17:25:38 +0800 Message-ID: <20181204092548.3038-10-josephl@nvidia.com> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181204092548.3038-1-josephl@nvidia.com> References: <20181204092548.3038-1-josephl@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1543915615; bh=32gQCSi3rdD/JumyxHm5aUzRwX7rA7zwZkthzgmu/Lo=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=hqrgY54QxKbHZZq5vvxf0z/8//m5d/nr+9VOh4Ekg1mIJDCc0EfvD4/1oXlpKDipO lNtAwOa0xF6I5qe0XLdr6QeMknteRLociOB0tytEeDkSZE8bZYeSVmHerbr0qDM/5Z vwo5FQ23eQghHNtPodz03JEHpmiuW1eiPc8JiMisn0NCQztII8LkUhFWFvorTx7q+B FaZvLKfV8Yh4yfnytsat6vqZLqESD4W0mrYU2yOiFv7czncj4sWONFwMlc58vlUHaw a+1DvQCydRVTysrJ3rhNSMhyS+jyRYFX+eJC3mYiANXzpXuAwcLW1HqTMPdgbKKoM/ b+SBHYVg5kxOQ== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Add CVB tables with different chip characterization, so that we can generate the customize OPP table that suitable for different chips with different SKUs. Signed-off-by: Joseph Lo --- drivers/clk/tegra/clk-tegra124-dfll-fcpu.c | 426 +++++++++++++++++++++ drivers/clk/tegra/cvb.h | 1 + 2 files changed, 427 insertions(+) diff --git a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c b/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c index 071a5c674832..bc1358d8084b 100644 --- a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c +++ b/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c @@ -88,6 +88,421 @@ static const struct cvb_table tegra124_cpu_cvb_tables[] = { }, }; +static const unsigned long tegra210_cpu_max_freq_table[] = { + [0] = 1912500000UL, + [1] = 1912500000UL, + [2] = 2218500000UL, + [3] = 1785000000UL, + [4] = 1632000000UL, + [5] = 1912500000UL, + [6] = 2014500000UL, + [7] = 1734000000UL, + [8] = 1683000000UL, + [9] = 1555500000UL, + [10] = 1504500000UL, +}; + +#define CPU_CVB_TABLE \ + .speedo_scale = 100, \ + .voltage_scale = 1000, \ + .entries = { \ + { 204000000UL, { 1007452, -23865, 370 } }, \ + { 306000000UL, { 1052709, -24875, 370 } }, \ + { 408000000UL, { 1099069, -25895, 370 } }, \ + { 510000000UL, { 1146534, -26905, 370 } }, \ + { 612000000UL, { 1195102, -27915, 370 } }, \ + { 714000000UL, { 1244773, -28925, 370 } }, \ + { 816000000UL, { 1295549, -29935, 370 } }, \ + { 918000000UL, { 1347428, -30955, 370 } }, \ + { 1020000000UL, { 1400411, -31965, 370 } }, \ + { 1122000000UL, { 1454497, -32975, 370 } }, \ + { 1224000000UL, { 1509687, -33985, 370 } }, \ + { 1326000000UL, { 1565981, -35005, 370 } }, \ + { 1428000000UL, { 1623379, -36015, 370 } }, \ + { 1530000000UL, { 1681880, -37025, 370 } }, \ + { 1632000000UL, { 1741485, -38035, 370 } }, \ + { 1734000000UL, { 1802194, -39055, 370 } }, \ + { 1836000000UL, { 1864006, -40065, 370 } }, \ + { 1912500000UL, { 1910780, -40815, 370 } }, \ + { 2014500000UL, { 1227000, 0, 0 } }, \ + { 2218500000UL, { 1227000, 0, 0 } }, \ + { 0UL, { 0, 0, 0 } }, \ + } + +#define CPU_CVB_TABLE_XA \ + .speedo_scale = 100, \ + .voltage_scale = 1000, \ + .entries = { \ + { 204000000UL, { 1250024, -39785, 565 } }, \ + { 306000000UL, { 1297556, -41145, 565 } }, \ + { 408000000UL, { 1346718, -42505, 565 } }, \ + { 510000000UL, { 1397511, -43855, 565 } }, \ + { 612000000UL, { 1449933, -45215, 565 } }, \ + { 714000000UL, { 1503986, -46575, 565 } }, \ + { 816000000UL, { 1559669, -47935, 565 } }, \ + { 918000000UL, { 1616982, -49295, 565 } }, \ + { 1020000000UL, { 1675926, -50645, 565 } }, \ + { 1122000000UL, { 1736500, -52005, 565 } }, \ + { 1224000000UL, { 1798704, -53365, 565 } }, \ + { 1326000000UL, { 1862538, -54725, 565 } }, \ + { 1428000000UL, { 1928003, -56085, 565 } }, \ + { 1530000000UL, { 1995097, -57435, 565 } }, \ + { 1606500000UL, { 2046149, -58445, 565 } }, \ + { 1632000000UL, { 2063822, -58795, 565 } }, \ + { 0UL, { 0, 0, 0 } }, \ + } + +#define CPU_CVB_TABLE_EUCM1 \ + .speedo_scale = 100, \ + .voltage_scale = 1000, \ + .entries = { \ + { 204000000UL, { 734429, 0, 0 } }, \ + { 306000000UL, { 768191, 0, 0 } }, \ + { 408000000UL, { 801953, 0, 0 } }, \ + { 510000000UL, { 835715, 0, 0 } }, \ + { 612000000UL, { 869477, 0, 0 } }, \ + { 714000000UL, { 903239, 0, 0 } }, \ + { 816000000UL, { 937001, 0, 0 } }, \ + { 918000000UL, { 970763, 0, 0 } }, \ + { 1020000000UL, { 1004525, 0, 0 } }, \ + { 1122000000UL, { 1038287, 0, 0 } }, \ + { 1224000000UL, { 1072049, 0, 0 } }, \ + { 1326000000UL, { 1105811, 0, 0 } }, \ + { 1428000000UL, { 1130000, 0, 0 } }, \ + { 1555500000UL, { 1130000, 0, 0 } }, \ + { 1632000000UL, { 1170000, 0, 0 } }, \ + { 1734000000UL, { 1227500, 0, 0 } }, \ + { 0UL, { 0, 0, 0 } }, \ + } + +#define CPU_CVB_TABLE_EUCM2 \ + .speedo_scale = 100, \ + .voltage_scale = 1000, \ + .entries = { \ + { 204000000UL, { 742283, 0, 0 } }, \ + { 306000000UL, { 776249, 0, 0 } }, \ + { 408000000UL, { 810215, 0, 0 } }, \ + { 510000000UL, { 844181, 0, 0 } }, \ + { 612000000UL, { 878147, 0, 0 } }, \ + { 714000000UL, { 912113, 0, 0 } }, \ + { 816000000UL, { 946079, 0, 0 } }, \ + { 918000000UL, { 980045, 0, 0 } }, \ + { 1020000000UL, { 1014011, 0, 0 } }, \ + { 1122000000UL, { 1047977, 0, 0 } }, \ + { 1224000000UL, { 1081943, 0, 0 } }, \ + { 1326000000UL, { 1090000, 0, 0 } }, \ + { 1479000000UL, { 1090000, 0, 0 } }, \ + { 1555500000UL, { 1162000, 0, 0 } }, \ + { 1683000000UL, { 1195000, 0, 0 } }, \ + { 0UL, { 0, 0, 0 } }, \ + } + +#define CPU_CVB_TABLE_EUCM2_JOINT_RAIL \ + .speedo_scale = 100, \ + .voltage_scale = 1000, \ + .entries = { \ + { 204000000UL, { 742283, 0, 0 } }, \ + { 306000000UL, { 776249, 0, 0 } }, \ + { 408000000UL, { 810215, 0, 0 } }, \ + { 510000000UL, { 844181, 0, 0 } }, \ + { 612000000UL, { 878147, 0, 0 } }, \ + { 714000000UL, { 912113, 0, 0 } }, \ + { 816000000UL, { 946079, 0, 0 } }, \ + { 918000000UL, { 980045, 0, 0 } }, \ + { 1020000000UL, { 1014011, 0, 0 } }, \ + { 1122000000UL, { 1047977, 0, 0 } }, \ + { 1224000000UL, { 1081943, 0, 0 } }, \ + { 1326000000UL, { 1090000, 0, 0 } }, \ + { 1479000000UL, { 1090000, 0, 0 } }, \ + { 1504500000UL, { 1120000, 0, 0 } }, \ + { 0UL, { 0, 0, 0 } }, \ + } + +#define CPU_CVB_TABLE_ODN \ + .speedo_scale = 100, \ + .voltage_scale = 1000, \ + .entries = { \ + { 204000000UL, { 721094, 0, 0 } }, \ + { 306000000UL, { 754040, 0, 0 } }, \ + { 408000000UL, { 786986, 0, 0 } }, \ + { 510000000UL, { 819932, 0, 0 } }, \ + { 612000000UL, { 852878, 0, 0 } }, \ + { 714000000UL, { 885824, 0, 0 } }, \ + { 816000000UL, { 918770, 0, 0 } }, \ + { 918000000UL, { 915716, 0, 0 } }, \ + { 1020000000UL, { 984662, 0, 0 } }, \ + { 1122000000UL, { 1017608, 0, 0 } }, \ + { 1224000000UL, { 1050554, 0, 0 } }, \ + { 1326000000UL, { 1083500, 0, 0 } }, \ + { 1428000000UL, { 1116446, 0, 0 } }, \ + { 1581000000UL, { 1130000, 0, 0 } }, \ + { 1683000000UL, { 1168000, 0, 0 } }, \ + { 1785000000UL, { 1227500, 0, 0 } }, \ + { 0UL, { 0, 0, 0 } }, \ + } + +struct cvb_table tegra210_cpu_cvb_tables[] = { + { + .speedo_id = 10, + .process_id = 0, + .min_millivolts = 840, + .max_millivolts = 1120, + CPU_CVB_TABLE_EUCM2_JOINT_RAIL, + .cpu_dfll_data = { + .tune0_low = 0xffead0ff, + .tune0_high = 0xffead0ff, + .tune1 = 0x20091d9, + .tune_high_min_millivolts = 864, + } + }, + { + .speedo_id = 10, + .process_id = 1, + .min_millivolts = 840, + .max_millivolts = 1120, + CPU_CVB_TABLE_EUCM2_JOINT_RAIL, + .cpu_dfll_data = { + .tune0_low = 0xffead0ff, + .tune0_high = 0xffead0ff, + .tune1 = 0x20091d9, + .tune_high_min_millivolts = 864, + } + }, + { + .speedo_id = 9, + .process_id = 0, + .min_millivolts = 900, + .max_millivolts = 1162, + CPU_CVB_TABLE_EUCM2, + .cpu_dfll_data = { + .tune0_low = 0xffead0ff, + .tune0_high = 0xffead0ff, + .tune1 = 0x20091d9, + } + }, + { + .speedo_id = 9, + .process_id = 1, + .min_millivolts = 900, + .max_millivolts = 1162, + CPU_CVB_TABLE_EUCM2, + .cpu_dfll_data = { + .tune0_low = 0xffead0ff, + .tune0_high = 0xffead0ff, + .tune1 = 0x20091d9, + } + }, + { + .speedo_id = 8, + .process_id = 0, + .min_millivolts = 900, + .max_millivolts = 1195, + CPU_CVB_TABLE_EUCM2, + .cpu_dfll_data = { + .tune0_low = 0xffead0ff, + .tune0_high = 0xffead0ff, + .tune1 = 0x20091d9, + } + }, + { + .speedo_id = 8, + .process_id = 1, + .min_millivolts = 900, + .max_millivolts = 1195, + CPU_CVB_TABLE_EUCM2, + .cpu_dfll_data = { + .tune0_low = 0xffead0ff, + .tune0_high = 0xffead0ff, + .tune1 = 0x20091d9, + } + }, + { + .speedo_id = 7, + .process_id = 0, + .min_millivolts = 841, + .max_millivolts = 1227, + CPU_CVB_TABLE_EUCM1, + .cpu_dfll_data = { + .tune0_low = 0xffead0ff, + .tune0_high = 0xffead0ff, + .tune1 = 0x20091d9, + .tune_high_min_millivolts = 864, + } + }, + { + .speedo_id = 7, + .process_id = 1, + .min_millivolts = 841, + .max_millivolts = 1227, + CPU_CVB_TABLE_EUCM1, + .cpu_dfll_data = { + .tune0_low = 0xffead0ff, + .tune0_high = 0xffead0ff, + .tune1 = 0x20091d9, + .tune_high_min_millivolts = 864, + } + }, + { + .speedo_id = 6, + .process_id = 0, + .min_millivolts = 870, + .max_millivolts = 1150, + CPU_CVB_TABLE, + .cpu_dfll_data = { + .tune0_low = 0xffead0ff, + .tune1 = 0x20091d9, + } + }, + { + .speedo_id = 6, + .process_id = 1, + .min_millivolts = 870, + .max_millivolts = 1150, + CPU_CVB_TABLE, + .cpu_dfll_data = { + .tune0_low = 0xffead0ff, + .tune1 = 0x25501d0, + } + }, + { + .speedo_id = 5, + .process_id = 0, + .min_millivolts = 818, + .max_millivolts = 1227, + CPU_CVB_TABLE, + .cpu_dfll_data = { + .tune0_low = 0xffead0ff, + .tune0_high = 0xffead0ff, + .tune1 = 0x20091d9, + .tune_high_min_millivolts = 864, + } + }, + { + .speedo_id = 5, + .process_id = 1, + .min_millivolts = 818, + .max_millivolts = 1227, + CPU_CVB_TABLE, + .cpu_dfll_data = { + .tune0_low = 0xffead0ff, + .tune0_high = 0xffead0ff, + .tune1 = 0x25501d0, + .tune_high_min_millivolts = 864, + } + }, + { + .speedo_id = 4, + .process_id = -1, + .min_millivolts = 918, + .max_millivolts = 1113, + CPU_CVB_TABLE_XA, + .cpu_dfll_data = { + .tune0_low = 0xffead0ff, + .tune1 = 0x17711BD, + } + }, + { + .speedo_id = 3, + .process_id = 0, + .min_millivolts = 825, + .max_millivolts = 1227, + CPU_CVB_TABLE_ODN, + .cpu_dfll_data = { + .tune0_low = 0xffead0ff, + .tune0_high = 0xffead0ff, + .tune1 = 0x20091d9, + .tune_high_min_millivolts = 864, + } + }, + { + .speedo_id = 3, + .process_id = 1, + .min_millivolts = 825, + .max_millivolts = 1227, + CPU_CVB_TABLE_ODN, + .cpu_dfll_data = { + .tune0_low = 0xffead0ff, + .tune0_high = 0xffead0ff, + .tune1 = 0x25501d0, + .tune_high_min_millivolts = 864, + } + }, + { + .speedo_id = 2, + .process_id = 0, + .min_millivolts = 870, + .max_millivolts = 1227, + CPU_CVB_TABLE, + .cpu_dfll_data = { + .tune0_low = 0xffead0ff, + .tune1 = 0x20091d9, + } + }, + { + .speedo_id = 2, + .process_id = 1, + .min_millivolts = 870, + .max_millivolts = 1227, + CPU_CVB_TABLE, + .cpu_dfll_data = { + .tune0_low = 0xffead0ff, + .tune1 = 0x25501d0, + } + }, + { + .speedo_id = 1, + .process_id = 0, + .min_millivolts = 837, + .max_millivolts = 1227, + CPU_CVB_TABLE, + .cpu_dfll_data = { + .tune0_low = 0xffead0ff, + .tune0_high = 0xffead0ff, + .tune1 = 0x20091d9, + .tune_high_min_millivolts = 864, + } + }, + { + .speedo_id = 1, + .process_id = 1, + .min_millivolts = 837, + .max_millivolts = 1227, + CPU_CVB_TABLE, + .cpu_dfll_data = { + .tune0_low = 0xffead0ff, + .tune0_high = 0xffead0ff, + .tune1 = 0x25501d0, + .tune_high_min_millivolts = 864, + } + }, + { + .speedo_id = 0, + .process_id = 0, + .min_millivolts = 850, + .max_millivolts = 1170, + CPU_CVB_TABLE, + .cpu_dfll_data = { + .tune0_low = 0xffead0ff, + .tune0_high = 0xffead0ff, + .tune1 = 0x20091d9, + .tune_high_min_millivolts = 864, + } + }, + { + .speedo_id = 0, + .process_id = 1, + .min_millivolts = 850, + .max_millivolts = 1170, + CPU_CVB_TABLE, + .cpu_dfll_data = { + .tune0_low = 0xffead0ff, + .tune0_high = 0xffead0ff, + .tune1 = 0x25501d0, + .tune_high_min_millivolts = 864, + } + }, +}; + static const struct dfll_fcpu_data tegra124_dfll_fcpu_data = { .cpu_max_freq_table = tegra124_cpu_max_freq_table, .cpu_max_freq_table_size = ARRAY_SIZE(tegra124_cpu_max_freq_table), @@ -95,11 +510,22 @@ static const struct dfll_fcpu_data tegra124_dfll_fcpu_data = { .cpu_cvb_tables_size = ARRAY_SIZE(tegra124_cpu_cvb_tables) }; +static const struct dfll_fcpu_data tegra210_dfll_fcpu_data = { + .cpu_max_freq_table = tegra210_cpu_max_freq_table, + .cpu_max_freq_table_size = ARRAY_SIZE(tegra210_cpu_max_freq_table), + .cpu_cvb_tables = tegra210_cpu_cvb_tables, + .cpu_cvb_tables_size = ARRAY_SIZE(tegra210_cpu_cvb_tables), +}; + static const struct of_device_id tegra124_dfll_fcpu_of_match[] = { { .compatible = "nvidia,tegra124-dfll", .data = &tegra124_dfll_fcpu_data, }, + { + .compatible = "nvidia,tegra210-dfll", + .data = &tegra210_dfll_fcpu_data + }, { }, }; diff --git a/drivers/clk/tegra/cvb.h b/drivers/clk/tegra/cvb.h index bcf15a089b93..91a1941c21ef 100644 --- a/drivers/clk/tegra/cvb.h +++ b/drivers/clk/tegra/cvb.h @@ -41,6 +41,7 @@ struct cvb_cpu_dfll_data { u32 tune0_low; u32 tune0_high; u32 tune1; + unsigned int tune_high_min_millivolts; }; struct cvb_table { From patchwork Tue Dec 4 09:25:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 1007504 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="Z5UCCHdu"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 438Ghy6mZMz9s55 for ; Tue, 4 Dec 2018 20:26:58 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725767AbeLDJ06 (ORCPT ); Tue, 4 Dec 2018 04:26:58 -0500 Received: from hqemgate16.nvidia.com ([216.228.121.65]:4065 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725957AbeLDJ06 (ORCPT ); Tue, 4 Dec 2018 04:26:58 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 04 Dec 2018 01:26:59 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 04 Dec 2018 01:26:57 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 04 Dec 2018 01:26:57 -0800 Received: from HQMAIL106.nvidia.com (172.18.146.12) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 4 Dec 2018 09:26:56 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Tue, 4 Dec 2018 09:26:57 +0000 Received: from josephl-linux.nvidia.com (Not Verified[10.19.108.132]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 04 Dec 2018 01:26:57 -0800 From: Joseph Lo To: Thierry Reding , Peter De Schrijver , Jonathan Hunter CC: , , , Joseph Lo Subject: [PATCH 10/19] clk: tegra: dfll: build clk-dfll.c for Tegra124 and Tegra210 Date: Tue, 4 Dec 2018 17:25:39 +0800 Message-ID: <20181204092548.3038-11-josephl@nvidia.com> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181204092548.3038-1-josephl@nvidia.com> References: <20181204092548.3038-1-josephl@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1543915619; bh=2WMlVwdYaQNvFt9k9dlLEzyBuIg4itEIC2FIiuGVzUk=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=Z5UCCHduEPjtYGIgNSwYDAUC6ApB+JvyGkZAoE70tqaT1ZIylDAMMvSj6i4M2F4Bh aVAaU5ywuRVfOuEMBvhJPiCkh/dfi0u+Am7XRBo5n9RdGlLhN717Hky6uwuxmV9rcH e5hgeWR7FxSMJpyri4ZXvrYRBzQ/8dKjUxjrSH6heboAPFj7D5iSX94GamJ/iClQLH of9qSzqn61luiiwwbjePP43hJG4B+mv3inBwhMTVgAtwg2DcRwIxvgOPkRiEXRu0FK P17zTxp3xRiRI5HpKBzfHPTit9NE5BsprgZQZOUwzp5pUnag8MeIbb3mg7JewkTktG EnBLg/eaNKfFg== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Peter De Schrijver Tegra210 has a DFLL as well and can share the majority of the code with the Tegra124 implementation. So build the same code for both platforms. Signed-off-by: Peter De Schrijver Signed-off-by: Joseph Lo Acked-by: Jon Hunter --- drivers/clk/tegra/Kconfig | 5 +++++ drivers/clk/tegra/Makefile | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/clk/tegra/Kconfig b/drivers/clk/tegra/Kconfig index 7ddacae5d0b1..57902ab43f4a 100644 --- a/drivers/clk/tegra/Kconfig +++ b/drivers/clk/tegra/Kconfig @@ -5,3 +5,8 @@ config TEGRA_CLK_EMC config CLK_TEGRA_BPMP def_bool y depends on TEGRA_BPMP + +config TEGRA_CLK_DFLL + depends on (ARCH_TEGRA_124_SOC || ARCH_TEGRA_210_SOC) + select PM_OPP + def_bool y diff --git a/drivers/clk/tegra/Makefile b/drivers/clk/tegra/Makefile index 6507acc843c7..4812e45c2214 100644 --- a/drivers/clk/tegra/Makefile +++ b/drivers/clk/tegra/Makefile @@ -20,7 +20,7 @@ obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += clk-tegra20.o obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += clk-tegra30.o obj-$(CONFIG_ARCH_TEGRA_114_SOC) += clk-tegra114.o obj-$(CONFIG_ARCH_TEGRA_124_SOC) += clk-tegra124.o -obj-$(CONFIG_ARCH_TEGRA_124_SOC) += clk-tegra124-dfll-fcpu.o +obj-$(CONFIG_TEGRA_CLK_DFLL) += clk-tegra124-dfll-fcpu.o obj-$(CONFIG_ARCH_TEGRA_132_SOC) += clk-tegra124.o obj-y += cvb.o obj-$(CONFIG_ARCH_TEGRA_210_SOC) += clk-tegra210.o From patchwork Tue Dec 4 09:25:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 1007506 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="Jd+uUEYv"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 438Gj30xwxz9s55 for ; Tue, 4 Dec 2018 20:27:03 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725979AbeLDJ1C (ORCPT ); Tue, 4 Dec 2018 04:27:02 -0500 Received: from hqemgate16.nvidia.com ([216.228.121.65]:4069 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725898AbeLDJ1C (ORCPT ); Tue, 4 Dec 2018 04:27:02 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 04 Dec 2018 01:27:02 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 04 Dec 2018 01:27:00 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 04 Dec 2018 01:27:00 -0800 Received: from HQMAIL110.nvidia.com (172.18.146.15) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 4 Dec 2018 09:27:00 +0000 Received: from HQMAIL106.nvidia.com (172.18.146.12) by hqmail110.nvidia.com (172.18.146.15) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 4 Dec 2018 09:26:59 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Tue, 4 Dec 2018 09:26:59 +0000 Received: from josephl-linux.nvidia.com (Not Verified[10.19.108.132]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 04 Dec 2018 01:26:59 -0800 From: Joseph Lo To: Thierry Reding , Peter De Schrijver , Jonathan Hunter CC: , , , Joseph Lo , Viresh Kumar , Subject: [PATCH 11/19] cpufreq: tegra124: do not handle the CPU rail Date: Tue, 4 Dec 2018 17:25:40 +0800 Message-ID: <20181204092548.3038-12-josephl@nvidia.com> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181204092548.3038-1-josephl@nvidia.com> References: <20181204092548.3038-1-josephl@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1543915622; bh=keK1cFRn89M3cmuIffiAPACzFEXeNYnLBLsdkkMVf14=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=Jd+uUEYvcxJq3OU88H3tbNTlHTaVCEMqDNSjyQujoU4J09+7ZmWys6r9nmvO1ankt 9ftaPNTEfkFlGxe30ofdCPM69HLkOv9Sd26hDDUz6ch6R3NAN7VMMMdeBz86xEO9px 7wfygFfoNDmRl8oMk/+o2eNpWISvZjrp1Z4kTbX1xbPCali+GRLXFJkQpf3JrLTgP8 9y3nt1nO3BfRscqExQ2ImTRVADyLuRLY8dVSpJVsOtAYmKZsDhXYRggWIWYEWcnvoM Ph+Pyl4pso+jH6LvCAu59YRh++mERFAY9zVmxdMoIifoek+Jtz4DGz3XkT/IlKGTo1 p+SE1/TCDyNzg== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org The Tegra124 cpufreq driver has no information to handle the Vdd-CPU rail. So the driver shouldn't handle for the CPU clock switching from DFLL to other PLL clocks. It was designed to work on DFLL clock only, which handle the frequency/voltage scaling in the background. This patch removes the driver dependency of the CPU rail. Cc: Viresh Kumar Cc: linux-pm@vger.kernel.org Signed-off-by: Joseph Lo --- drivers/cpufreq/Kconfig.arm | 2 +- drivers/cpufreq/tegra124-cpufreq.c | 26 ++------------------------ 2 files changed, 3 insertions(+), 25 deletions(-) diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm index 4e1131ef85ae..a609f8820c47 100644 --- a/drivers/cpufreq/Kconfig.arm +++ b/drivers/cpufreq/Kconfig.arm @@ -262,7 +262,7 @@ config ARM_TEGRA20_CPUFREQ config ARM_TEGRA124_CPUFREQ tristate "Tegra124 CPUFreq support" - depends on ARCH_TEGRA && CPUFREQ_DT && REGULATOR + depends on ARCH_TEGRA && CPUFREQ_DT default y help This adds the CPUFreq driver support for Tegra124 SOCs. diff --git a/drivers/cpufreq/tegra124-cpufreq.c b/drivers/cpufreq/tegra124-cpufreq.c index 43530254201a..448d00763d00 100644 --- a/drivers/cpufreq/tegra124-cpufreq.c +++ b/drivers/cpufreq/tegra124-cpufreq.c @@ -22,11 +22,9 @@ #include #include #include -#include #include struct tegra124_cpufreq_priv { - struct regulator *vdd_cpu_reg; struct clk *cpu_clk; struct clk *pllp_clk; struct clk *pllx_clk; @@ -60,14 +58,6 @@ static int tegra124_cpu_switch_to_dfll(struct tegra124_cpufreq_priv *priv) return ret; } -static void tegra124_cpu_switch_to_pllx(struct tegra124_cpufreq_priv *priv) -{ - clk_set_parent(priv->cpu_clk, priv->pllp_clk); - clk_disable_unprepare(priv->dfll_clk); - regulator_sync_voltage(priv->vdd_cpu_reg); - clk_set_parent(priv->cpu_clk, priv->pllx_clk); -} - static int tegra124_cpufreq_probe(struct platform_device *pdev) { struct tegra124_cpufreq_priv *priv; @@ -88,16 +78,10 @@ static int tegra124_cpufreq_probe(struct platform_device *pdev) if (!np) return -ENODEV; - priv->vdd_cpu_reg = regulator_get(cpu_dev, "vdd-cpu"); - if (IS_ERR(priv->vdd_cpu_reg)) { - ret = PTR_ERR(priv->vdd_cpu_reg); - goto out_put_np; - } - priv->cpu_clk = of_clk_get_by_name(np, "cpu_g"); if (IS_ERR(priv->cpu_clk)) { ret = PTR_ERR(priv->cpu_clk); - goto out_put_vdd_cpu_reg; + goto out_put_np; } priv->dfll_clk = of_clk_get_by_name(np, "dfll"); @@ -129,15 +113,13 @@ static int tegra124_cpufreq_probe(struct platform_device *pdev) platform_device_register_full(&cpufreq_dt_devinfo); if (IS_ERR(priv->cpufreq_dt_pdev)) { ret = PTR_ERR(priv->cpufreq_dt_pdev); - goto out_switch_to_pllx; + goto out_put_pllp_clk; } platform_set_drvdata(pdev, priv); return 0; -out_switch_to_pllx: - tegra124_cpu_switch_to_pllx(priv); out_put_pllp_clk: clk_put(priv->pllp_clk); out_put_pllx_clk: @@ -146,8 +128,6 @@ static int tegra124_cpufreq_probe(struct platform_device *pdev) clk_put(priv->dfll_clk); out_put_cpu_clk: clk_put(priv->cpu_clk); -out_put_vdd_cpu_reg: - regulator_put(priv->vdd_cpu_reg); out_put_np: of_node_put(np); @@ -159,13 +139,11 @@ static int tegra124_cpufreq_remove(struct platform_device *pdev) struct tegra124_cpufreq_priv *priv = platform_get_drvdata(pdev); platform_device_unregister(priv->cpufreq_dt_pdev); - tegra124_cpu_switch_to_pllx(priv); clk_put(priv->pllp_clk); clk_put(priv->pllx_clk); clk_put(priv->dfll_clk); clk_put(priv->cpu_clk); - regulator_put(priv->vdd_cpu_reg); return 0; } From patchwork Tue Dec 4 09:25:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 1007507 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="nORrykIb"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 438Gj41msQz9s55 for ; Tue, 4 Dec 2018 20:27:04 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725989AbeLDJ1D (ORCPT ); Tue, 4 Dec 2018 04:27:03 -0500 Received: from hqemgate15.nvidia.com ([216.228.121.64]:19053 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725898AbeLDJ1D (ORCPT ); Tue, 4 Dec 2018 04:27:03 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 04 Dec 2018 01:27:02 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 04 Dec 2018 01:27:02 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 04 Dec 2018 01:27:02 -0800 Received: from HQMAIL112.nvidia.com (172.18.146.18) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 4 Dec 2018 09:27:02 +0000 Received: from HQMAIL103.nvidia.com (172.20.187.11) by HQMAIL112.nvidia.com (172.18.146.18) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 4 Dec 2018 09:27:02 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Tue, 4 Dec 2018 09:27:02 +0000 Received: from josephl-linux.nvidia.com (Not Verified[10.19.108.132]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 04 Dec 2018 01:27:02 -0800 From: Joseph Lo To: Thierry Reding , Peter De Schrijver , Jonathan Hunter CC: , , , Joseph Lo , Viresh Kumar , Subject: [PATCH 12/19] cpufreq: tegra124: extend to support Tegra210 Date: Tue, 4 Dec 2018 17:25:41 +0800 Message-ID: <20181204092548.3038-13-josephl@nvidia.com> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181204092548.3038-1-josephl@nvidia.com> References: <20181204092548.3038-1-josephl@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1543915622; bh=PUqZqvwOmEG3dp1ozyzqvKGj8MSy9Znu2Zs9DfS61YA=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=nORrykIbh3S1kzNHkMcqeOitwXoRZDCfzA4yWirWamhbCsAPLRYsByMcx54rdGDXi jTbjxzlth/rl09mM3kEUfRf8xVVf0rtMd7ed5mGuQ/2l8DULq1Ymf7jcFYldln1Ps3 qvQjmM6gG6LufbjMpkGgpgVej9UkgpXrACH2WBHVf1G7zSrGgm9GDyMATE+RzyCXQQ 2EyjZFIncLj4WVL9RYf40xSUrukz7OrQ5WduaGM08AKnpICIKAnvCi7T0ieqq6mtlJ 4zsbzvzSIu6PbvO9pEBp7OvjkvUeDyggBesQR92Q2VPVTYVr+PHu3mMEOVGjdIPeMs SdhDZCROmygGg== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Tegra210 uses the same methodology as Tegra124 for CPUFreq controlling that based on DFLL clock. So extending this driver to support Tegra210. Cc: Viresh Kumar Cc: linux-pm@vger.kernel.org Signed-off-by: Joseph Lo Acked-by: Viresh Kumar Acked-by: Jon Hunter --- drivers/cpufreq/tegra124-cpufreq.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/cpufreq/tegra124-cpufreq.c b/drivers/cpufreq/tegra124-cpufreq.c index 448d00763d00..1af955fb715c 100644 --- a/drivers/cpufreq/tegra124-cpufreq.c +++ b/drivers/cpufreq/tegra124-cpufreq.c @@ -159,7 +159,8 @@ static int __init tegra_cpufreq_init(void) int ret; struct platform_device *pdev; - if (!of_machine_is_compatible("nvidia,tegra124")) + if (!(of_machine_is_compatible("nvidia,tegra124") || + of_machine_is_compatible("nvidia,tegra210"))) return -ENODEV; /* From patchwork Tue Dec 4 09:25:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 1007508 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="SSkXZSQ2"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 438Gj61w89z9s55 for ; Tue, 4 Dec 2018 20:27:06 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725998AbeLDJ1F (ORCPT ); Tue, 4 Dec 2018 04:27:05 -0500 Received: from hqemgate16.nvidia.com ([216.228.121.65]:4075 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725996AbeLDJ1F (ORCPT ); Tue, 4 Dec 2018 04:27:05 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 04 Dec 2018 01:27:07 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 04 Dec 2018 01:27:04 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 04 Dec 2018 01:27:04 -0800 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 4 Dec 2018 09:27:04 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Tue, 4 Dec 2018 09:27:04 +0000 Received: from josephl-linux.nvidia.com (Not Verified[10.19.108.132]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 04 Dec 2018 01:27:04 -0800 From: Joseph Lo To: Thierry Reding , Peter De Schrijver , Jonathan Hunter CC: , , , Joseph Lo Subject: [PATCH 13/19] arm64: dts: tegra210: add DFLL clock Date: Tue, 4 Dec 2018 17:25:42 +0800 Message-ID: <20181204092548.3038-14-josephl@nvidia.com> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181204092548.3038-1-josephl@nvidia.com> References: <20181204092548.3038-1-josephl@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1543915627; bh=0iBfIoTpjMNvTe2HiUitSTQD9qacFKjCr8+8R9poNCk=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=SSkXZSQ2ZsimgKoNgScXLZ7XpKQVdO2Xl4319RiUTqPIfdtxqVno7oj6LXXsfGNQf K4lPY+XI9SB415QCkr8y6yssJnneY8VNxQoNs9VTSY1JVQb+GJ7C/ZxZhx4n1vyTZe CVgTkZ19ADbCCb1qICJo39arSy6j34Dki4wZHso8RZtPz24hDsFbaMfwzGkYoyUd7A gHBzQKXhUrfn31t/llAxDckEKETqsgaR6w+FFxaGg6+x1i3KHlT/kijU198YzxPKvY yFSTMa0IzEsN3ThcY2VVYuD5XkrhUFtxhVSkElfVdhm8LsdJD/Q4qDZesQCxf1njgA 56T1Fq6WaW4Eg== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Add essential DFLL clock properties for Tegra210. Signed-off-by: Joseph Lo Acked-by: Jon Hunter --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 2205d66b0443..a6db62157442 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -4,6 +4,7 @@ #include #include #include +#include #include #include @@ -1131,6 +1132,24 @@ #nvidia,mipi-calibrate-cells = <1>; }; + dfll: clock@70110000 { + compatible = "nvidia,tegra210-dfll"; + reg = <0 0x70110000 0 0x100>, /* DFLL control */ + <0 0x70110000 0 0x100>, /* I2C output control */ + <0 0x70110100 0 0x100>, /* Integrated I2C controller */ + <0 0x70110200 0 0x100>; /* Look-up table RAM */ + interrupts = ; + clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>, + <&tegra_car TEGRA210_CLK_DFLL_REF>, + <&tegra_car TEGRA210_CLK_I2C5>; + clock-names = "soc", "ref", "i2c"; + resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>; + reset-names = "dvco"; + #clock-cells = <0>; + clock-output-names = "dfllCPU_out"; + status = "disabled"; + }; + aconnect@702c0000 { compatible = "nvidia,tegra210-aconnect"; clocks = <&tegra_car TEGRA210_CLK_APE>, From patchwork Tue Dec 4 09:25:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 1007509 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="NypVPskb"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 438GjB2CpDz9s55 for ; Tue, 4 Dec 2018 20:27:10 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725999AbeLDJ1K (ORCPT ); Tue, 4 Dec 2018 04:27:10 -0500 Received: from hqemgate15.nvidia.com ([216.228.121.64]:19071 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725996AbeLDJ1J (ORCPT ); Tue, 4 Dec 2018 04:27:09 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 04 Dec 2018 01:27:08 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 04 Dec 2018 01:27:09 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 04 Dec 2018 01:27:09 -0800 Received: from HQMAIL112.nvidia.com (172.18.146.18) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 4 Dec 2018 09:27:08 +0000 Received: from HQMAIL104.nvidia.com (172.18.146.11) by HQMAIL112.nvidia.com (172.18.146.18) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 4 Dec 2018 09:27:08 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Tue, 4 Dec 2018 09:27:08 +0000 Received: from josephl-linux.nvidia.com (Not Verified[10.19.108.132]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 04 Dec 2018 01:27:06 -0800 From: Joseph Lo To: Thierry Reding , Peter De Schrijver , Jonathan Hunter CC: , , , Joseph Lo Subject: [PATCH 14/19] arm64: dts: tegra210: add CPU clocks Date: Tue, 4 Dec 2018 17:25:43 +0800 Message-ID: <20181204092548.3038-15-josephl@nvidia.com> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181204092548.3038-1-josephl@nvidia.com> References: <20181204092548.3038-1-josephl@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1543915628; bh=Hydh+fdd1CB8y+XWjmPQC692LZY2Bym/yEIWKRQQvhU=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=NypVPskbmtm1UyCrBj6pPfQZRIzyXvw/+ixFcj9OG0mpHsKvkxSsHeLiFHk3U4mbX 7MqCZRELvz/pkIW2IYJHtSn0HmOlErjOjZyLVxErA5/+zY3C/BmVP8Q3TtodbCLnso mZmNMxXxJs5x/czg+OMG6GsUp1cKEG1y6QuHxFbUwIqnn58P7bChG2RFbwC6Aeajgm h0+cAkEAer25sb0KQZTtnRKdH5dv54ZQXVIphb6F4dhSL4OFJ24A+p1MBYDpTXMTtk JySlhQDbQ5s9ASIr665atJTQ2GznUJ8WmNCDcjpIzvoAnJyzeXOo4jgnLopda3X+b4 f92qup9P8TOQA== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Add CPU clocks for Tegra210. Signed-off-by: Joseph Lo Acked-by: Jon Hunter --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index a6db62157442..e2baf52fe1af 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -1304,6 +1304,12 @@ device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <0>; + clocks = <&tegra_car TEGRA210_CLK_CCLK_G>, + <&tegra_car TEGRA210_CLK_PLL_X>, + <&tegra_car TEGRA210_CLK_PLL_P_OUT4>, + <&dfll>; + clock-names = "cpu_g", "pll_x", "pll_p", "dfll"; + clock-latency = <300000>; }; cpu@1 { From patchwork Tue Dec 4 09:25:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 1007510 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="E3eOWFJZ"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 438GjC56CLz9s7W for ; Tue, 4 Dec 2018 20:27:11 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726003AbeLDJ1L (ORCPT ); Tue, 4 Dec 2018 04:27:11 -0500 Received: from hqemgate16.nvidia.com ([216.228.121.65]:4082 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725996AbeLDJ1L (ORCPT ); Tue, 4 Dec 2018 04:27:11 -0500 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 04 Dec 2018 01:27:12 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Tue, 04 Dec 2018 01:27:10 -0800 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Tue, 04 Dec 2018 01:27:10 -0800 Received: from HQMAIL112.nvidia.com (172.18.146.18) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 4 Dec 2018 09:27:10 +0000 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL112.nvidia.com (172.18.146.18) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 4 Dec 2018 09:27:09 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Tue, 4 Dec 2018 09:27:09 +0000 Received: from josephl-linux.nvidia.com (Not Verified[10.19.108.132]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 04 Dec 2018 01:27:09 -0800 From: Joseph Lo To: Thierry Reding , Peter De Schrijver , Jonathan Hunter CC: , , , Joseph Lo Subject: [PATCH 15/19] arm64: dts: tegra210-p2597: add pinmux for PWM-based DFLL support Date: Tue, 4 Dec 2018 17:25:44 +0800 Message-ID: <20181204092548.3038-16-josephl@nvidia.com> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181204092548.3038-1-josephl@nvidia.com> References: <20181204092548.3038-1-josephl@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1543915632; bh=KepNCfBPnU5ZiDktGsOR/RVGKY4GGdZXvAy6lpDbQD8=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=E3eOWFJZmHZdp7ey5fZUjE1Nan/iEBxbslX8eJOjM0ApjRc9BbGNSwSfeRUMaNH1q NAzlAWiOq7zlGVxhq2QeZ2p3Wo3+ngASL5B0kxmws53LgHUfhu4c7NKxucRJyddcS7 cYOOZl2L3/iDle5fCbTfxPSod/aAeZxvIACHp8K3arMecnl5v6JrxU8/ltBe0+8Lhw 339iAnTnc9vconf4G3AxHLNpvEzasR4pLfZDqz/UDdkBQwzI3GPZ9fTrxM/VytSCr6 Oyu16fnvdn7uIX6U/fxdF/5VEeDTichieLudBXWVlVHOfKpKwBywTQu7h7W0kTsy0L u9Beqk4dMzP2g== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Add pinmux for PWM-based DFLL support. Signed-off-by: Joseph Lo Acked-by: Jon Hunter --- arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi index 365726ddd418..db5dc0ad466d 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi @@ -1278,6 +1278,20 @@ nvidia,open-drain = ; }; }; + + dvfs_pwm_active_state: dvfs_pwm_active { + dvfs_pwm_pbb1 { + nvidia,pins = "dvfs_pwm_pbb1"; + nvidia,tristate = ; + }; + }; + + dvfs_pwm_inactive_state: dvfs_pwm_inactive { + dvfs_pwm_pbb1 { + nvidia,pins = "dvfs_pwm_pbb1"; + nvidia,tristate = ; + }; + }; }; pwm@7000a000 { From patchwork Tue Dec 4 09:25:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 1007511 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="L/M/Sj8y"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 438GjF24G6z9s55 for ; Tue, 4 Dec 2018 20:27:13 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725996AbeLDJ1N (ORCPT ); Tue, 4 Dec 2018 04:27:13 -0500 Received: from hqemgate14.nvidia.com ([216.228.121.143]:3734 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725898AbeLDJ1M (ORCPT ); Tue, 4 Dec 2018 04:27:12 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 04 Dec 2018 01:27:11 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 04 Dec 2018 01:27:12 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 04 Dec 2018 01:27:12 -0800 Received: from HQMAIL102.nvidia.com (172.18.146.10) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 4 Dec 2018 09:27:11 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL102.nvidia.com (172.18.146.10) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Tue, 4 Dec 2018 09:27:11 +0000 Received: from josephl-linux.nvidia.com (Not Verified[10.19.108.132]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 04 Dec 2018 01:27:11 -0800 From: Joseph Lo To: Thierry Reding , Peter De Schrijver , Jonathan Hunter CC: , , , Joseph Lo Subject: [PATCH 16/19] arm64: dts: tegra210-p2371-2180: enable DFLL clock Date: Tue, 4 Dec 2018 17:25:45 +0800 Message-ID: <20181204092548.3038-17-josephl@nvidia.com> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181204092548.3038-1-josephl@nvidia.com> References: <20181204092548.3038-1-josephl@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1543915631; bh=kpTaO/fqNYDNOAC7geVVmnzlQpoAANJs9ytAihdlyS8=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=L/M/Sj8ynTEjWxtRYYC+DvSLPLqJIwVBR/+z2+5YgHvDfCie3hWgOP5s9hG9bSAKF DMsO1Z/OlMGKiFT0KmdaIyXdDeQd5Oef0UgfT/UVn13djqTfIvgKXRIUbrPEFV4U9o YMULr8dWNgvVpj6WP8m5emlQn6mCyg7KTySmVmmfj3XxFWdPMAJob3dBrz4jqI27j8 L8cTyLoFwwaSgyeSuMpOIi/b1dxJfACPjl/CRwfCFG/iAfUYpJlExn4Xnrtr3TqeLz 5FT+QafRII6Mfg4Cne34+oc2wldACI4JTZvh5WddXmfnbt4n6nXdZLejOulqGw7tia pYnJoak+8bVVA== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Enable DFLL clock for Jetson TX1 platform. Signed-off-by: Joseph Lo --- .../boot/dts/nvidia/tegra210-p2371-2180.dts | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts index 37e3c46e753f..53f497c2b3ff 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts @@ -78,4 +78,24 @@ }; }; }; + + clock@70110000 { + status = "okay"; + nvidia,pwm-to-pmic; + nvidia,init-uv = <1000000>; + nvidia,align-offset-uv = <708000>; + nvidia,align-step-uv = <19200>; + nvidia,sample-rate = <25000>; + nvidia,droop-ctrl = <0x00000f00>; + nvidia,force-mode = <1>; + nvidia,cf = <6>; + nvidia,ci = <0>; + nvidia,cg = <2>; + nvidia,idle-override; + nvidia,one-shot-calibrate; + nvidia,pwm-period = <2500>; /* 2.5us */ + pinctrl-names = "dvfs_pwm_enable", "dvfs_pwm_disable"; + pinctrl-0 = <&dvfs_pwm_active_state>; + pinctrl-1 = <&dvfs_pwm_inactive_state>; + }; }; From patchwork Tue Dec 4 09:25:46 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 1007512 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="VAMOz7eq"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 438GjH21tyz9s55 for ; Tue, 4 Dec 2018 20:27:15 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726006AbeLDJ1O (ORCPT ); Tue, 4 Dec 2018 04:27:14 -0500 Received: from hqemgate14.nvidia.com ([216.228.121.143]:3738 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725898AbeLDJ1O (ORCPT ); Tue, 4 Dec 2018 04:27:14 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 04 Dec 2018 01:27:13 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 04 Dec 2018 01:27:14 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 04 Dec 2018 01:27:14 -0800 Received: from HQMAIL106.nvidia.com (172.18.146.12) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 4 Dec 2018 09:27:13 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Tue, 4 Dec 2018 09:27:13 +0000 Received: from josephl-linux.nvidia.com (Not Verified[10.19.108.132]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 04 Dec 2018 01:27:13 -0800 From: Joseph Lo To: Thierry Reding , Peter De Schrijver , Jonathan Hunter CC: , , , Joseph Lo Subject: [PATCH 17/19] arm64: dts: tegra210-smaug: add CPU power rail regulator Date: Tue, 4 Dec 2018 17:25:46 +0800 Message-ID: <20181204092548.3038-18-josephl@nvidia.com> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181204092548.3038-1-josephl@nvidia.com> References: <20181204092548.3038-1-josephl@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1543915633; bh=37UJgg+Sk0f+mVmsOgZriZGkBps4DIlrQrAyeAWRxnA=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=VAMOz7eqaxBxVKYW4FR83jA0Pf+HUF5ZA3pRbroxCgLQItANrtsNdkGAbTImJ05ik UW4PkEzMXdEsxnwtuG4rFfy/yMJJ0fgadJulUFNRSFzCWwSdEpcaPhk3MpMahbjhsp t9+wN3BynMGEGdk+zhBx/86RESeOdrNMduM2hb24DFYb5/AwCsJqm9pJh38twRwM3a XMb5Ox6bRpAS4kRwPnfo0mYIZ7SIIUX7K6tW8XcGFWZ/S1rzODETeE1g9bJDAoe/qy Ln9y35IabNzdxLBDN5Oblz1pEbHM4X9kdzHncWNmi1/I8PYrMC8ujuSr1z1tZ96U75 iEgY2Yz27U7sA== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Add CPU power rail regulator for Smaug board. Signed-off-by: Joseph Lo Acked-by: Jon Hunter --- arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts index 43cae4798870..b3930a9dd139 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts @@ -1340,6 +1340,25 @@ status = "okay"; clock-frequency = <1000000>; + max77621_cpu: max77621@1b { + compatible = "maxim,max77621"; + reg = <0x1b>; + interrupt-parent = <&gpio>; + interrupts = ; + regulator-name = "PPVAR_CPU"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1231250>; + regulator-ramp-delay = <12500>; + regulator-boot-on; + regulator-always-on; + maxim,dvs-default-state = <1>; + maxim,enable-active-discharge; + maxim,enable-bias-control; + maxim,enable-etr; + maxim,enable-gpio = <&max77620 5 0>; + maxim,externally-enable; + }; + max77620: max77620@3c { compatible = "maxim,max77620"; reg = <0x3c>; From patchwork Tue Dec 4 09:25:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 1007513 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="Uc/V1bHX"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 438GjK2z5pz9s55 for ; Tue, 4 Dec 2018 20:27:17 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725949AbeLDJ1R (ORCPT ); Tue, 4 Dec 2018 04:27:17 -0500 Received: from hqemgate16.nvidia.com ([216.228.121.65]:4090 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725871AbeLDJ1Q (ORCPT ); Tue, 4 Dec 2018 04:27:16 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 04 Dec 2018 01:27:18 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 04 Dec 2018 01:27:16 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 04 Dec 2018 01:27:16 -0800 Received: from HQMAIL106.nvidia.com (172.18.146.12) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 4 Dec 2018 09:27:15 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Tue, 4 Dec 2018 09:27:15 +0000 Received: from josephl-linux.nvidia.com (Not Verified[10.19.108.132]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 04 Dec 2018 01:27:15 -0800 From: Joseph Lo To: Thierry Reding , Peter De Schrijver , Jonathan Hunter CC: , , , Joseph Lo Subject: [PATCH 18/19] arm64: dts: tegra210-smaug: enable DFLL clock Date: Tue, 4 Dec 2018 17:25:47 +0800 Message-ID: <20181204092548.3038-19-josephl@nvidia.com> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181204092548.3038-1-josephl@nvidia.com> References: <20181204092548.3038-1-josephl@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1543915638; bh=rJyx7zXRuTxfbnU7n2PuC6aW6kvPz9uE39dkSEuq+7Y=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=Uc/V1bHXazMNlld1T8Iasz+oXxBWIQO/tf8Mvzc5no5GZhUviu9D6y5GaiEfjHfjF Qtx2+poKe2KR+52zaCljgavwlECJJSAVi6GJCRK6ESzvADGmfVL0JpXYJdnYwbsUQY rJzikITvJYC55UwsWs8oj13peNJOsKuYFJMkozq0wSi6qg/njvKLCV5az3a1mTXuq7 GH0VKslbIFE6iUoz9EZiO1cvXiP8krwLpm/rI+9hfxZIan21+ZVLask+HYJKr2bind jdRPbKniz7aXzNHTDaCCYBGt3F0V+/6FKHJqNdcLoLy5TB0+Nrz1g7lybLWXK2v1mj ZjxYTlJzWwMcQ== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Enable DFLL clock for Smaug board. Signed-off-by: Joseph Lo Acked-by: Jon Hunter --- arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts index b3930a9dd139..beac7b0bf436 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts @@ -1698,6 +1698,18 @@ status = "okay"; }; + clock@70110000 { + status = "okay"; + nvidia,sample-rate = <12500>; + nvidia,droop-ctrl = <0x00000f00>; + nvidia,force-mode = <1>; + nvidia,cf = <6>; + nvidia,ci = <0>; + nvidia,cg = <2>; + nvidia,i2c-fs-rate = <400000>; + vdd-cpu-supply = <&max77621_cpu>; + }; + aconnect@702c0000 { status = "okay"; From patchwork Tue Dec 4 09:25:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 1007514 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="qktwJkGq"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 438GjM4ly0z9s7W for ; Tue, 4 Dec 2018 20:27:19 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725898AbeLDJ1T (ORCPT ); Tue, 4 Dec 2018 04:27:19 -0500 Received: from hqemgate14.nvidia.com ([216.228.121.143]:3742 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725871AbeLDJ1T (ORCPT ); Tue, 4 Dec 2018 04:27:19 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 04 Dec 2018 01:27:17 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 04 Dec 2018 01:27:18 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 04 Dec 2018 01:27:18 -0800 Received: from HQMAIL112.nvidia.com (172.18.146.18) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 4 Dec 2018 09:27:18 +0000 Received: from HQMAIL108.nvidia.com (172.18.146.13) by HQMAIL112.nvidia.com (172.18.146.18) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 4 Dec 2018 09:27:17 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Tue, 4 Dec 2018 09:27:17 +0000 Received: from josephl-linux.nvidia.com (Not Verified[10.19.108.132]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 04 Dec 2018 01:27:17 -0800 From: Joseph Lo To: Thierry Reding , Peter De Schrijver , Jonathan Hunter CC: , , , Joseph Lo Subject: [PATCH 19/19] arm64: defconfig: Enable MAX8973 regulator Date: Tue, 4 Dec 2018 17:25:48 +0800 Message-ID: <20181204092548.3038-20-josephl@nvidia.com> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181204092548.3038-1-josephl@nvidia.com> References: <20181204092548.3038-1-josephl@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1543915637; bh=Jw2G9SmrFUt26WmWgjXCnnyrPuOPmpOMPrT1wFjPAQ0=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=qktwJkGqZWXwYOLEWycGsoqyfWyctpI8vhvy65nU2lsHUuHRQv5GfkrmVANudIzjH DSEWYukcwwfa9gymy3hVJJrqZv4oKmhMED4mX3efiz+yr5bll+Lfz7hAFZU0k6K03j Ku7wHzIWg6z0SgG9U1f7S3rsDC7LUc6ZM97CeqabFI8REEVNgFnvzgjpHbZCOZ+uM4 dKqE+iN/lUfh6ZTzl9oW5wHP83D/IACzr3ooEG9dhIdl65usJ2atw9KHMAiURrvYvg j1Qtp9xSvoPX+blYvN30+RBMEnThT7927CsooUQX3h1g+sR98RUAv1RXs8JQqK8X6k LQmC5r4gT4Dsw== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org The Tegra210 Smaug board uses MAX77621 for both CPU & GPU rail. Note that max8973 and max77621 share the same driver. So enable this driver for the PMIC. Signed-off-by: Joseph Lo Acked-by: Jon Hunter --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 5c2b1f6842f8..8dab129395a1 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -420,6 +420,7 @@ CONFIG_REGULATOR_GPIO=y CONFIG_REGULATOR_HI6421V530=y CONFIG_REGULATOR_HI655X=y CONFIG_REGULATOR_MAX77620=y +CONFIG_REGULATOR_MAX8973=y CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_QCOM_RPMH=y CONFIG_REGULATOR_QCOM_SMD_RPM=y