From patchwork Sun Dec 2 20:23:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mesih Kilinc X-Patchwork-Id: 1006575 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="R5Hnrjy5"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 437KQK603pz9s7W for ; Mon, 3 Dec 2018 07:26:01 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725786AbeLBUYR (ORCPT ); Sun, 2 Dec 2018 15:24:17 -0500 Received: from mail-wm1-f65.google.com ([209.85.128.65]:51375 "EHLO mail-wm1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725730AbeLBUYR (ORCPT ); Sun, 2 Dec 2018 15:24:17 -0500 Received: by mail-wm1-f65.google.com with SMTP id s14so3723261wmh.1; Sun, 02 Dec 2018 12:24:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=VF0eXPvxEQ8eg24ufuqCwYbc3OHuCombUgJA5hM0DFE=; b=R5Hnrjy5AZQR/YOegp9OG5MwjGVSqr5ylRLfDC9OEFoghKwvtTwpC65Mx1lTqqvD/c L/9bvjQJcCAB17o1b4hoagzj75v2qeCrjzRdpwDR6wc/h8sXAFnUQgGIsOH5i0tcVDFK LtjYP3IzF2/FxO5KQ4c8bMq/qqJfoLI2YlRfvjlYkjOjlzYFCL39kw5SHknsCHnpc+6L pgyX6/1dYQcPsVOVK/d8toQafmzS2hYPftNilLVuousgGFfQ2j3wHYE5uFluuefe3RE+ VINLNgJ5qVyui3mq/Gu25YoIzztAAIQLCYAcNZPDoDpgY1AHQmAcqSmn42PWCRdc0OXd roJA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=VF0eXPvxEQ8eg24ufuqCwYbc3OHuCombUgJA5hM0DFE=; b=gggEqR+F9ysihFD3bHvwz5LI9ol4XsEJTZMn+5rvf7X/lRLVM00vCRbu4x8NKO8id8 +WcURlWZwRu+kZkyq1LwzvbQXbSHz4KJfZHThdC10PBhNPrC9m7L9dxUg0N/im5R4S+J 7LsV8iuDlhUGUaQ6GRNkjeB4SB2NcJYSuIH2pg3/Eh5YZTCuE42xOHsRMauSiR+kYpjm syaY9zOjWWuo78fpJL78luLRXVmCWhUs6aAGu3yuox6Wxzf/XRscIVuxs23PfvppgVjB wVjODS871lffRDQg6MHhRnXkV43zD8T1d+R6OkhmgaL0aEjbdwF97/4d7ogwJJZp/EE3 s55w== X-Gm-Message-State: AA+aEWaN5fjRr2luPydRNWceAEhP6Yqm7eHnNUpVhIt+Zrq2C0gUT6uD bl1yeE8ManBg0sMt5XbUaGMTvlaGa7I= X-Google-Smtp-Source: AFSGD/X8J8uBvA+Atj2GldMyKoLN9X1VZyIrPrn5AEDmQeZ8PFIAwb3OctXByDSlmb+MmGKQBXN9Dg== X-Received: by 2002:a1c:f0e:: with SMTP id 14mr5742096wmp.37.1543782252226; Sun, 02 Dec 2018 12:24:12 -0800 (PST) Received: from ThinkPad.home ([185.219.177.152]) by smtp.gmail.com with ESMTPSA id l3sm14451510wma.44.2018.12.02.12.24.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 02 Dec 2018 12:24:11 -0800 (PST) From: Mesih Kilinc To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com Cc: Mesih Kilinc , Maxime Ripard , Chen-Yu Tsai , Russell King , Daniel Lezcano , Marc Zyngier , Linus Walleij , Icenowy Zheng , Rob Herring , Julian Calaby Subject: [PATCH v6 01/17] ARM: Check ARCH_MULTI_V7 to differentiate ARMv5/v7 Allwinner SoCs Date: Sun, 2 Dec 2018 23:23:35 +0300 Message-Id: <1a4e6f2b1d6aa5a079e2afb5d1ddf39f830eb8be.1543781680.git.mesihkilinc@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Allwinner also has some ARMv5 SoCs. In order to add support for them, check ARM_MULTI_V7 before enabling ARMv7 SoC's. Add help text for ARCH_SUNXI menuconfig. Signed-off-by: Mesih Kilinc --- arch/arm/mach-sunxi/Kconfig | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index d9c8ecf..185c573 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -9,9 +9,13 @@ menuconfig ARCH_SUNXI select PM_OPP select SUN4I_TIMER select RESET_CONTROLLER + help + Support for Allwinner ARM-based family of processors if ARCH_SUNXI +if ARCH_MULTI_V7 + config MACH_SUN4I bool "Allwinner A10 (sun4i) SoCs support" default ARCH_SUNXI @@ -56,3 +60,5 @@ config ARCH_SUNXI_MC_SMP select ARM_CPU_SUSPEND endif + +endif From patchwork Sun Dec 2 20:23:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mesih Kilinc X-Patchwork-Id: 1006572 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="gzmdAlgs"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 437KQC6p5Tz9s7W for ; Mon, 3 Dec 2018 07:25:55 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725819AbeLBUYV (ORCPT ); Sun, 2 Dec 2018 15:24:21 -0500 Received: from mail-wr1-f68.google.com ([209.85.221.68]:43608 "EHLO mail-wr1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725803AbeLBUYU (ORCPT ); Sun, 2 Dec 2018 15:24:20 -0500 Received: by mail-wr1-f68.google.com with SMTP id r10so10029770wrs.10; Sun, 02 Dec 2018 12:24:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=+V2WbDnTTYDb5DheTPlD4ID/xDgu/F+Pl9HjYjs8x9s=; b=gzmdAlgscUYL21LnLlekT5aOUIsAwdn6tX96qbCodW9DGKkZFT40/EKT+Xv9/xMNUl 0Vjuurbizu6q5Xq/a47UvjlY9mUlWaDFYTk+6WWiybiH/lwae5t+Dt3d0TS0MPRqy4iJ le2t5pxPRldKUNTBBuW92urVTjZtLQngeNs49LXoZWqC3mc8q2ATrs18VBN5FiyMdsgg MqylHFQ77uz9jnexx8vdSDvMXjzafQ1YhnhBBmVWGxGWSdwUPsD9AGzZbymjv8dxilJl nUFQgJFc5l5PCVPeyU980UOFkUdfF4VdQQAWta/46S3BYqFgh0emVWYWtk0F+V887dTN hmkA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=+V2WbDnTTYDb5DheTPlD4ID/xDgu/F+Pl9HjYjs8x9s=; b=n5QXnQWgiiEOPvHJg9fFneq29qnLn0uTQWxYViS0vVC1705g5MH30li7YtkXh21rhs TBAp+c3pGf9CVtxPPf1lHuynYmB+oVVHqfUriV0TVubbTKg+Cbl5iq2LCfi2qP3VjMXy 65WldFeUl2bWMiYoEIvuwJMUpUiFb3hEwbfxmkBYilJhupIYB3zvfzy2eKxT6i+/Qqy4 7oZn90rnzPDogmmaU6i5UVQl6WM6DhEgsiKJw9Vhd7KXJ0RhSwzISjYcNS+3W+WxPVcu /WO7kcZB8tDvf6ymwQJE+Eigp4YPEJ8iF9J5A8gv1u1vmT4VicEwoPuTTXSDlj5C7p7Q SJPA== X-Gm-Message-State: AA+aEWYXaak5SnpqZqiW7tvTdQ8CjkP7CXNReB3dc2jRRuSKAmoM2uPJ 0ip8dCL+MLWOjqGgr/iorzvdusmHguU= X-Google-Smtp-Source: AFSGD/UvqSUUDOejX6SjyUwczTcah8rkFmvGhQoVogLPun72q5lzEFpLT8WIyylrx395yFeAiioYlQ== X-Received: by 2002:a5d:61c4:: with SMTP id q4mr11112960wrv.308.1543782253959; Sun, 02 Dec 2018 12:24:13 -0800 (PST) Received: from ThinkPad.home ([185.219.177.152]) by smtp.gmail.com with ESMTPSA id l3sm14451510wma.44.2018.12.02.12.24.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 02 Dec 2018 12:24:13 -0800 (PST) From: Mesih Kilinc To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com Cc: Mesih Kilinc , Maxime Ripard , Chen-Yu Tsai , Russell King , Daniel Lezcano , Marc Zyngier , Linus Walleij , Icenowy Zheng , Rob Herring , Julian Calaby Subject: [PATCH v6 02/17] dt-bindings: arm: Add new Allwinner ARMv5 F1C100s SoC Date: Sun, 2 Dec 2018 23:23:36 +0300 Message-Id: <6fa3cf509379a0888388821eef3e322c014df5b8.1543781680.git.mesihkilinc@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add new Allwinner ARMv5 F1C100s SoC's compatible string Signed-off-by: Mesih Kilinc Acked-by: Maxime Ripard Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/arm/sunxi.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt b/Documentation/devicetree/bindings/arm/sunxi.txt index e4beec3..f9ddc05 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.txt +++ b/Documentation/devicetree/bindings/arm/sunxi.txt @@ -18,4 +18,5 @@ using one of the following compatible strings: allwinner,sun8i-v3s allwinner,sun9i-a80 allwinner,sun50i-a64 + allwinner,suniv-f1c100s nextthing,gr8 From patchwork Sun Dec 2 20:23:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mesih Kilinc X-Patchwork-Id: 1006571 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="gt3nGvK8"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 437KQ75Qnhz9s7W for ; Mon, 3 Dec 2018 07:25:51 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725803AbeLBUYW (ORCPT ); Sun, 2 Dec 2018 15:24:22 -0500 Received: from mail-wm1-f66.google.com ([209.85.128.66]:32819 "EHLO mail-wm1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725710AbeLBUYW (ORCPT ); Sun, 2 Dec 2018 15:24:22 -0500 Received: by mail-wm1-f66.google.com with SMTP id r24so5502411wmh.0; Sun, 02 Dec 2018 12:24:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=zZAcd5DCVFwIJh7pdMnlLFltxq06uySPlY2MVRx9NcI=; b=gt3nGvK8NwsEwK5RJDBj/2x+YS+lOCQ7+bXLEo/6nmmzBptA+3rt1F6H2R5NvrVncP sRqCYhYPTatsdgL9k+nyP2gb4031HLQB39nU5GycYJ1iYAUxqYzpYpciwT7HD0FbwccX kKzMlu9IRNG3UDO86/4rUE/Pf4hut1HCRw+mN99B6xE9JSvGIB/Fodd9BgscSb2aKfH7 UHxMEXHsiy7hb68SoXruVjOLFOK9yjCwFU7MvrI+Ba9aTDs22wl+2etMeHeargImX0YC 0lgLMj1W3dMi/ayDzUUE5zgXyW1RsWix+BF6/adDxXq/b134LX13DwfJ4xtym9maIBdL ZkXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=zZAcd5DCVFwIJh7pdMnlLFltxq06uySPlY2MVRx9NcI=; b=hkjaO4lC1ucXwtbiTwn4F0oYG1xtXcJE+lARUYlRa4QRoepbk6hcrosD9BzTtRtTTl TjXqRO0AUXQEdVbZg8+E+qEVOALUORmvdumXMp+mVmJOEcgd+q9XfKiUlWBKteIIheDT yvY13DzAX9n3K5U0mmENGEwN9s7sqgvNCWYrQ9cQSJO4+dsxM96Wc3Cu3NI7M4Qw4zcO 1JhleCL6vNeRoM8uwMJXgdhgeMQ2IrIr/D11ZFQ4KNPrOAMtjh9iTl+bzyhtwxpViCZ/ kw/MNVFWHl6ihmtB61PhlGigZzRHiXuAKXl6isKfM0jdbVXrBU7UTjzW3Olu+5lVbrNw +F8w== X-Gm-Message-State: AA+aEWbAsju0EvrU8VkYJxkHJFBe8WOM2P1EdZq3XaKAG42+J891oHds s/MpGYCWevnAPUQXqn/Y86hiy+brXF4= X-Google-Smtp-Source: AFSGD/UN6jAOjEyAnAksPMWBNNew+GSzwYbOdZr/pbVEbOevS6G+zY9Ict6vDwwjDsLG75dyNEg4iQ== X-Received: by 2002:a1c:f116:: with SMTP id p22mr5918334wmh.0.1543782255665; Sun, 02 Dec 2018 12:24:15 -0800 (PST) Received: from ThinkPad.home ([185.219.177.152]) by smtp.gmail.com with ESMTPSA id l3sm14451510wma.44.2018.12.02.12.24.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 02 Dec 2018 12:24:15 -0800 (PST) From: Mesih Kilinc To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com Cc: Mesih Kilinc , Maxime Ripard , Chen-Yu Tsai , Russell King , Daniel Lezcano , Marc Zyngier , Linus Walleij , Icenowy Zheng , Rob Herring , Julian Calaby Subject: [PATCH v6 03/17] ARM: sunxi: add Allwinner ARMv5 SoCs Date: Sun, 2 Dec 2018 23:23:37 +0300 Message-Id: X-Mailer: git-send-email 2.7.4 In-Reply-To: References: Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add option for Allwinner ARMv5 SoCs and SoC F1C100s (which has a die used for many new F-series products, including F1C100A, F1C100s, F1C200s, F1C500, F1C600). Signed-off-by: Mesih Kilinc Acked-by: Maxime Ripard --- arch/arm/mach-sunxi/Kconfig | 13 ++++++++++++- arch/arm/mach-sunxi/sunxi.c | 10 ++++++++++ 2 files changed, 22 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 185c573..7fa6a3d 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -1,6 +1,6 @@ menuconfig ARCH_SUNXI bool "Allwinner SoCs" - depends on ARCH_MULTI_V7 + depends on ARCH_MULTI_V5 || ARCH_MULTI_V7 select ARCH_HAS_RESET_CONTROLLER select CLKSRC_MMIO select GENERIC_IRQ_CHIP @@ -61,4 +61,15 @@ config ARCH_SUNXI_MC_SMP endif +if ARCH_MULTI_V5 + +config MACH_SUNIV + bool "Allwinner ARMv5 F-series (suniv) SoCs support" + default ARCH_SUNXI + help + Support for Allwinner suniv ARMv5 SoCs. + (F1C100A, F1C100s, F1C200s, F1C500, F1C600) + +endif + endif diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c index de4b0e9..155cd9e 100644 --- a/arch/arm/mach-sunxi/sunxi.c +++ b/arch/arm/mach-sunxi/sunxi.c @@ -101,3 +101,13 @@ static const char * const sun9i_board_dt_compat[] = { DT_MACHINE_START(SUN9I_DT, "Allwinner sun9i Family") .dt_compat = sun9i_board_dt_compat, MACHINE_END + +static const char * const suniv_board_dt_compat[] = { + "allwinner,suniv-f1c100s", + NULL, +}; + +DT_MACHINE_START(SUNIV_DT, "Allwinner suniv Family") + .dt_compat = suniv_board_dt_compat, +MACHINE_END + From patchwork Sun Dec 2 20:23:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mesih Kilinc X-Patchwork-Id: 1006569 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="e9iKNK98"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 437KPz5HN3z9s7W for ; Mon, 3 Dec 2018 07:25:43 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725874AbeLBUYY (ORCPT ); Sun, 2 Dec 2018 15:24:24 -0500 Received: from mail-wr1-f66.google.com ([209.85.221.66]:36542 "EHLO mail-wr1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725835AbeLBUYX (ORCPT ); Sun, 2 Dec 2018 15:24:23 -0500 Received: by mail-wr1-f66.google.com with SMTP id u3so10053744wrs.3; Sun, 02 Dec 2018 12:24:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=PqiSTLwl5WXrDtWtjcIXDjRJSUqIIl0Us7oauuCOk9k=; b=e9iKNK98m11pgSa/BPEv8VvGiLNUd1ZlXI9Y3Yo90vq9Fjau0IsbrlkKLAeu0ePix1 W445CLoeL3/XFiA6y64V21KVljl/vZaMyuiufxyZ8Oo1P5QEfEE1Lfqavavq+2iHOZVG KUSvcEX4jqDc5zfzRZnX1zBJs4PTUlkOmSecW/2iMAaMOh7u4s9TaxkqyhJoQ+7w4DGF WPSbBnoF2vVg0lOmhWKIO1x/C/AERgYpPQwuF5WG9zrOwCDitJlJ5xGMnbgi+WZMhJ01 WxlCaKSEXITINCZXxTGGJfU9ofzk1JK5DnTjkUo0JTZouA1PIUKmiS1pEwhYNCktqwkr n7NA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=PqiSTLwl5WXrDtWtjcIXDjRJSUqIIl0Us7oauuCOk9k=; b=EJ9pIC7kwe/TtkkA4tn7CashcSkuatbFtbhQhH1FGfawlfzN+6dfGF4KJGm8DowGmP e0FKNOTZnDQJjzXhoVdsPA2ceRwCKNsTAov72QHPbT/NfIRP38vwun9Fg1qC/dDyp+uU p0ySWZVMnrSbrSe/K0eVaYZ+tznxHOCbxE48O/pVDE3I4mwlGOgX/NB51yIdSTc6KOr6 /OsSHaVutzz/h0VAQn+1DYq1cof2GC3gyDrnYatg2X+Z4YnpmqH4h/YuN/8p8Y0XPA5L eP6SwsGz04WRWNR8vLpkeprcfHXUM8Fo65MeWvg+m0cwJfqS3VPeLTcNxmIBZrZ+yHps hpUw== X-Gm-Message-State: AA+aEWbjWK9AUGQXxnzBlsrDsm1MTRffk4cgyc9UaGoNOKHGj0Kb2MsX TFNuQ1iuDVhOzpUYSQcjunN4TCrqu3A= X-Google-Smtp-Source: AFSGD/UqijtIBCI4InCgJ2A+px76jgUgOs52e/O3u9GKyFEmb6OwmrQkEnOqP4xOnrZx74oUzsLkhg== X-Received: by 2002:adf:891a:: with SMTP id s26mr11571267wrs.44.1543782257366; Sun, 02 Dec 2018 12:24:17 -0800 (PST) Received: from ThinkPad.home ([185.219.177.152]) by smtp.gmail.com with ESMTPSA id l3sm14451510wma.44.2018.12.02.12.24.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 02 Dec 2018 12:24:16 -0800 (PST) From: Mesih Kilinc To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com Cc: Mesih Kilinc , Maxime Ripard , Chen-Yu Tsai , Russell King , Daniel Lezcano , Marc Zyngier , Linus Walleij , Icenowy Zheng , Rob Herring , Julian Calaby Subject: [PATCH v6 04/17] dt-bindings: interrupt-controller: Add suniv interrupt-controller Date: Sun, 2 Dec 2018 23:23:38 +0300 Message-Id: <0d15ef1e424f0f9627b4e278273c7e77239869af.1543781680.git.mesihkilinc@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add compatible string for Alwinner suniv F1C100s SoC interrupt controller which is stripped version of sun4i Signed-off-by: Mesih Kilinc Acked-by: Maxime Ripard Reviewed-by: Rob Herring --- .../devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt index b290ca1..4043525 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt @@ -2,7 +2,9 @@ Allwinner Sunxi Interrupt Controller Required properties: -- compatible : should be "allwinner,sun4i-a10-ic" +- compatible : should be one of the following: + "allwinner,sun4i-a10-ic" + "allwinner,suniv-f1c100s-ic" - reg : Specifies base physical address and size of the registers. - interrupt-controller : Identifies the node as an interrupt controller - #interrupt-cells : Specifies the number of cells needed to encode an From patchwork Sun Dec 2 20:23:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mesih Kilinc X-Patchwork-Id: 1006568 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="QOuECvqc"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 437KPz0M6vz9s9h for ; Mon, 3 Dec 2018 07:25:43 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725887AbeLBUY0 (ORCPT ); Sun, 2 Dec 2018 15:24:26 -0500 Received: from mail-wm1-f67.google.com ([209.85.128.67]:52658 "EHLO mail-wm1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725710AbeLBUYZ (ORCPT ); Sun, 2 Dec 2018 15:24:25 -0500 Received: by mail-wm1-f67.google.com with SMTP id r11-v6so3705663wmb.2; Sun, 02 Dec 2018 12:24:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=pPyUIGXeqFRSeuAkF4pGGd34E1h9rjxV9MCCqdJ4qRg=; b=QOuECvqcAlUgIsP9LqxNG42D4v+HpYYhQORwIESqsXZteyRJm1qZv5spl5pZIyogDv 4r/6bDKKRiAkWhu8DVhaYi50ZJJsA1LT8Kiez5rYyriQg7EyqjatlSJR3KxmDBT8edXl Lyb6DXi5QtLf7IWmCLElrb7EDO3rfSkWA2PdJhoeGrjIPigQijKN2bCDCDPfNHvJ2Z1Q k2hqdig/DGWEXud1/izPPZ76x7GKYSt8Qhr1YvgE5TxZ3sgNHCDd0uFkTDeXkRtsUDSM Ks78VUKEhVB4UL3p72an+EetGA3zZpJP4cWmtZdbSFb8rBbI6rXFWwlbvqCr4eK7bfsC uK2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=pPyUIGXeqFRSeuAkF4pGGd34E1h9rjxV9MCCqdJ4qRg=; b=cfAByWftKRp9XZV2B1AbBKY26h0Y01J7QV+xAW6Bc9KWklxQXdBMMiQrHzc6bNl1ZY +m0ifTK/zexobey11rgsJL7TDvw4Yndzgc8RprqR0MLjRQqi/jU9vYYglk+D6FvTqv8p Ny44MrcXnQewSyiIugl04iDCZxcIw7okoxaVmRkpWqDsLJPeudbTbB/qxqcgVs1YmFKy eX9u3ogHl6JLaPj48PiOyNkASMW++2pJozvg5b83JaGVdDpfFUCjIMn9zAevLPTgqFZk OrR60se1F9GVPYl+9B/EsYU2H8L6ZyhnwzPJGcabWLC9Om2/FLiY2F2nzo+IumoQtI+v Ul4A== X-Gm-Message-State: AA+aEWaYPq3+/XuUVmLIDCIO/SiFAgI/YehkMJwJra1H7VMJvtzchNL1 nrAZ1A7hCyEtD/TEaEvpQ7DcjyqiOTU= X-Google-Smtp-Source: AFSGD/WaqYDAklJn2pD4CHWmb1NbC2owA99yUfQAtycTuFSdRkufIZOiGTFnXa1aB9bELjQ6EUKtaA== X-Received: by 2002:a7b:c397:: with SMTP id s23mr5694878wmj.127.1543782259113; Sun, 02 Dec 2018 12:24:19 -0800 (PST) Received: from ThinkPad.home ([185.219.177.152]) by smtp.gmail.com with ESMTPSA id l3sm14451510wma.44.2018.12.02.12.24.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 02 Dec 2018 12:24:18 -0800 (PST) From: Mesih Kilinc To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com Cc: Mesih Kilinc , Maxime Ripard , Chen-Yu Tsai , Russell King , Daniel Lezcano , Marc Zyngier , Linus Walleij , Icenowy Zheng , Rob Herring , Julian Calaby Subject: [PATCH v6 05/17] irqchip/sun4i: Add a struct to hold global variables Date: Sun, 2 Dec 2018 23:23:39 +0300 Message-Id: X-Mailer: git-send-email 2.7.4 In-Reply-To: References: Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org In order to support different chips, IC specific data should be hold in a struct. This patch moves irq_base and irq_domain global variables to struct. Signed-off-by: Mesih Kilinc Acked-by: Maxime Ripard --- drivers/irqchip/irq-sun4i.c | 64 +++++++++++++++++++++++++++------------------ 1 file changed, 38 insertions(+), 26 deletions(-) diff --git a/drivers/irqchip/irq-sun4i.c b/drivers/irqchip/irq-sun4i.c index e3e5b91..0c32506 100644 --- a/drivers/irqchip/irq-sun4i.c +++ b/drivers/irqchip/irq-sun4i.c @@ -31,8 +31,12 @@ #define SUN4I_IRQ_ENABLE_REG(x) (0x40 + 0x4 * x) #define SUN4I_IRQ_MASK_REG(x) (0x50 + 0x4 * x) -static void __iomem *sun4i_irq_base; -static struct irq_domain *sun4i_irq_domain; +struct sun4i_irq_chip_data { + void __iomem *irq_base; + struct irq_domain *irq_domain; +}; + +static struct sun4i_irq_chip_data *irq_ic_data; static void __exception_irq_entry sun4i_handle_irq(struct pt_regs *regs); @@ -43,7 +47,7 @@ static void sun4i_irq_ack(struct irq_data *irqd) if (irq != 0) return; /* Only IRQ 0 / the ENMI needs to be acked */ - writel(BIT(0), sun4i_irq_base + SUN4I_IRQ_PENDING_REG(0)); + writel(BIT(0), irq_ic_data->irq_base + SUN4I_IRQ_PENDING_REG(0)); } static void sun4i_irq_mask(struct irq_data *irqd) @@ -53,9 +57,9 @@ static void sun4i_irq_mask(struct irq_data *irqd) int reg = irq / 32; u32 val; - val = readl(sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg)); + val = readl(irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(reg)); writel(val & ~(1 << irq_off), - sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg)); + irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(reg)); } static void sun4i_irq_unmask(struct irq_data *irqd) @@ -65,9 +69,9 @@ static void sun4i_irq_unmask(struct irq_data *irqd) int reg = irq / 32; u32 val; - val = readl(sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg)); + val = readl(irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(reg)); writel(val | (1 << irq_off), - sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg)); + irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(reg)); } static struct irq_chip sun4i_irq_chip = { @@ -95,35 +99,41 @@ static const struct irq_domain_ops sun4i_irq_ops = { static int __init sun4i_of_init(struct device_node *node, struct device_node *parent) { - sun4i_irq_base = of_iomap(node, 0); - if (!sun4i_irq_base) + irq_ic_data = kzalloc(sizeof(struct sun4i_irq_chip_data), GFP_KERNEL); + if (!irq_ic_data) { + pr_err("kzalloc failed!\n"); + return -ENOMEM; + } + + irq_ic_data->irq_base = of_iomap(node, 0); + if (!irq_ic_data->irq_base) panic("%pOF: unable to map IC registers\n", node); /* Disable all interrupts */ - writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(0)); - writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(1)); - writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(2)); + writel(0, irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(0)); + writel(0, irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(1)); + writel(0, irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(2)); /* Unmask all the interrupts, ENABLE_REG(x) is used for masking */ - writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(0)); - writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(1)); - writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(2)); + writel(0, irq_ic_data->irq_base + SUN4I_IRQ_MASK_REG(0)); + writel(0, irq_ic_data->irq_base + SUN4I_IRQ_MASK_REG(1)); + writel(0, irq_ic_data->irq_base + SUN4I_IRQ_MASK_REG(2)); /* Clear all the pending interrupts */ - writel(0xffffffff, sun4i_irq_base + SUN4I_IRQ_PENDING_REG(0)); - writel(0xffffffff, sun4i_irq_base + SUN4I_IRQ_PENDING_REG(1)); - writel(0xffffffff, sun4i_irq_base + SUN4I_IRQ_PENDING_REG(2)); + writel(0xffffffff, irq_ic_data->irq_base + SUN4I_IRQ_PENDING_REG(0)); + writel(0xffffffff, irq_ic_data->irq_base + SUN4I_IRQ_PENDING_REG(1)); + writel(0xffffffff, irq_ic_data->irq_base + SUN4I_IRQ_PENDING_REG(2)); /* Enable protection mode */ - writel(0x01, sun4i_irq_base + SUN4I_IRQ_PROTECTION_REG); + writel(0x01, irq_ic_data->irq_base + SUN4I_IRQ_PROTECTION_REG); /* Configure the external interrupt source type */ - writel(0x00, sun4i_irq_base + SUN4I_IRQ_NMI_CTRL_REG); + writel(0x00, irq_ic_data->irq_base + SUN4I_IRQ_NMI_CTRL_REG); - sun4i_irq_domain = irq_domain_add_linear(node, 3 * 32, + irq_ic_data->irq_domain = irq_domain_add_linear(node, 3 * 32, &sun4i_irq_ops, NULL); - if (!sun4i_irq_domain) + if (!irq_ic_data->irq_domain) panic("%pOF: unable to create IRQ domain\n", node); set_handle_irq(sun4i_handle_irq); @@ -146,13 +156,15 @@ static void __exception_irq_entry sun4i_handle_irq(struct pt_regs *regs) * the extra check in the common case of 1 hapening after having * read the vector-reg once. */ - hwirq = readl(sun4i_irq_base + SUN4I_IRQ_VECTOR_REG) >> 2; + hwirq = readl(irq_ic_data->irq_base + SUN4I_IRQ_VECTOR_REG) >> 2; if (hwirq == 0 && - !(readl(sun4i_irq_base + SUN4I_IRQ_PENDING_REG(0)) & BIT(0))) + !(readl(irq_ic_data->irq_base + SUN4I_IRQ_PENDING_REG(0)) & + BIT(0))) return; do { - handle_domain_irq(sun4i_irq_domain, hwirq, regs); - hwirq = readl(sun4i_irq_base + SUN4I_IRQ_VECTOR_REG) >> 2; + handle_domain_irq(irq_ic_data->irq_domain, hwirq, regs); + hwirq = readl(irq_ic_data->irq_base + + SUN4I_IRQ_VECTOR_REG) >> 2; } while (hwirq != 0); } From patchwork Sun Dec 2 20:23:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mesih Kilinc X-Patchwork-Id: 1006567 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="ip7YB2KP"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 437KPr4J0dz9s7W for ; Mon, 3 Dec 2018 07:25:36 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725909AbeLBUY1 (ORCPT ); Sun, 2 Dec 2018 15:24:27 -0500 Received: from mail-wr1-f66.google.com ([209.85.221.66]:39832 "EHLO mail-wr1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725835AbeLBUY1 (ORCPT ); Sun, 2 Dec 2018 15:24:27 -0500 Received: by mail-wr1-f66.google.com with SMTP id t27so10059313wra.6; Sun, 02 Dec 2018 12:24:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=6Tg/Nlf4DVosGXWUAPR1HKg7aUMJ7+jsissUOrruo7A=; b=ip7YB2KP/uFzP4hjDqvDTMMAqKjIV2+DA8xEXmeRnJLu9l8IFwiYOXK7vgwn5gFwtv YKWVzlWU+lu9LCEjGsHISnjUiAeOT3T101u+myvtj8x53lyXxizmHRcbagnntyIK0YAo qBGVOZMZC2MdsI5XAB9f5CrsJ2qCrWV18AFhkB2TnWSHxzoke2W/YkAi3BVU1NBUMTzQ +B5yQPQOozGmdE3hf6geB/zIWNF0LTZd0lwOTaD8O6NQlP7ux9jdHBhg/9BSiqZ+PMLK B8SMUL/ZjfAsg5eF2w15B1QgXCwpB5JAb2I0+cjtGHxa5Sno85koz5Sjz10Emt6Tqur2 52QA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=6Tg/Nlf4DVosGXWUAPR1HKg7aUMJ7+jsissUOrruo7A=; b=AheCpegV6GxgLI0kMVgsIXP/ZDhit92OqQyepjGtAhRShM+zPGqIGRmY8E6SttOaam c7WS6A9/50Zd5DWhtyWzEkjiOwMDJjWGcgIK6LuHFjd/zkUtJbw7UhyFZPtUoiU0jp5z t0xKynVE/EeYPJ16flhu8ERrq3TTpRAKAoxeR6txnAUW1PUPSqwNK4G0IA3L1xJ5Gv8v kr4s7V6RebzMVhfsT8RCEfgSsPwp5vHgUa9oopwTkLN1Hvuv58nJ5ZLdWMAEtjewdKpO nnMU8zTlH4DdCBHFt3RDMWQC1LpoenVTOJdTArh9wAEtYiCb0TUHPEJNKaevhNQxtHt6 twGQ== X-Gm-Message-State: AA+aEWacyEdoOlvYsfSD8cbQW/FD+deT/DInl2qHBm+VqFrXO1AQ3GIJ A4EJoWu/yjdgfH4TYznaenprteE4kD4= X-Google-Smtp-Source: AFSGD/UYA/ZwoZ4cE+mkzHvdE0aO2dQwEm7fduDyEzyRE4V5YN4GOBJWtdIx5rtePcpxa8cIJ1sDZg== X-Received: by 2002:adf:b102:: with SMTP id l2mr11224233wra.296.1543782260969; Sun, 02 Dec 2018 12:24:20 -0800 (PST) Received: from ThinkPad.home ([185.219.177.152]) by smtp.gmail.com with ESMTPSA id l3sm14451510wma.44.2018.12.02.12.24.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 02 Dec 2018 12:24:20 -0800 (PST) From: Mesih Kilinc To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com Cc: Mesih Kilinc , Maxime Ripard , Chen-Yu Tsai , Russell King , Daniel Lezcano , Marc Zyngier , Linus Walleij , Icenowy Zheng , Rob Herring , Julian Calaby Subject: [PATCH v6 06/17] irqchip/sun4i: Move IC specific register offsets to struct Date: Sun, 2 Dec 2018 23:23:40 +0300 Message-Id: X-Mailer: git-send-email 2.7.4 In-Reply-To: References: Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This patch moves IC specific register offsets to sun4i_irq_chip_data struct in order to support different chips. Signed-off-by: Mesih Kilinc Acked-by: Maxime Ripard --- drivers/irqchip/irq-sun4i.c | 33 +++++++++++++++++++++------------ 1 file changed, 21 insertions(+), 12 deletions(-) diff --git a/drivers/irqchip/irq-sun4i.c b/drivers/irqchip/irq-sun4i.c index 0c32506..507f4e3 100644 --- a/drivers/irqchip/irq-sun4i.c +++ b/drivers/irqchip/irq-sun4i.c @@ -28,12 +28,16 @@ #define SUN4I_IRQ_NMI_CTRL_REG 0x0c #define SUN4I_IRQ_PENDING_REG(x) (0x10 + 0x4 * x) #define SUN4I_IRQ_FIQ_PENDING_REG(x) (0x20 + 0x4 * x) -#define SUN4I_IRQ_ENABLE_REG(x) (0x40 + 0x4 * x) -#define SUN4I_IRQ_MASK_REG(x) (0x50 + 0x4 * x) +#define SUN4I_IRQ_ENABLE_REG(data, x) ((data)->enable_reg_offset + 0x4 * x) +#define SUN4I_IRQ_MASK_REG(data, x) ((data)->mask_reg_offset + 0x4 * x) +#define SUN4I_IRQ_ENABLE_REG_OFFSET 0x40 +#define SUN4I_IRQ_MASK_REG_OFFSET 0x50 struct sun4i_irq_chip_data { void __iomem *irq_base; struct irq_domain *irq_domain; + u32 enable_reg_offset; + u32 mask_reg_offset; }; static struct sun4i_irq_chip_data *irq_ic_data; @@ -57,9 +61,10 @@ static void sun4i_irq_mask(struct irq_data *irqd) int reg = irq / 32; u32 val; - val = readl(irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(reg)); + val = readl(irq_ic_data->irq_base + + SUN4I_IRQ_ENABLE_REG(irq_ic_data, reg)); writel(val & ~(1 << irq_off), - irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(reg)); + irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(irq_ic_data, reg)); } static void sun4i_irq_unmask(struct irq_data *irqd) @@ -69,9 +74,10 @@ static void sun4i_irq_unmask(struct irq_data *irqd) int reg = irq / 32; u32 val; - val = readl(irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(reg)); + val = readl(irq_ic_data->irq_base + + SUN4I_IRQ_ENABLE_REG(irq_ic_data, reg)); writel(val | (1 << irq_off), - irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(reg)); + irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(irq_ic_data, reg)); } static struct irq_chip sun4i_irq_chip = { @@ -105,20 +111,23 @@ static int __init sun4i_of_init(struct device_node *node, return -ENOMEM; } + irq_ic_data->enable_reg_offset = SUN4I_IRQ_ENABLE_REG_OFFSET; + irq_ic_data->mask_reg_offset = SUN4I_IRQ_MASK_REG_OFFSET; + irq_ic_data->irq_base = of_iomap(node, 0); if (!irq_ic_data->irq_base) panic("%pOF: unable to map IC registers\n", node); /* Disable all interrupts */ - writel(0, irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(0)); - writel(0, irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(1)); - writel(0, irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(2)); + writel(0, irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(irq_ic_data, 0)); + writel(0, irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(irq_ic_data, 1)); + writel(0, irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(irq_ic_data, 2)); /* Unmask all the interrupts, ENABLE_REG(x) is used for masking */ - writel(0, irq_ic_data->irq_base + SUN4I_IRQ_MASK_REG(0)); - writel(0, irq_ic_data->irq_base + SUN4I_IRQ_MASK_REG(1)); - writel(0, irq_ic_data->irq_base + SUN4I_IRQ_MASK_REG(2)); + writel(0, irq_ic_data->irq_base + SUN4I_IRQ_MASK_REG(irq_ic_data, 0)); + writel(0, irq_ic_data->irq_base + SUN4I_IRQ_MASK_REG(irq_ic_data, 1)); + writel(0, irq_ic_data->irq_base + SUN4I_IRQ_MASK_REG(irq_ic_data, 2)); /* Clear all the pending interrupts */ writel(0xffffffff, irq_ic_data->irq_base + SUN4I_IRQ_PENDING_REG(0)); From patchwork Sun Dec 2 20:23:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mesih Kilinc X-Patchwork-Id: 1006566 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="L8v7t5zb"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 437KPm5x0cz9s7W for ; Mon, 3 Dec 2018 07:25:32 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725926AbeLBUY3 (ORCPT ); Sun, 2 Dec 2018 15:24:29 -0500 Received: from mail-wm1-f68.google.com ([209.85.128.68]:53685 "EHLO mail-wm1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725710AbeLBUY2 (ORCPT ); Sun, 2 Dec 2018 15:24:28 -0500 Received: by mail-wm1-f68.google.com with SMTP id y1so3691535wmi.3; Sun, 02 Dec 2018 12:24:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=U5HquPP+e02dVOAMk7E3AUX6XcA/ii1Z/T8jnzUactc=; b=L8v7t5zbQqh3/DPYoJLHYE40hz4yqDp09mr0+ytfO+988shSCu9X7GkxbxVX0Fvdec IO6VkFhMbltF92r1jmInr2Cd+4dCc6zxZoMBfd1Z3rTzVdhZBI6Zsqu4gsmC2np5D4EQ dRBXjcmy0GoWomDyQlSzAZw8Hpu7xx2Nq5Q22UeEH/aJulByTagBEPWI2SKRXPKt0JNA UnjiJ8O6fvT+AN4CBEU44l8BiTiNCY8//BAs9eFepowwyfZQka5AfketwwXGcrewxz0j MfwYqf+VLOKqmgGZiuNpXIGPJv3gxocJp34ct4FujbpTHvBJvGV1Mv9SfK/xi8xeleLr tlKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=U5HquPP+e02dVOAMk7E3AUX6XcA/ii1Z/T8jnzUactc=; b=SMhhWvC3atd+EEzmGUn/pzWl+yK2pED2qO4GeRYqazuJ0ICx85mEckTDJX0YJeLpXa uHBPCL9cvkFXH76uX0BNhldYNzm8in6wDhzcEYjn6cgI7Bkj8Z42u9Jqkei2pIfxp78D zCbVZYdUB7GjMf5gYsmEczEkGu7s2LSIWKTLSFV4R471i2OzehR44zoF1A+vTY7m41Kj hRA3df0bJY9kMXIqBKlRUKDggUeLBBcYOXAbre/odstHS9A4Bn+K5Qz2XqzP0QxLmGNG 3AagrRrLrnzqyV9irMIkdA12IsPZJ2lO8DW2eZFnwmraCZpnnTeifk1YRQndKJLhJehW +/+g== X-Gm-Message-State: AA+aEWZpKAN+Lzs8icIhG6rG9iceCmZNFK8U5LCToL1TUCZltCI+L44e Vna1UPm6ac111gpW1EXV1yh/xoNim70= X-Google-Smtp-Source: AFSGD/UFKK2jtp9cBl8PYI9aqb6iLHAmap/42TqW2mdTbBNEWU2kbvckHWh2BcLHDt88Mu+0GCuM6g== X-Received: by 2002:a1c:c148:: with SMTP id r69mr5870493wmf.147.1543782262710; Sun, 02 Dec 2018 12:24:22 -0800 (PST) Received: from ThinkPad.home ([185.219.177.152]) by smtp.gmail.com with ESMTPSA id l3sm14451510wma.44.2018.12.02.12.24.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 02 Dec 2018 12:24:22 -0800 (PST) From: Mesih Kilinc To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com Cc: Mesih Kilinc , Maxime Ripard , Chen-Yu Tsai , Russell King , Daniel Lezcano , Marc Zyngier , Linus Walleij , Icenowy Zheng , Rob Herring , Julian Calaby Subject: [PATCH v6 07/17] irqchip/sun4i: Add support for Allwinner ARMv5 F1C100s Date: Sun, 2 Dec 2018 23:23:41 +0300 Message-Id: <5fe6eafae0bd8994dcdb5ea6b9255a64e6cdf02c.1543781680.git.mesihkilinc@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This patch adds support for suniv Allwinner ARMv5 F1C100s SoC which has stripped version of interrupt controller that found in A10/A13. Signed-off-by: Mesih Kilinc Acked-by: Maxime Ripard --- drivers/irqchip/irq-sun4i.c | 47 +++++++++++++++++++++++++++++++++++---------- 1 file changed, 37 insertions(+), 10 deletions(-) diff --git a/drivers/irqchip/irq-sun4i.c b/drivers/irqchip/irq-sun4i.c index 507f4e3..fb78d66 100644 --- a/drivers/irqchip/irq-sun4i.c +++ b/drivers/irqchip/irq-sun4i.c @@ -32,6 +32,8 @@ #define SUN4I_IRQ_MASK_REG(data, x) ((data)->mask_reg_offset + 0x4 * x) #define SUN4I_IRQ_ENABLE_REG_OFFSET 0x40 #define SUN4I_IRQ_MASK_REG_OFFSET 0x50 +#define SUNIV_IRQ_ENABLE_REG_OFFSET 0x20 +#define SUNIV_IRQ_MASK_REG_OFFSET 0x30 struct sun4i_irq_chip_data { void __iomem *irq_base; @@ -105,15 +107,6 @@ static const struct irq_domain_ops sun4i_irq_ops = { static int __init sun4i_of_init(struct device_node *node, struct device_node *parent) { - irq_ic_data = kzalloc(sizeof(struct sun4i_irq_chip_data), GFP_KERNEL); - if (!irq_ic_data) { - pr_err("kzalloc failed!\n"); - return -ENOMEM; - } - - irq_ic_data->enable_reg_offset = SUN4I_IRQ_ENABLE_REG_OFFSET; - irq_ic_data->mask_reg_offset = SUN4I_IRQ_MASK_REG_OFFSET; - irq_ic_data->irq_base = of_iomap(node, 0); if (!irq_ic_data->irq_base) panic("%pOF: unable to map IC registers\n", @@ -149,7 +142,41 @@ static int __init sun4i_of_init(struct device_node *node, return 0; } -IRQCHIP_DECLARE(allwinner_sun4i_ic, "allwinner,sun4i-a10-ic", sun4i_of_init); + +static int __init sun4i_ic_of_init(struct device_node *node, + struct device_node *parent) +{ + irq_ic_data = kzalloc(sizeof(struct sun4i_irq_chip_data), GFP_KERNEL); + if (!irq_ic_data) { + pr_err("kzalloc failed!\n"); + return -ENOMEM; + } + + irq_ic_data->enable_reg_offset = SUN4I_IRQ_ENABLE_REG_OFFSET; + irq_ic_data->mask_reg_offset = SUN4I_IRQ_MASK_REG_OFFSET; + + return sun4i_of_init(node, parent); +} + +IRQCHIP_DECLARE(allwinner_sun4i_ic, "allwinner,sun4i-a10-ic", sun4i_ic_of_init); + +static int __init suniv_ic_of_init(struct device_node *node, + struct device_node *parent) +{ + irq_ic_data = kzalloc(sizeof(struct sun4i_irq_chip_data), GFP_KERNEL); + if (!irq_ic_data) { + pr_err("kzalloc failed!\n"); + return -ENOMEM; + } + + irq_ic_data->enable_reg_offset = SUNIV_IRQ_ENABLE_REG_OFFSET; + irq_ic_data->mask_reg_offset = SUNIV_IRQ_MASK_REG_OFFSET; + + return sun4i_of_init(node, parent); +} + +IRQCHIP_DECLARE(allwinner_sunvi_ic, "allwinner,suniv-f1c100s-ic", + suniv_ic_of_init); static void __exception_irq_entry sun4i_handle_irq(struct pt_regs *regs) { From patchwork Sun Dec 2 20:23:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mesih Kilinc X-Patchwork-Id: 1006564 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="gLGP7GIa"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 437KPg6BbQz9s8r for ; Mon, 3 Dec 2018 07:25:27 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725941AbeLBUYb (ORCPT ); Sun, 2 Dec 2018 15:24:31 -0500 Received: from mail-wm1-f68.google.com ([209.85.128.68]:32825 "EHLO mail-wm1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725835AbeLBUYa (ORCPT ); Sun, 2 Dec 2018 15:24:30 -0500 Received: by mail-wm1-f68.google.com with SMTP id r24so5502554wmh.0; Sun, 02 Dec 2018 12:24:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=JOM18/2JI/XRqmtoCiSEfwWrBMkMvuRt2TRd7mJVRjI=; b=gLGP7GIaVXawVef7RXWc0UwDAdtOX2LMpmP0FaeI+zFg1FlFTMrX3BSsca8bF9a1CP htQqoMaoPCjg0ow8siWQ8AlVeUhYf2usojFv1/xQzM3HyX+NjzHZsRfzFLglgq8I6WhV Lu2aRcwTs9KJhFKZRXFLZPzOjpMmd3WRDRlfCKkfoJlQZEFbsHB0o1rwDzBBM5L/5lRI nwl0tOlgsAp6ghGbmgMpDdmxXDvNwqbpiTPT6hJbOl4Xw/v3TYEbJOQ2L/PswYpJaThS t6oRqUfzj03DphaveXQWD9ZJ/jIMeq3r9vF0xUQdlPd9Pln5O2oMXVipr+VHmXwG9bBf DJYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=JOM18/2JI/XRqmtoCiSEfwWrBMkMvuRt2TRd7mJVRjI=; b=gvnCWxuq+9YuVs5mtwfo4tWJ35/YdNYbKb7+HOyYvNqCNBZ5c+pivydpN5YXqRxXd1 S35ToM+zgun8UbHwTOMsGfglRTpxZCkZoZj5Kr4xtvQzzE/yKjyCw3EfYaKC+SPnGfpm tCFpBaKR9FkCUaG/Aj3UiO1VYAlY/VCtPBF71CAJhLo7M9EBqEcgw8NR7Usr8yILckEp Tp8Kc8XtPV1RvvGCc5wHKnVSAajUCvp1kx0iRgMxk4qE6UxY854EgwEFvmZfuM+Gt/oY 7XNDi+ctUkYwGvhFDOAFf1hDyTDy2TFUWa3vuFXjBgzZ5IWFkpt93igsKd5B6eBsgEtT K+LQ== X-Gm-Message-State: AA+aEWa1IAOgyBTqEXpt250kB37iKq/FpfrneUZ3FpH5N/txVntshYV8 V3NgqGn0+mMYhVkAkU6BlCmvCE57CfI= X-Google-Smtp-Source: AFSGD/W7QX4J2lsvaA8NvQCdiuL27IRzzpKO6FhpOjj25mfcInqV8rBl40DwmYhmRdkims1AAu47BQ== X-Received: by 2002:a1c:3e84:: with SMTP id l126-v6mr5546933wma.91.1543782264458; Sun, 02 Dec 2018 12:24:24 -0800 (PST) Received: from ThinkPad.home ([185.219.177.152]) by smtp.gmail.com with ESMTPSA id l3sm14451510wma.44.2018.12.02.12.24.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 02 Dec 2018 12:24:23 -0800 (PST) From: Mesih Kilinc To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com Cc: Mesih Kilinc , Maxime Ripard , Chen-Yu Tsai , Russell King , Daniel Lezcano , Marc Zyngier , Linus Walleij , Icenowy Zheng , Rob Herring , Julian Calaby Subject: [PATCH v6 08/17] dt-bindings: timer: Add Allwinner suniv timer Date: Sun, 2 Dec 2018 23:23:42 +0300 Message-Id: <50f5d37e67d9aaf88c911aa614a7a520a9179996.1543781680.git.mesihkilinc@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add compatible string for Allwinner suniv timer which is similar to sun4i timer. Signed-off-by: Mesih Kilinc Acked-by: Maxime Ripard Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt b/Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt index 5c2e235..3da9d51 100644 --- a/Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt +++ b/Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt @@ -2,7 +2,9 @@ Allwinner A1X SoCs Timer Controller Required properties: -- compatible : should be "allwinner,sun4i-a10-timer" +- compatible : should be one of the following: + "allwinner,sun4i-a10-timer" + "allwinner,suniv-f1c100s-timer" - reg : Specifies base physical address and size of the registers. - interrupts : The interrupt of the first timer - clocks: phandle to the source clock (usually a 24 MHz fixed clock) From patchwork Sun Dec 2 20:23:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mesih Kilinc X-Patchwork-Id: 1006563 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="M+Qj1ubQ"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 437KPd1TSTz9s9h for ; Mon, 3 Dec 2018 07:25:25 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725954AbeLBUYc (ORCPT ); Sun, 2 Dec 2018 15:24:32 -0500 Received: from mail-wm1-f67.google.com ([209.85.128.67]:40631 "EHLO mail-wm1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725710AbeLBUYc (ORCPT ); Sun, 2 Dec 2018 15:24:32 -0500 Received: by mail-wm1-f67.google.com with SMTP id q26so3646477wmf.5; Sun, 02 Dec 2018 12:24:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=X2MJDswe0qbs6RG81mMPQ4p4MRYjzcSOeYYQ8FhXgr8=; b=M+Qj1ubQFvaREfl4/OBN9UUta+ly3CdzpG/BcCRSAwkE/jYCGhNwzHaRZFQ/gBQQ46 j8EGEIa1ktgegY2zOf2IHSNEK85pIFk3tuCM7zGLAlGQEoZzHZDwwpc87Aa7zgCFkzWB WmmFhL66zj91hyJsP4/4CTDej1Kwwz6c/i4P4ig9rn8NqDzQXD2DYW0WS53p74hoF9UQ oHaMoMZ+sxYXFYrDDJM8uO0MpGbVB+nvHYQY2U6rUGlSB5QwjWLF8TmFjGBCXHNuRF7D ahepO74vR3pMwAlcv7tIfUKK79K7pl2ByV08w35uZUCephJz1ltlDgGazoB3a6wCA2yc V0aw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=X2MJDswe0qbs6RG81mMPQ4p4MRYjzcSOeYYQ8FhXgr8=; b=edOqluz/BUFgqAgJ3byWAw0PT+4Z4nkIqR+AgbOO7xlESuitrTmUIz9a41cCDo/4z8 cSAi1P0441SDC9XMxi0cOQjwmDZASsEXQK7Nh33bQg9Rp9uzOoHCj6nxF3Gdg64WGEjr H4CF+/0mWUbANaUut4ElrrdiBdJJxAQNlehE/f1GvkROrPX5r7lG/UCWZfa54/BLNEJz orz9BzZfC/wfgQyzssPrZvmWvEF/DeoO38YH6vmrd12uu5P1gRlrrgc1pDa7g4q8lR1s i6/uwZEL3YU74LRsxfZzgxl8xrjXqzsWFoQJmHJunrzlMsAE7Xp9NTd+VkvWdWuNWkxH E75w== X-Gm-Message-State: AA+aEWZZVSguD7LgLrjRK9fpvLbMIx33O83BksCxS7XRg8b2iVm0MyXu DyIRCP3a0PKmYNljVQnsgCsPQMRQnLg= X-Google-Smtp-Source: AFSGD/UqjgLR3cwcry2yhqBeBLwEwmExmps8Kw8/WEGYd9+uBz+JNpuEQuiKyO1AaNIZaWgRWqvvVw== X-Received: by 2002:a1c:c181:: with SMTP id r123-v6mr6011173wmf.82.1543782266161; Sun, 02 Dec 2018 12:24:26 -0800 (PST) Received: from ThinkPad.home ([185.219.177.152]) by smtp.gmail.com with ESMTPSA id l3sm14451510wma.44.2018.12.02.12.24.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 02 Dec 2018 12:24:25 -0800 (PST) From: Mesih Kilinc To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com Cc: Mesih Kilinc , Maxime Ripard , Chen-Yu Tsai , Russell King , Daniel Lezcano , Marc Zyngier , Linus Walleij , Icenowy Zheng , Rob Herring , Julian Calaby Subject: [PATCH v6 09/17] clocksource: sun4i: add a compatible for suniv Date: Sun, 2 Dec 2018 23:23:43 +0300 Message-Id: <2b0e0a33b1e99f0f33d2eebd44de38bae9140bca.1543781680.git.mesihkilinc@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The suniv (new F-series) chip has a timer with less functionality than the A10 timer, e.g. it has only 3 channels. Add a new compatible for it. As we didn't use the extra channels on A10 either now, the code needn't to be changed. The suniv chip is based on ARM926EJ-S CPU, thus it has no architecture timer. Register sun4i_timer as sched_clock on it. Signed-off-by: Mesih Kilinc Acked-by: Maxime Ripard Acked-by: Daniel Lezcano --- drivers/clocksource/sun4i_timer.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/clocksource/sun4i_timer.c b/drivers/clocksource/sun4i_timer.c index 6e0180a..65f38f6 100644 --- a/drivers/clocksource/sun4i_timer.c +++ b/drivers/clocksource/sun4i_timer.c @@ -186,7 +186,8 @@ static int __init sun4i_timer_init(struct device_node *node) */ if (of_machine_is_compatible("allwinner,sun4i-a10") || of_machine_is_compatible("allwinner,sun5i-a13") || - of_machine_is_compatible("allwinner,sun5i-a10s")) + of_machine_is_compatible("allwinner,sun5i-a10s") || + of_machine_is_compatible("allwinner,suniv-f1c100s")) sched_clock_register(sun4i_timer_sched_read, 32, timer_of_rate(&to)); @@ -218,3 +219,5 @@ static int __init sun4i_timer_init(struct device_node *node) } TIMER_OF_DECLARE(sun4i, "allwinner,sun4i-a10-timer", sun4i_timer_init); +TIMER_OF_DECLARE(suniv, "allwinner,suniv-f1c100s-timer", + sun4i_timer_init); From patchwork Sun Dec 2 20:23:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mesih Kilinc X-Patchwork-Id: 1006550 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="gj+80Ode"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 437KNc13MHz9sCQ for ; Mon, 3 Dec 2018 07:24:32 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725983AbeLBUYe (ORCPT ); Sun, 2 Dec 2018 15:24:34 -0500 Received: from mail-wr1-f68.google.com ([209.85.221.68]:46694 "EHLO mail-wr1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725835AbeLBUYd (ORCPT ); Sun, 2 Dec 2018 15:24:33 -0500 Received: by mail-wr1-f68.google.com with SMTP id l9so10047831wrt.13; Sun, 02 Dec 2018 12:24:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=tGbSsIW2SbVXCg2177J/dhUcc17dCh4iHBqaTiJQmZQ=; b=gj+80OdebSSVq5nefzz3NW171uHq85/iL3ZzgkH8altvMKjQqGTaQMu4z+nbvSKCPP 4A5kkAhOzJOf8PYGQmDfVs1PRDVJEne2d965qhxeMJtv3qY7+ItYIkzom6S2qvokP3tR wpDr0FIo1k7F7fK7Nm7svwptMgykTa5TeBzpuv2wRsIvzC0xjWZU1LEWp/31yVot3/+T t1+rCWJeIQHxYm1izibJAkZpq7l1m74z3v+GoqUVUfwRZsttzeOz5cnbL23PthnFu8HY HAKTaV9IKPYgi/OUuzIoyJOGC2CHPq9o+bHh0eNrHWcCl+vvO6uGB2APN1Ig+p7DOLPK ZTmQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=tGbSsIW2SbVXCg2177J/dhUcc17dCh4iHBqaTiJQmZQ=; b=nDrJn1zdUo5L98W4hdMXvHs8aSyJJZPJXccJ/9YT2GyevJMHahDay0U2ZtU5JY+XMJ yR5b3Bh4ex6hJGGO1KVpKG0JhUhLfpQb1NScNUqLkQ1v82yf7Y+C0wKtQJ6LFiqZmi6J UKNOqx9w02rsu2vL26tS6wt21HmSulLrgGcS69vtifNcmTSQQaepc2WBWvtWKcAd8qRl HxLrPBUJ1XK6mnQaBEvNun2Kjo31CzxEzgzc4BuLHEyaToB3RBlkxhqWXx3omkmBOZiW BhEjGlrzyV+kHoyURvoUMImODLbDx1ixhFygyuI8ov1ZNQT/g6rBSjpO/pdgQp6V3SiX 7EPQ== X-Gm-Message-State: AA+aEWaTNioH1qCJ+F7wagqdNnqzm1gDG8npzJz4dWTjK0murWFKqDq0 V5of7F+9amR6QHZsEmTcwZxm69N6hKs= X-Google-Smtp-Source: AFSGD/UDZGcVXa7xLpVupO30EWsZ/e6ViKVGcMCI0S3Z7YAkyXlUSnC2Lcb246MQfkxU4uJgO+N8cg== X-Received: by 2002:adf:8421:: with SMTP id 30mr12119622wrf.153.1543782267898; Sun, 02 Dec 2018 12:24:27 -0800 (PST) Received: from ThinkPad.home ([185.219.177.152]) by smtp.gmail.com with ESMTPSA id l3sm14451510wma.44.2018.12.02.12.24.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 02 Dec 2018 12:24:27 -0800 (PST) From: Mesih Kilinc To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com Cc: Mesih Kilinc , Maxime Ripard , Chen-Yu Tsai , Russell King , Daniel Lezcano , Marc Zyngier , Linus Walleij , Icenowy Zheng , Rob Herring , Julian Calaby Subject: [PATCH v6 10/17] dt-bindings: pinctrl: Add Allwinner suniv F1C100s pinctrl Date: Sun, 2 Dec 2018 23:23:44 +0300 Message-Id: <9e222e14e31fd28fd5400d50259f77fc89273f5d.1543781680.git.mesihkilinc@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add compatible string for Allwinner suniv F1C100s SoC's pinctrl. Signed-off-by: Mesih Kilinc Acked-by: Maxime Ripard Patch applied to the pin control tree for v4.21. --- Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt index 258a464..a7f7133 100644 --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt @@ -29,6 +29,7 @@ Required properties: "allwinner,sun50i-h5-pinctrl" "allwinner,sun50i-h6-pinctrl" "allwinner,sun50i-h6-r-pinctrl" + "allwinner,suniv-f1c100s-pinctrl" "nextthing,gr8-pinctrl" - reg: Should contain the register physical address and length for the From patchwork Sun Dec 2 20:23:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mesih Kilinc X-Patchwork-Id: 1006559 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="YBA0QM5b"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 437KPL3CYbz9sBQ for ; Mon, 3 Dec 2018 07:25:10 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725990AbeLBUYi (ORCPT ); Sun, 2 Dec 2018 15:24:38 -0500 Received: from mail-wr1-f68.google.com ([209.85.221.68]:38263 "EHLO mail-wr1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725984AbeLBUYh (ORCPT ); Sun, 2 Dec 2018 15:24:37 -0500 Received: by mail-wr1-f68.google.com with SMTP id v13so10054616wrw.5; Sun, 02 Dec 2018 12:24:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Ev11KvbTIafEFzHvK/2w3PWoFb4QTPWkxQGfu8Exr1E=; b=YBA0QM5bHjzWob/D0W/tHk1MbCX9NXJz81tt0ZeDV2ROseL8IGnfJesLORqiigRmIX 5C0/CrX0dM1BwYLvk1SbEogcrpbiK7R2YB3muKswARmuopMS2YsSZiPX4p+oCSsfqYxi EcEWyobUsaokwJa/WsJ4XV7fNzoBHl06KZTCC8h7UfpR9UDj/OaVSG47mWlS8M/HGVFp TAWLoKqW5gGPAdf4KNbfQSlCVkWGdTi3su3YEpoOG8SKSbELG350QNql9ctkgA5gihEc T3CZhe3100B0IBNO1CFTw/+YMRipfJCDQFu3RbLZs5RoqK9sH/M8sIdTZGta8pdkT7ir Jw9A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Ev11KvbTIafEFzHvK/2w3PWoFb4QTPWkxQGfu8Exr1E=; b=r3InhEwF/sVlSLUSu3GRGhkW9lDljrTloJRLN3smjJFgUNQ4MoPfmhD5PPgYVXDM72 fEy9P4YPDf7xhnSk+sXAkIwf3NbrQuDDlKME714sGCJ0Mz/8C8MUaMHaSJR6/aSdgaqS AZ28+9vnxZbHgSZ69RWx0q72/AI0vL9Ys78Dw7eBbcOAwnx2EeWzqLsypkRg8DNKtNdw GZ+BuxffnFff1nB55imqAyz4OJbIYe6zTp0B7+OqPdjUfZXDdNWr3o4E40ngKINteyWw LFLfSJ86HNC9/lJ/pQ8wll12H9UjY//1NHi8i5aKxM1j9hHGLB3EzewVGG+FiZIKeebC WYFg== X-Gm-Message-State: AA+aEWZnX1c3Nepsftr1vUBKCp9pHsyCLntt8nzCHCdWWzzZ/J9mEDM0 ZLvvTYHIb2Um4QnNjvpQVUexMlj+efg= X-Google-Smtp-Source: AFSGD/XiEbH3Gikq+fwiMtc7cBCK4gDJonKwensh7TilLpxcBMfBzvR7dLN1ku07/ybi3U+Spu+TXA== X-Received: by 2002:a5d:68c3:: with SMTP id p3mr12119990wrw.34.1543782269920; Sun, 02 Dec 2018 12:24:29 -0800 (PST) Received: from ThinkPad.home ([185.219.177.152]) by smtp.gmail.com with ESMTPSA id l3sm14451510wma.44.2018.12.02.12.24.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 02 Dec 2018 12:24:29 -0800 (PST) From: Mesih Kilinc To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com Cc: Mesih Kilinc , Maxime Ripard , Chen-Yu Tsai , Russell King , Daniel Lezcano , Marc Zyngier , Linus Walleij , Icenowy Zheng , Rob Herring , Julian Calaby Subject: [PATCH v6 11/17] pinctrl: sunxi: add support for suniv F1C100s (newer F-series SoCs) Date: Sun, 2 Dec 2018 23:23:45 +0300 Message-Id: <668e78ee04771c491a91d1f2bd054b252782c4dd.1543781680.git.mesihkilinc@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The suniv F1C100s chip (several new F-series SoCs) of Allwinner has a pin controller like other SoCs from Allwinner. Add support for it. Signed-off-by: Mesih Kilinc Acked-by: Maxime Ripard Patch applied to the pin control tree for v4.21. --- drivers/pinctrl/sunxi/Kconfig | 4 + drivers/pinctrl/sunxi/Makefile | 1 + drivers/pinctrl/sunxi/pinctrl-suniv-f1c100s.c | 416 ++++++++++++++++++++++++++ 3 files changed, 421 insertions(+) create mode 100644 drivers/pinctrl/sunxi/pinctrl-suniv-f1c100s.c diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig index 95282cd..a731fc9 100644 --- a/drivers/pinctrl/sunxi/Kconfig +++ b/drivers/pinctrl/sunxi/Kconfig @@ -6,6 +6,10 @@ config PINCTRL_SUNXI select GENERIC_PINCONF select GPIOLIB +config PINCTRL_SUNIV_F1C100S + def_bool MACH_SUNIV + select PINCTRL_SUNXI + config PINCTRL_SUN4I_A10 def_bool MACH_SUN4I || MACH_SUN7I || MACH_SUN8I select PINCTRL_SUNXI diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile index adb8443..fafcdae 100644 --- a/drivers/pinctrl/sunxi/Makefile +++ b/drivers/pinctrl/sunxi/Makefile @@ -3,6 +3,7 @@ obj-y += pinctrl-sunxi.o # SoC Drivers +obj-$(CONFIG_PINCTRL_SUNIV_F1C100S) += pinctrl-suniv-f1c100s.o obj-$(CONFIG_PINCTRL_SUN4I_A10) += pinctrl-sun4i-a10.o obj-$(CONFIG_PINCTRL_SUN5I) += pinctrl-sun5i.o obj-$(CONFIG_PINCTRL_SUN6I_A31) += pinctrl-sun6i-a31.o diff --git a/drivers/pinctrl/sunxi/pinctrl-suniv-f1c100s.c b/drivers/pinctrl/sunxi/pinctrl-suniv-f1c100s.c new file mode 100644 index 0000000..2801ca7 --- /dev/null +++ b/drivers/pinctrl/sunxi/pinctrl-suniv-f1c100s.c @@ -0,0 +1,416 @@ +/* + * Allwinner new F-series F1C100s SoC (suniv) pinctrl driver. + * + * Copyright (C) 2018 Icenowy Zheng + * + * Icenowy Zheng + * + * Copyright (C) 2014 Jackie Hwang + * + * Jackie Hwang + * + * Copyright (C) 2014 Chen-Yu Tsai + * + * Chen-Yu Tsai + * + * Copyright (C) 2014 Maxime Ripard + * + * Maxime Ripard + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include + +#include "pinctrl-sunxi.h" +static const struct sunxi_desc_pin suniv_f1c100s_pins[] = { + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "rtp"), /* X1 */ + SUNXI_FUNCTION(0x4, "i2s"), /* BCLK */ + SUNXI_FUNCTION(0x5, "uart1"), /* RTS */ + SUNXI_FUNCTION(0x6, "spi1")), /* CS */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "rtp"), /* X2 */ + SUNXI_FUNCTION(0x4, "i2s"), /* LRCK */ + SUNXI_FUNCTION(0x5, "uart1"), /* CTS */ + SUNXI_FUNCTION(0x6, "spi1")), /* MOSI */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "rtp"), /* Y1 */ + SUNXI_FUNCTION(0x3, "pwm0"), /* PWM0 */ + SUNXI_FUNCTION(0x4, "i2s"), /* IN */ + SUNXI_FUNCTION(0x5, "uart1"), /* RX */ + SUNXI_FUNCTION(0x6, "spi1")), /* MOSI */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "rtp"), /* Y2 */ + SUNXI_FUNCTION(0x3, "ir0"), /* RX */ + SUNXI_FUNCTION(0x4, "i2s"), /* OUT */ + SUNXI_FUNCTION(0x5, "uart1"), /* TX */ + SUNXI_FUNCTION(0x6, "spi1")), /* MISO */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "dram"), /* DQS0 */ + SUNXI_FUNCTION(0x3, "i2c1"), /* SCK */ + SUNXI_FUNCTION(0x4, "i2s"), /* BCLK */ + SUNXI_FUNCTION(0x5, "uart1"), /* RTS */ + SUNXI_FUNCTION(0x6, "spi1")), /* CS */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "dram"), /* DQS1 */ + SUNXI_FUNCTION(0x3, "i2c1"), /* SDA */ + SUNXI_FUNCTION(0x4, "i2s"), /* LRCK */ + SUNXI_FUNCTION(0x5, "uart1"), /* CTS */ + SUNXI_FUNCTION(0x6, "spi1")), /* MOSI */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "dram"), /* CKE */ + SUNXI_FUNCTION(0x3, "pwm0"), /* PWM0 */ + SUNXI_FUNCTION(0x4, "i2s"), /* IN */ + SUNXI_FUNCTION(0x5, "uart1"), /* RX */ + SUNXI_FUNCTION(0x6, "spi1")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "dram"), /* DDR_REF_D */ + SUNXI_FUNCTION(0x3, "ir0"), /* RX */ + SUNXI_FUNCTION(0x4, "i2s"), /* OUT */ + SUNXI_FUNCTION(0x5, "uart1"), /* TX */ + SUNXI_FUNCTION(0x6, "spi1")), /* MISO */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi0"), /* CLK */ + SUNXI_FUNCTION(0x3, "mmc1")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi0"), /* CS */ + SUNXI_FUNCTION(0x3, "mmc1")), /* CMD */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi0"), /* MISO */ + SUNXI_FUNCTION(0x3, "mmc1")), /* D0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi0"), /* MOSI */ + SUNXI_FUNCTION(0x3, "uart0")), /* TX */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D2 */ + SUNXI_FUNCTION(0x3, "i2c0"), /* SDA */ + SUNXI_FUNCTION(0x4, "rsb"), /* SDA */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D3 */ + SUNXI_FUNCTION(0x3, "uart1"), /* RTS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D4*/ + SUNXI_FUNCTION(0x3, "uart1"), /* CTS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D5 */ + SUNXI_FUNCTION(0x3, "uart1"), /* RX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D6 */ + SUNXI_FUNCTION(0x3, "uart1"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D7 */ + SUNXI_FUNCTION(0x3, "i2c1"), /* SCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D10 */ + SUNXI_FUNCTION(0x3, "i2c1"), /* SDA */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D11 */ + SUNXI_FUNCTION(0x3, "i2s"), /* MCLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D12 */ + SUNXI_FUNCTION(0x3, "i2s"), /* BCLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D13 */ + SUNXI_FUNCTION(0x3, "i2s"), /* LRCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D14 */ + SUNXI_FUNCTION(0x3, "i2s"), /* IN */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D15 */ + SUNXI_FUNCTION(0x3, "i2s"), /* OUT */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D18 */ + SUNXI_FUNCTION(0x3, "i2c0"), /* SCK */ + SUNXI_FUNCTION(0x4, "rsb"), /* SCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D19 */ + SUNXI_FUNCTION(0x3, "uart2"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D20 */ + SUNXI_FUNCTION(0x3, "lvds1"), /* RX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 14)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D21 */ + SUNXI_FUNCTION(0x3, "uart2"), /* RTS */ + SUNXI_FUNCTION(0x4, "i2c2"), /* SCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D22 */ + SUNXI_FUNCTION(0x3, "uart2"), /* CTS */ + SUNXI_FUNCTION(0x4, "i2c2"), /* SDA */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D23 */ + SUNXI_FUNCTION(0x3, "spdif"), /* OUT */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* CLK */ + SUNXI_FUNCTION(0x3, "spi0"), /* CS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 18)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* DE */ + SUNXI_FUNCTION(0x3, "spi0"), /* MOSI */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 19)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* HYSNC */ + SUNXI_FUNCTION(0x3, "spi0"), /* CLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 20)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* VSYNC */ + SUNXI_FUNCTION(0x3, "spi0"), /* MISO */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 21)), + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */ + SUNXI_FUNCTION(0x3, "lcd"), /* D0 */ + SUNXI_FUNCTION(0x4, "i2c2"), /* SCK */ + SUNXI_FUNCTION(0x5, "uart0"), /* RX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */ + SUNXI_FUNCTION(0x3, "lcd"), /* D1 */ + SUNXI_FUNCTION(0x4, "i2c2"), /* SDA */ + SUNXI_FUNCTION(0x5, "uart0"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* PCLK */ + SUNXI_FUNCTION(0x3, "lcd"), /* D8 */ + SUNXI_FUNCTION(0x4, "clk"), /* OUT */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D0 */ + SUNXI_FUNCTION(0x3, "lcd"), /* D9 */ + SUNXI_FUNCTION(0x4, "i2s"), /* BCLK */ + SUNXI_FUNCTION(0x5, "rsb"), /* SCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D1 */ + SUNXI_FUNCTION(0x3, "lcd"), /* D16 */ + SUNXI_FUNCTION(0x4, "i2s"), /* LRCK */ + SUNXI_FUNCTION(0x5, "rsb"), /* SDA */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D2 */ + SUNXI_FUNCTION(0x3, "lcd"), /* D17 */ + SUNXI_FUNCTION(0x4, "i2s"), /* IN */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D3 */ + SUNXI_FUNCTION(0x3, "pwm1"), /* PWM1 */ + SUNXI_FUNCTION(0x4, "i2s"), /* OUT */ + SUNXI_FUNCTION(0x5, "spdif"), /* OUT */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D4 */ + SUNXI_FUNCTION(0x3, "uart2"), /* TX */ + SUNXI_FUNCTION(0x4, "spi1"), /* CS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D5 */ + SUNXI_FUNCTION(0x3, "uart2"), /* RX */ + SUNXI_FUNCTION(0x4, "spi1"), /* MOSI */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D6 */ + SUNXI_FUNCTION(0x3, "uart2"), /* RTS */ + SUNXI_FUNCTION(0x4, "spi1"), /* CLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D7 */ + SUNXI_FUNCTION(0x3, "uart2"), /* CTS */ + SUNXI_FUNCTION(0x4, "spi1"), /* MISO */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 10)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "clk0"), /* OUT */ + SUNXI_FUNCTION(0x3, "i2c0"), /* SCK */ + SUNXI_FUNCTION(0x4, "ir"), /* RX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 11)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s"), /* MCLK */ + SUNXI_FUNCTION(0x3, "i2c0"), /* SDA */ + SUNXI_FUNCTION(0x4, "pwm0"), /* PWM0 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 12)), + + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */ + SUNXI_FUNCTION(0x3, "jtag"), /* MS */ + SUNXI_FUNCTION(0x4, "ir0"), /* MS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */ + SUNXI_FUNCTION(0x3, "dgb0"), /* DI */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */ + SUNXI_FUNCTION(0x3, "uart0"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */ + SUNXI_FUNCTION(0x3, "jtag"), /* DO */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */ + SUNXI_FUNCTION(0x3, "uart0"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */ + SUNXI_FUNCTION(0x3, "jtag"), /* CK */ + SUNXI_FUNCTION(0x4, "pwm1"), /* PWM1 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)), +}; + +static const struct sunxi_pinctrl_desc suniv_f1c100s_pinctrl_data = { + .pins = suniv_f1c100s_pins, + .npins = ARRAY_SIZE(suniv_f1c100s_pins), + .irq_banks = 3, +}; + +static int suniv_pinctrl_probe(struct platform_device *pdev) +{ + return sunxi_pinctrl_init(pdev, + &suniv_f1c100s_pinctrl_data); +} + +static const struct of_device_id suniv_f1c100s_pinctrl_match[] = { + { .compatible = "allwinner,suniv-f1c100s-pinctrl", }, + {} +}; + +static struct platform_driver suniv_f1c100s_pinctrl_driver = { + .probe = suniv_pinctrl_probe, + .driver = { + .name = "suniv-f1c100s-pinctrl", + .of_match_table = suniv_f1c100s_pinctrl_match, + }, +}; +builtin_platform_driver(suniv_f1c100s_pinctrl_driver); From patchwork Sun Dec 2 20:23:46 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mesih Kilinc X-Patchwork-Id: 1006561 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="aNUqTPbs"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 437KPR5N7Sz9sBh for ; Mon, 3 Dec 2018 07:25:15 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726079AbeLBUZO (ORCPT ); Sun, 2 Dec 2018 15:25:14 -0500 Received: from mail-wm1-f67.google.com ([209.85.128.67]:35014 "EHLO mail-wm1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725835AbeLBUYi (ORCPT ); Sun, 2 Dec 2018 15:24:38 -0500 Received: by mail-wm1-f67.google.com with SMTP id c126so3670222wmh.0; Sun, 02 Dec 2018 12:24:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=b3VT8ipXM4GVCZfalW4x+w8+g6CzhWh2u23wr46Xid4=; b=aNUqTPbso6m71CsDPncXaS+OD9GjWDC8sdZNTC5QUXKn5NR3XXevF+2rH7Kos/bZgq +HVpsXGjnXO2I61hUE4benHItT6tIgyGNYqMeOrS7HdRZDYkxBLH0YmGqR89wOjYPiYg lfcZW2ruOVm9y+auWUQAr2VxlodOPgEwepwWk9qtvg2QDO9jmtNi28noUbpf2ErVxw1h LTrD1SKoxVMDkwsfKbjMAIw1KrP7fX/A2Hl6v2VORzADCh8qMCUOCo93k48Tm2mwp7Iw ZgGnMqXIq+wMz3Qk9Yeb0iKaFTxrrksbYq/f09V/EuRZ+k2zyvheFhCgKrOkV31prfTK 6dlg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=b3VT8ipXM4GVCZfalW4x+w8+g6CzhWh2u23wr46Xid4=; b=MN/7sK1VoJFzNe9BBf2NHLz2yRgGzTD8wudygClarSH6Th7/tl7vxJLyJC4o2G0kei 1KmlUSNWyD8R7mFNfp7sXH6CXXJHeRpM+99/AtmB/eAyLadap+hrTvclmyB7ZeGqNTPr /oK8C/9bYnFGrM8MgaOUDbaP4z2H4O+Y0ODFvBoq3g9J6ppteoKjfh8x++WBTm9SWoVO qrCm11b5uegseS95q67mrm1NZTaVdoUm6A3O+D0sECIJoahVG2yCuT7T2dF0X1wKTw88 gCc5CbMAL+uzCyUcTN+l9gkqTEWTNjV3rB+k8RiKpqN2DhN/QmhTQNC0+DAvmRjPwBD7 GL+w== X-Gm-Message-State: AA+aEWYh7jeUMp7c2aQuQiFtzhVYQl2xJvgkXFhbSpp8SN0OF+/k4ZnH 6XXc7lgY+9Ifpx4CNejDyOcRlEmS1Q8= X-Google-Smtp-Source: AFSGD/VH0g5NGCrKj4K3ZKMdWMNXZ10pqp0zr3BBq6RdMbSLXd+fpFXumiuxq4rbqS8pJkeiQZPd7A== X-Received: by 2002:a1c:2807:: with SMTP id o7-v6mr5699286wmo.138.1543782271634; Sun, 02 Dec 2018 12:24:31 -0800 (PST) Received: from ThinkPad.home ([185.219.177.152]) by smtp.gmail.com with ESMTPSA id l3sm14451510wma.44.2018.12.02.12.24.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 02 Dec 2018 12:24:31 -0800 (PST) From: Mesih Kilinc To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com Cc: Mesih Kilinc , Maxime Ripard , Chen-Yu Tsai , Russell King , Daniel Lezcano , Marc Zyngier , Linus Walleij , Icenowy Zheng , Rob Herring , Julian Calaby Subject: [PATCH v6 12/17] dt-bindings: clock: Add Allwinner suniv F1C100s CCU Date: Sun, 2 Dec 2018 23:23:46 +0300 Message-Id: <963e6608b509ae7a83966c76b9d0fc7d8bf1c07b.1543781680.git.mesihkilinc@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add compatiple string for Allwinner suniv F1C100s CCU. Add clock and reset definitions. Signed-off-by: Mesih Kilinc Acked-by: Maxime Ripard Acked-by: Stephen Boyd --- .../devicetree/bindings/clock/sunxi-ccu.txt | 1 + include/dt-bindings/clock/suniv-ccu-f1c100s.h | 70 ++++++++++++++++++++++ include/dt-bindings/reset/suniv-ccu-f1c100s.h | 38 ++++++++++++ 3 files changed, 109 insertions(+) create mode 100644 include/dt-bindings/clock/suniv-ccu-f1c100s.h create mode 100644 include/dt-bindings/reset/suniv-ccu-f1c100s.h diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt index 47d2e90..e3bd88a 100644 --- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt +++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt @@ -22,6 +22,7 @@ Required properties : - "allwinner,sun50i-h5-ccu" - "allwinner,sun50i-h6-ccu" - "allwinner,sun50i-h6-r-ccu" + - "allwinner,suniv-f1c100s-ccu" - "nextthing,gr8-ccu" - reg: Must contain the registers base address and length diff --git a/include/dt-bindings/clock/suniv-ccu-f1c100s.h b/include/dt-bindings/clock/suniv-ccu-f1c100s.h new file mode 100644 index 0000000..f5ac155 --- /dev/null +++ b/include/dt-bindings/clock/suniv-ccu-f1c100s.h @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) + * + * Copyright (c) 2018 Icenowy Zheng + * + */ + +#ifndef _DT_BINDINGS_CLK_SUNIV_F1C100S_H_ +#define _DT_BINDINGS_CLK_SUNIV_F1C100S_H_ + +#define CLK_CPU 11 + +#define CLK_BUS_DMA 14 +#define CLK_BUS_MMC0 15 +#define CLK_BUS_MMC1 16 +#define CLK_BUS_DRAM 17 +#define CLK_BUS_SPI0 18 +#define CLK_BUS_SPI1 19 +#define CLK_BUS_OTG 20 +#define CLK_BUS_VE 21 +#define CLK_BUS_LCD 22 +#define CLK_BUS_DEINTERLACE 23 +#define CLK_BUS_CSI 24 +#define CLK_BUS_TVD 25 +#define CLK_BUS_TVE 26 +#define CLK_BUS_DE_BE 27 +#define CLK_BUS_DE_FE 28 +#define CLK_BUS_CODEC 29 +#define CLK_BUS_SPDIF 30 +#define CLK_BUS_IR 31 +#define CLK_BUS_RSB 32 +#define CLK_BUS_I2S0 33 +#define CLK_BUS_I2C0 34 +#define CLK_BUS_I2C1 35 +#define CLK_BUS_I2C2 36 +#define CLK_BUS_PIO 37 +#define CLK_BUS_UART0 38 +#define CLK_BUS_UART1 39 +#define CLK_BUS_UART2 40 + +#define CLK_MMC0 41 +#define CLK_MMC0_SAMPLE 42 +#define CLK_MMC0_OUTPUT 43 +#define CLK_MMC1 44 +#define CLK_MMC1_SAMPLE 45 +#define CLK_MMC1_OUTPUT 46 +#define CLK_I2S 47 +#define CLK_SPDIF 48 + +#define CLK_USB_PHY0 49 + +#define CLK_DRAM_VE 50 +#define CLK_DRAM_CSI 51 +#define CLK_DRAM_DEINTERLACE 52 +#define CLK_DRAM_TVD 53 +#define CLK_DRAM_DE_FE 54 +#define CLK_DRAM_DE_BE 55 + +#define CLK_DE_BE 56 +#define CLK_DE_FE 57 +#define CLK_TCON 58 +#define CLK_DEINTERLACE 59 +#define CLK_TVE2_CLK 60 +#define CLK_TVE1_CLK 61 +#define CLK_TVD 62 +#define CLK_CSI 63 +#define CLK_VE 64 +#define CLK_CODEC 65 +#define CLK_AVS 66 + +#endif diff --git a/include/dt-bindings/reset/suniv-ccu-f1c100s.h b/include/dt-bindings/reset/suniv-ccu-f1c100s.h new file mode 100644 index 0000000..6a4b438 --- /dev/null +++ b/include/dt-bindings/reset/suniv-ccu-f1c100s.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) + * + * Copyright (C) 2018 Icenowy Zheng + * + */ + +#ifndef _DT_BINDINGS_RST_SUNIV_F1C100S_H_ +#define _DT_BINDINGS_RST_SUNIV_F1C100S_H_ + +#define RST_USB_PHY0 0 +#define RST_BUS_DMA 1 +#define RST_BUS_MMC0 2 +#define RST_BUS_MMC1 3 +#define RST_BUS_DRAM 4 +#define RST_BUS_SPI0 5 +#define RST_BUS_SPI1 6 +#define RST_BUS_OTG 7 +#define RST_BUS_VE 8 +#define RST_BUS_LCD 9 +#define RST_BUS_DEINTERLACE 10 +#define RST_BUS_CSI 11 +#define RST_BUS_TVD 12 +#define RST_BUS_TVE 13 +#define RST_BUS_DE_BE 14 +#define RST_BUS_DE_FE 15 +#define RST_BUS_CODEC 16 +#define RST_BUS_SPDIF 17 +#define RST_BUS_IR 18 +#define RST_BUS_RSB 19 +#define RST_BUS_I2S0 20 +#define RST_BUS_I2C0 21 +#define RST_BUS_I2C1 22 +#define RST_BUS_I2C2 23 +#define RST_BUS_UART0 24 +#define RST_BUS_UART1 25 +#define RST_BUS_UART2 26 + +#endif /* _DT_BINDINGS_RST_SUNIV_F1C100S_H_ */ From patchwork Sun Dec 2 20:23:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mesih Kilinc X-Patchwork-Id: 1006556 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="WiU8VDmd"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 437KPF0CDTz9sBQ for ; Mon, 3 Dec 2018 07:25:05 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726016AbeLBUYm (ORCPT ); Sun, 2 Dec 2018 15:24:42 -0500 Received: from mail-wm1-f67.google.com ([209.85.128.67]:55662 "EHLO mail-wm1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725984AbeLBUYl (ORCPT ); Sun, 2 Dec 2018 15:24:41 -0500 Received: by mail-wm1-f67.google.com with SMTP id y139so3689663wmc.5; Sun, 02 Dec 2018 12:24:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=1VX9AgbPf8osA2Q9b9h/AoAGF/rTe3H+4X+LtF99svg=; b=WiU8VDmdslXJLTiUoBUzIwBOVaXrSlQkCm5HOCoyjPcxWmKudk1422qD8M0KLT1NkN JaxeEG2U0mR2XnJJuz9AzRDQTcgLXNmU1sqbGq765Ie3OwR6trT/qHWFdWtbM1YOJ3eD i0RQJuyxFKVfmCjqmzb6tsjk6FhWD0nt8AqqvwHy3mmTqLuLkIwYP1JX6etTvkpzX9pS 4sYom2kO0TYLhu2DTZ6Dz1ac5Adtr0SDrYOzfXIXC6TchGDxj5BKWl7sbHS29yYSeqsg 5TzynCO4HF3z7egA0Y/nx2jrbcA625R0HzFrT0C3eZuiAyxrZNn2MVAiGcz8F69byp0/ JKMQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=1VX9AgbPf8osA2Q9b9h/AoAGF/rTe3H+4X+LtF99svg=; b=qt62G8h8QmW0KKjBkusBsMrlebmG3hoUmBlaQG9ay/oowLaNaz41N6mm4QJJAbpalR FnDf0+9b0wfMo+CfZFhZpNLptl3XGn08+hWpGlqzyUjvE270Yl/Yo1x+nRQ0+PIN2FIw SSkWzRRDxcIxk1YRtzhp29G9y/UgoBDnTzcdF2w+0YcTvqw99hQwtyduFgJWux01I+vW 0MLCB3ascoQ7OtPzQuNPjYKBGcuvDeoIo5nAh6qg77coKSx/jK8u3/ROSHfuUoVWxNop MQJO3ZgYrpyJoW06coeYAn5YFOOUjIT715z+b8Fg06YAFtcIFyZLNiKfUeQJsBKIOcca FKWQ== X-Gm-Message-State: AA+aEWaCBpzYevuLHymTCl0xk87kEtdhdoqIRcZfoc50A9ow8pEkyw8B 7i+1t3FVYBD0p9A/vr/A5hTEjiC3aNw= X-Google-Smtp-Source: AFSGD/UqELMowyzgLqP+/wHCcSy/qw0cNIAY/rI5uH/45WWPZXDHaJCpNdFBETqf2DRps4RKzejVoQ== X-Received: by 2002:a1c:6707:: with SMTP id b7mr5817565wmc.138.1543782273571; Sun, 02 Dec 2018 12:24:33 -0800 (PST) Received: from ThinkPad.home ([185.219.177.152]) by smtp.gmail.com with ESMTPSA id l3sm14451510wma.44.2018.12.02.12.24.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 02 Dec 2018 12:24:33 -0800 (PST) From: Mesih Kilinc To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com Cc: Mesih Kilinc , Maxime Ripard , Chen-Yu Tsai , Russell King , Daniel Lezcano , Marc Zyngier , Linus Walleij , Icenowy Zheng , Rob Herring , Julian Calaby Subject: [PATCH v6 13/17] clk: sunxi-ng: add support for suniv F1C100s SoC Date: Sun, 2 Dec 2018 23:23:47 +0300 Message-Id: X-Mailer: git-send-email 2.7.4 In-Reply-To: References: Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The suniv F1C100s SoC (the chip in some new F-series products of Allwinner) has a CCU which seems to be a stripped version of the CCU in SoCs after sun6i. Add support for the CCU. Signed-off-by: Mesih Kilinc Acked-by: Maxime Ripard --- drivers/clk/sunxi-ng/Kconfig | 5 + drivers/clk/sunxi-ng/Makefile | 1 + drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c | 541 +++++++++++++++++++++++++++++++ drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h | 34 ++ 4 files changed, 581 insertions(+) create mode 100644 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c create mode 100644 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig index 826674d..429ea4a 100644 --- a/drivers/clk/sunxi-ng/Kconfig +++ b/drivers/clk/sunxi-ng/Kconfig @@ -6,6 +6,11 @@ config SUNXI_CCU if SUNXI_CCU +config SUNIV_F1C100S_CCU + bool "Support for the Allwinner newer F1C100s CCU" + default MACH_SUNIV + depends on MACH_SUNIV || COMPILE_TEST + config SUN50I_A64_CCU bool "Support for the Allwinner A64 CCU" default ARM64 && ARCH_SUNXI diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile index 4945470..4c7bee8 100644 --- a/drivers/clk/sunxi-ng/Makefile +++ b/drivers/clk/sunxi-ng/Makefile @@ -21,6 +21,7 @@ obj-y += ccu_nm.o obj-y += ccu_mp.o # SoC support +obj-$(CONFIG_SUNIV_F1C100S_CCU) += ccu-suniv-f1c100s.o obj-$(CONFIG_SUN50I_A64_CCU) += ccu-sun50i-a64.o obj-$(CONFIG_SUN50I_H6_CCU) += ccu-sun50i-h6.o obj-$(CONFIG_SUN50I_H6_R_CCU) += ccu-sun50i-h6-r.o diff --git a/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c b/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c new file mode 100644 index 0000000..ea335a6 --- /dev/null +++ b/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c @@ -0,0 +1,541 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (c) 2016 Icenowy Zheng + * + */ + +#include +#include + +#include "ccu_common.h" +#include "ccu_reset.h" + +#include "ccu_div.h" +#include "ccu_gate.h" +#include "ccu_mp.h" +#include "ccu_mult.h" +#include "ccu_nk.h" +#include "ccu_nkm.h" +#include "ccu_nkmp.h" +#include "ccu_nm.h" +#include "ccu_phase.h" + +#include "ccu-suniv-f1c100s.h" + +static struct ccu_nkmp pll_cpu_clk = { + .enable = BIT(31), + .lock = BIT(28), + + .n = _SUNXI_CCU_MULT(8, 5), + .k = _SUNXI_CCU_MULT(4, 2), + .m = _SUNXI_CCU_DIV(0, 2), + /* MAX is guessed by the BSP table */ + .p = _SUNXI_CCU_DIV_MAX(16, 2, 4), + + .common = { + .reg = 0x000, + .hw.init = CLK_HW_INIT("pll-cpu", "osc24M", + &ccu_nkmp_ops, + CLK_SET_RATE_UNGATE), + }, +}; + +/* + * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from + * the base (2x, 4x and 8x), and one variable divider (the one true + * pll audio). + * + * We don't have any need for the variable divider for now, so we just + * hardcode it to match with the clock names + */ +#define SUNIV_PLL_AUDIO_REG 0x008 + +static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base", + "osc24M", 0x008, + 8, 7, /* N */ + 0, 5, /* M */ + BIT(31), /* gate */ + BIT(28), /* lock */ + CLK_SET_RATE_UNGATE); + +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video", + "osc24M", 0x010, + 8, 7, /* N */ + 0, 4, /* M */ + BIT(24), /* frac enable */ + BIT(25), /* frac select */ + 270000000, /* frac rate 0 */ + 297000000, /* frac rate 1 */ + BIT(31), /* gate */ + BIT(28), /* lock */ + CLK_SET_RATE_UNGATE); + +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve", + "osc24M", 0x018, + 8, 7, /* N */ + 0, 4, /* M */ + BIT(24), /* frac enable */ + BIT(25), /* frac select */ + 270000000, /* frac rate 0 */ + 297000000, /* frac rate 1 */ + BIT(31), /* gate */ + BIT(28), /* lock */ + CLK_SET_RATE_UNGATE); + +static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr", + "osc24M", 0x020, + 8, 5, /* N */ + 4, 2, /* K */ + 0, 2, /* M */ + BIT(31), /* gate */ + BIT(28), /* lock */ + CLK_IS_CRITICAL); + +static struct ccu_nk pll_periph_clk = { + .enable = BIT(31), + .lock = BIT(28), + .k = _SUNXI_CCU_MULT(4, 2), + .n = _SUNXI_CCU_MULT(8, 5), + .common = { + .reg = 0x028, + .hw.init = CLK_HW_INIT("pll-periph", "osc24M", + &ccu_nk_ops, 0), + }, +}; + +static const char * const cpu_parents[] = { "osc32k", "osc24M", + "pll-cpu", "pll-cpu" }; +static SUNXI_CCU_MUX(cpu_clk, "cpu", cpu_parents, + 0x050, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT); + +static const char * const ahb_parents[] = { "osc32k", "osc24M", + "cpu", "pll-periph" }; +static const struct ccu_mux_var_prediv ahb_predivs[] = { + { .index = 3, .shift = 6, .width = 2 }, +}; +static struct ccu_div ahb_clk = { + .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO), + + .mux = { + .shift = 12, + .width = 2, + + .var_predivs = ahb_predivs, + .n_var_predivs = ARRAY_SIZE(ahb_predivs), + }, + + .common = { + .reg = 0x054, + .features = CCU_FEATURE_VARIABLE_PREDIV, + .hw.init = CLK_HW_INIT_PARENTS("ahb", + ahb_parents, + &ccu_div_ops, + 0), + }, +}; + +static struct clk_div_table apb_div_table[] = { + { .val = 0, .div = 2 }, + { .val = 1, .div = 2 }, + { .val = 2, .div = 4 }, + { .val = 3, .div = 8 }, + { /* Sentinel */ }, +}; +static SUNXI_CCU_DIV_TABLE(apb_clk, "apb", "ahb", + 0x054, 8, 2, apb_div_table, 0); + +static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb", + 0x060, BIT(6), 0); +static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb", + 0x060, BIT(8), 0); +static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb", + 0x060, BIT(9), 0); +static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb", + 0x060, BIT(14), 0); +static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb", + 0x060, BIT(20), 0); +static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb", + 0x060, BIT(21), 0); +static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb", + 0x060, BIT(24), 0); + +static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb", + 0x064, BIT(0), 0); +static SUNXI_CCU_GATE(bus_lcd_clk, "bus-lcd", "ahb", + 0x064, BIT(4), 0); +static SUNXI_CCU_GATE(bus_deinterlace_clk, "bus-deinterlace", "ahb", + 0x064, BIT(5), 0); +static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb", + 0x064, BIT(8), 0); +static SUNXI_CCU_GATE(bus_tvd_clk, "bus-tvd", "ahb", + 0x064, BIT(9), 0); +static SUNXI_CCU_GATE(bus_tve_clk, "bus-tve", "ahb", + 0x064, BIT(10), 0); +static SUNXI_CCU_GATE(bus_de_be_clk, "bus-de-be", "ahb", + 0x064, BIT(12), 0); +static SUNXI_CCU_GATE(bus_de_fe_clk, "bus-de-fe", "ahb", + 0x064, BIT(14), 0); + +static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb", + 0x068, BIT(0), 0); +static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb", + 0x068, BIT(1), 0); +static SUNXI_CCU_GATE(bus_ir_clk, "bus-ir", "apb", + 0x068, BIT(2), 0); +static SUNXI_CCU_GATE(bus_rsb_clk, "bus-rsb", "apb", + 0x068, BIT(3), 0); +static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb", + 0x068, BIT(12), 0); +static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb", + 0x068, BIT(16), 0); +static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb", + 0x068, BIT(17), 0); +static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb", + 0x068, BIT(18), 0); +static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb", + 0x068, BIT(19), 0); +static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb", + 0x068, BIT(20), 0); +static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb", + 0x068, BIT(21), 0); +static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb", + 0x068, BIT(22), 0); + +static const char * const mod0_default_parents[] = { "osc24M", "pll-periph" }; +static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088, + 0, 4, /* M */ + 16, 2, /* P */ + 24, 2, /* mux */ + BIT(31), /* gate */ + 0); + +static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0_sample", "mmc0", + 0x088, 20, 3, 0); +static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0_output", "mmc0", + 0x088, 8, 3, 0); + +static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c, + 0, 4, /* M */ + 16, 2, /* P */ + 24, 2, /* mux */ + BIT(31), /* gate */ + 0); + +static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1_sample", "mmc1", + 0x08c, 20, 3, 0); +static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1_output", "mmc1", + 0x08c, 8, 3, 0); + +static const char * const i2s_spdif_parents[] = { "pll-audio-8x", + "pll-audio-4x", + "pll-audio-2x", + "pll-audio" }; + +static SUNXI_CCU_MUX_WITH_GATE(i2s_clk, "i2s", i2s_spdif_parents, + 0x0b0, 16, 2, BIT(31), 0); + +static SUNXI_CCU_MUX_WITH_GATE(spdif_clk, "spdif", i2s_spdif_parents, + 0x0b4, 16, 2, BIT(31), 0); + +/* The BSP header file has a CIR_CFG, but no mod clock uses this definition */ + +static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M", + 0x0cc, BIT(8), 0); + +static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "pll-ddr", + 0x100, BIT(0), 0); +static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "pll-ddr", + 0x100, BIT(1), 0); +static SUNXI_CCU_GATE(dram_deinterlace_clk, "dram-deinterlace", + "pll-ddr", 0x100, BIT(2), 0); +static SUNXI_CCU_GATE(dram_tvd_clk, "dram-tvd", "pll-ddr", + 0x100, BIT(3), 0); +static SUNXI_CCU_GATE(dram_de_fe_clk, "dram-de-fe", "pll-ddr", + 0x100, BIT(24), 0); +static SUNXI_CCU_GATE(dram_de_be_clk, "dram-de-be", "pll-ddr", + 0x100, BIT(26), 0); + +static const char * const de_parents[] = { "pll-video", "pll-periph" }; +static const u8 de_table[] = { 0, 2, }; +static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_be_clk, "de-be", + de_parents, de_table, + 0x104, 0, 4, 24, 3, BIT(31), 0); + +static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_fe_clk, "de-fe", + de_parents, de_table, + 0x10c, 0, 4, 24, 3, BIT(31), 0); + +static const char * const tcon_parents[] = { "pll-video", "pll-video-2x" }; +static const u8 tcon_table[] = { 0, 2, }; +static SUNXI_CCU_MUX_TABLE_WITH_GATE(tcon_clk, "tcon", + tcon_parents, tcon_table, + 0x118, 24, 3, BIT(31), + CLK_SET_RATE_PARENT); + +static const char * const deinterlace_parents[] = { "pll-video", + "pll-video-2x" }; +static const u8 deinterlace_table[] = { 0, 2, }; +static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(deinterlace_clk, "deinterlace", + deinterlace_parents, deinterlace_table, + 0x11c, 0, 4, 24, 3, BIT(31), 0); + +static const char * const tve_clk2_parents[] = { "pll-video", + "pll-video-2x" }; +static const u8 tve_clk2_table[] = { 0, 2, }; +static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(tve_clk2_clk, "tve-clk2", + tve_clk2_parents, tve_clk2_table, + 0x120, 0, 4, 24, 3, BIT(31), 0); +static SUNXI_CCU_M_WITH_GATE(tve_clk1_clk, "tve-clk1", "tve-clk2", + 0x120, 8, 1, BIT(15), 0); + +static const char * const tvd_parents[] = { "pll-video", "osc24M", + "pll-video-2x" }; +static SUNXI_CCU_M_WITH_MUX_GATE(tvd_clk, "tvd", tvd_parents, + 0x124, 0, 4, 24, 3, BIT(31), 0); + +static const char * const csi_parents[] = { "pll-video", "osc24M" }; +static const u8 csi_table[] = { 0, 5, }; +static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_clk, "csi", csi_parents, csi_table, + 0x120, 0, 4, 8, 3, BIT(15), 0); + +/* + * TODO: BSP says the parent is pll-audio, however common sense and experience + * told us it should be pll-ve. pll-ve is totally not used in BSP code. + */ +static SUNXI_CCU_GATE(ve_clk, "ve", "pll-audio", 0x13c, BIT(31), 0); + +static SUNXI_CCU_GATE(codec_clk, "codec", "pll-audio", 0x140, BIT(31), 0); + +static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M", 0x144, BIT(31), 0); + +static struct ccu_common *suniv_ccu_clks[] = { + &pll_cpu_clk.common, + &pll_audio_base_clk.common, + &pll_video_clk.common, + &pll_ve_clk.common, + &pll_ddr0_clk.common, + &pll_periph_clk.common, + &cpu_clk.common, + &ahb_clk.common, + &apb_clk.common, + &bus_dma_clk.common, + &bus_mmc0_clk.common, + &bus_mmc1_clk.common, + &bus_dram_clk.common, + &bus_spi0_clk.common, + &bus_spi1_clk.common, + &bus_otg_clk.common, + &bus_ve_clk.common, + &bus_lcd_clk.common, + &bus_deinterlace_clk.common, + &bus_csi_clk.common, + &bus_tve_clk.common, + &bus_tvd_clk.common, + &bus_de_be_clk.common, + &bus_de_fe_clk.common, + &bus_codec_clk.common, + &bus_spdif_clk.common, + &bus_ir_clk.common, + &bus_rsb_clk.common, + &bus_i2s0_clk.common, + &bus_i2c0_clk.common, + &bus_i2c1_clk.common, + &bus_i2c2_clk.common, + &bus_pio_clk.common, + &bus_uart0_clk.common, + &bus_uart1_clk.common, + &bus_uart2_clk.common, + &mmc0_clk.common, + &mmc0_sample_clk.common, + &mmc0_output_clk.common, + &mmc1_clk.common, + &mmc1_sample_clk.common, + &mmc1_output_clk.common, + &i2s_clk.common, + &spdif_clk.common, + &usb_phy0_clk.common, + &dram_ve_clk.common, + &dram_csi_clk.common, + &dram_deinterlace_clk.common, + &dram_tvd_clk.common, + &dram_de_fe_clk.common, + &dram_de_be_clk.common, + &de_be_clk.common, + &de_fe_clk.common, + &tcon_clk.common, + &deinterlace_clk.common, + &tve_clk2_clk.common, + &tve_clk1_clk.common, + &tvd_clk.common, + &csi_clk.common, + &ve_clk.common, + &codec_clk.common, + &avs_clk.common, +}; + +static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio", + "pll-audio-base", 4, 1, CLK_SET_RATE_PARENT); +static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x", + "pll-audio-base", 2, 1, CLK_SET_RATE_PARENT); +static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x", + "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT); +static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x", + "pll-audio-base", 1, 2, CLK_SET_RATE_PARENT); +static CLK_FIXED_FACTOR(pll_video_2x_clk, "pll-video-2x", + "pll-video", 1, 2, 0); + +static struct clk_hw_onecell_data suniv_hw_clks = { + .hws = { + [CLK_PLL_CPU] = &pll_cpu_clk.common.hw, + [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw, + [CLK_PLL_AUDIO] = &pll_audio_clk.hw, + [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw, + [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw, + [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw, + [CLK_PLL_VIDEO] = &pll_video_clk.common.hw, + [CLK_PLL_VIDEO_2X] = &pll_video_2x_clk.hw, + [CLK_PLL_VE] = &pll_ve_clk.common.hw, + [CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw, + [CLK_PLL_PERIPH] = &pll_periph_clk.common.hw, + [CLK_CPU] = &cpu_clk.common.hw, + [CLK_AHB] = &ahb_clk.common.hw, + [CLK_APB] = &apb_clk.common.hw, + [CLK_BUS_DMA] = &bus_dma_clk.common.hw, + [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw, + [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw, + [CLK_BUS_DRAM] = &bus_dram_clk.common.hw, + [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw, + [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw, + [CLK_BUS_OTG] = &bus_otg_clk.common.hw, + [CLK_BUS_VE] = &bus_ve_clk.common.hw, + [CLK_BUS_LCD] = &bus_lcd_clk.common.hw, + [CLK_BUS_DEINTERLACE] = &bus_deinterlace_clk.common.hw, + [CLK_BUS_CSI] = &bus_csi_clk.common.hw, + [CLK_BUS_TVD] = &bus_tvd_clk.common.hw, + [CLK_BUS_TVE] = &bus_tve_clk.common.hw, + [CLK_BUS_DE_BE] = &bus_de_be_clk.common.hw, + [CLK_BUS_DE_FE] = &bus_de_fe_clk.common.hw, + [CLK_BUS_CODEC] = &bus_codec_clk.common.hw, + [CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw, + [CLK_BUS_IR] = &bus_ir_clk.common.hw, + [CLK_BUS_RSB] = &bus_rsb_clk.common.hw, + [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw, + [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw, + [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw, + [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw, + [CLK_BUS_PIO] = &bus_pio_clk.common.hw, + [CLK_BUS_UART0] = &bus_uart0_clk.common.hw, + [CLK_BUS_UART1] = &bus_uart1_clk.common.hw, + [CLK_BUS_UART2] = &bus_uart2_clk.common.hw, + [CLK_MMC0] = &mmc0_clk.common.hw, + [CLK_MMC0_SAMPLE] = &mmc0_sample_clk.common.hw, + [CLK_MMC0_OUTPUT] = &mmc0_output_clk.common.hw, + [CLK_MMC1] = &mmc1_clk.common.hw, + [CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw, + [CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw, + [CLK_I2S] = &i2s_clk.common.hw, + [CLK_SPDIF] = &spdif_clk.common.hw, + [CLK_USB_PHY0] = &usb_phy0_clk.common.hw, + [CLK_DRAM_VE] = &dram_ve_clk.common.hw, + [CLK_DRAM_CSI] = &dram_csi_clk.common.hw, + [CLK_DRAM_DEINTERLACE] = &dram_deinterlace_clk.common.hw, + [CLK_DRAM_TVD] = &dram_tvd_clk.common.hw, + [CLK_DRAM_DE_FE] = &dram_de_fe_clk.common.hw, + [CLK_DRAM_DE_BE] = &dram_de_be_clk.common.hw, + [CLK_DE_BE] = &de_be_clk.common.hw, + [CLK_DE_FE] = &de_fe_clk.common.hw, + [CLK_TCON] = &tcon_clk.common.hw, + [CLK_DEINTERLACE] = &deinterlace_clk.common.hw, + [CLK_TVE2_CLK] = &tve_clk2_clk.common.hw, + [CLK_TVE1_CLK] = &tve_clk1_clk.common.hw, + [CLK_TVD] = &tvd_clk.common.hw, + [CLK_CSI] = &csi_clk.common.hw, + [CLK_VE] = &ve_clk.common.hw, + [CLK_CODEC] = &codec_clk.common.hw, + [CLK_AVS] = &avs_clk.common.hw, + }, + .num = CLK_NUMBER, +}; + +static struct ccu_reset_map suniv_ccu_resets[] = { + [RST_USB_PHY0] = { 0x0cc, BIT(0) }, + + [RST_BUS_DMA] = { 0x2c0, BIT(6) }, + [RST_BUS_MMC0] = { 0x2c0, BIT(8) }, + [RST_BUS_MMC1] = { 0x2c0, BIT(9) }, + [RST_BUS_DRAM] = { 0x2c0, BIT(14) }, + [RST_BUS_SPI0] = { 0x2c0, BIT(20) }, + [RST_BUS_SPI1] = { 0x2c0, BIT(21) }, + [RST_BUS_OTG] = { 0x2c0, BIT(24) }, + [RST_BUS_VE] = { 0x2c4, BIT(0) }, + [RST_BUS_LCD] = { 0x2c4, BIT(4) }, + [RST_BUS_DEINTERLACE] = { 0x2c4, BIT(5) }, + [RST_BUS_CSI] = { 0x2c4, BIT(8) }, + [RST_BUS_TVD] = { 0x2c4, BIT(9) }, + [RST_BUS_TVE] = { 0x2c4, BIT(10) }, + [RST_BUS_DE_BE] = { 0x2c4, BIT(12) }, + [RST_BUS_DE_FE] = { 0x2c4, BIT(14) }, + [RST_BUS_CODEC] = { 0x2d0, BIT(0) }, + [RST_BUS_SPDIF] = { 0x2d0, BIT(1) }, + [RST_BUS_IR] = { 0x2d0, BIT(2) }, + [RST_BUS_RSB] = { 0x2d0, BIT(3) }, + [RST_BUS_I2S0] = { 0x2d0, BIT(12) }, + [RST_BUS_I2C0] = { 0x2d0, BIT(16) }, + [RST_BUS_I2C1] = { 0x2d0, BIT(17) }, + [RST_BUS_I2C2] = { 0x2d0, BIT(18) }, + [RST_BUS_UART0] = { 0x2d0, BIT(20) }, + [RST_BUS_UART1] = { 0x2d0, BIT(21) }, + [RST_BUS_UART2] = { 0x2d0, BIT(22) }, +}; + +static const struct sunxi_ccu_desc suniv_ccu_desc = { + .ccu_clks = suniv_ccu_clks, + .num_ccu_clks = ARRAY_SIZE(suniv_ccu_clks), + + .hw_clks = &suniv_hw_clks, + + .resets = suniv_ccu_resets, + .num_resets = ARRAY_SIZE(suniv_ccu_resets), +}; + +static struct ccu_pll_nb suniv_pll_cpu_nb = { + .common = &pll_cpu_clk.common, + /* copy from pll_cpu_clk */ + .enable = BIT(31), + .lock = BIT(28), +}; + +static struct ccu_mux_nb suniv_cpu_nb = { + .common = &cpu_clk.common, + .cm = &cpu_clk.mux, + .delay_us = 1, /* > 8 clock cycles at 24 MHz */ + .bypass_index = 1, /* index of 24 MHz oscillator */ +}; + +static void __init suniv_f1c100s_ccu_setup(struct device_node *node) +{ + void __iomem *reg; + u32 val; + + reg = of_io_request_and_map(node, 0, of_node_full_name(node)); + if (IS_ERR(reg)) { + pr_err("%pOF: Could not map the clock registers\n", node); + return; + } + + /* Force the PLL-Audio-1x divider to 4 */ + val = readl(reg + SUNIV_PLL_AUDIO_REG); + val &= ~GENMASK(19, 16); + writel(val | (3 << 16), reg + SUNIV_PLL_AUDIO_REG); + + sunxi_ccu_probe(node, reg, &suniv_ccu_desc); + + /* Gate then ungate PLL CPU after any rate changes */ + ccu_pll_notifier_register(&suniv_pll_cpu_nb); + + /* Reparent CPU during PLL CPU rate changes */ + ccu_mux_notifier_register(pll_cpu_clk.common.hw.clk, + &suniv_cpu_nb); +} +CLK_OF_DECLARE(suniv_f1c100s_ccu, "allwinner,suniv-f1c100s-ccu", + suniv_f1c100s_ccu_setup); diff --git a/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h b/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h new file mode 100644 index 0000000..39d06fe --- /dev/null +++ b/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0+ + * + * Copyright 2017 Icenowy Zheng + * + */ + +#ifndef _CCU_SUNIV_F1C100S_H_ +#define _CCU_SUNIV_F1C100S_H_ + +#include +#include + +#define CLK_PLL_CPU 0 +#define CLK_PLL_AUDIO_BASE 1 +#define CLK_PLL_AUDIO 2 +#define CLK_PLL_AUDIO_2X 3 +#define CLK_PLL_AUDIO_4X 4 +#define CLK_PLL_AUDIO_8X 5 +#define CLK_PLL_VIDEO 6 +#define CLK_PLL_VIDEO_2X 7 +#define CLK_PLL_VE 8 +#define CLK_PLL_DDR0 9 +#define CLK_PLL_PERIPH 10 + +/* CPU clock is exported */ + +#define CLK_AHB 12 +#define CLK_APB 13 + +/* All bus gates, DRAM gates and mod clocks are exported */ + +#define CLK_NUMBER (CLK_AVS + 1) + +#endif /* _CCU_SUNIV_F1C100S_H_ */ From patchwork Sun Dec 2 20:23:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mesih Kilinc X-Patchwork-Id: 1006557 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="bjxfy4Zx"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 437KPG4GbZz9sCh for ; Mon, 3 Dec 2018 07:25:06 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726012AbeLBUYm (ORCPT ); Sun, 2 Dec 2018 15:24:42 -0500 Received: from mail-wr1-f67.google.com ([209.85.221.67]:46698 "EHLO mail-wr1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726000AbeLBUYl (ORCPT ); Sun, 2 Dec 2018 15:24:41 -0500 Received: by mail-wr1-f67.google.com with SMTP id l9so10048010wrt.13; Sun, 02 Dec 2018 12:24:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=0dF58WahZEvNWNI14RwNxBlOsuvWUlXAKVfNdqdb48I=; b=bjxfy4Zx1SjlZDb5rL/xrvQHQET/ZFAd+Donf4xWLce8TAsWEv4j9eLj1rli6nKwHW Y2uWkSWVCCAn62qPiTFZw+SZlhn5PLRyNIXcmq5lUHhQgwUPVKbB9dhZNPC75l6/z9j4 y+B8JNAl09+IxsGVg1dILhEYPYBbDjfjM2w0+aWxrTkqmGXzCWWKA1FNn29RDpTJChDp 2f8xJeLyT0HTxenEeYKGTyzzlOmOqsnJcGWGC6pKiQrxyFSYbMb/8oR45xM47gljmYHN Qgl3X+s27T7lpz+LgQT6HGHON5bkZHnDj2+H3FlffBUL2xfnnf1pxDftSz7RyiCXJ/77 /o1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=0dF58WahZEvNWNI14RwNxBlOsuvWUlXAKVfNdqdb48I=; b=CiZBiBZmE8T9pchsAQEKKqmVGG5LVxfNTHqFINQirgDnXZFNvpnsOoPsmU1Y7PJPd6 kyfKh0nxaOCQt2F/E4zKLGc8idQjacwPkd/wYyDW8vNGa5YxnhlfhnEmd9ETrsARNPIN eioMSneBk/CqVXqc9F73lfHyKEK0yged8HrVQNzbhvY/rz8FshVd6j0jgsrgZ+cbDe1l oaRHWjJaOn9aLK4Wg4yicONebDEcLwAgvp1Evy7efuhmKAAeYL5UI+VaKmMkhGbp0Rsj 0bkVchUdb2w28KVEPwgAuFvUf1uOXxdrCXQxSH8dyIYx2Yvb1k9czgFJfFs8rUp5k+nR a8Tg== X-Gm-Message-State: AA+aEWZl6pEQ5o1sjsTZ68atHvdMFCpfZxiLt+q9nE47EC0iN6J8YiCJ pMaNpxq7jVMpx99XFFsf1c20Py5lQQI= X-Google-Smtp-Source: AFSGD/UIBMpoEYOixHcQIADhaHNr5OeWHuua7IJ0G0x5OlPs1bOGAvxLi6k5dK31vLPTSh1JVyZd6g== X-Received: by 2002:adf:891a:: with SMTP id s26mr11571809wrs.44.1543782275282; Sun, 02 Dec 2018 12:24:35 -0800 (PST) Received: from ThinkPad.home ([185.219.177.152]) by smtp.gmail.com with ESMTPSA id l3sm14451510wma.44.2018.12.02.12.24.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 02 Dec 2018 12:24:34 -0800 (PST) From: Mesih Kilinc To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com Cc: Mesih Kilinc , Maxime Ripard , Chen-Yu Tsai , Russell King , Daniel Lezcano , Marc Zyngier , Linus Walleij , Icenowy Zheng , Rob Herring , Julian Calaby Subject: [PATCH v6 14/17] dt-bindings: sram: Add Allwinner suniv F1C100s Date: Sun, 2 Dec 2018 23:23:48 +0300 Message-Id: <0b60c924d30ce3e04325214789de2c5b0403a056.1543781680.git.mesihkilinc@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The suniv ARMv5 F1C100s chip has similar sram controller to sun4i A10. Add compatible string for it. Signed-off-by: Mesih Kilinc Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/sram/sunxi-sram.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/sram/sunxi-sram.txt b/Documentation/devicetree/bindings/sram/sunxi-sram.txt index 62dd074..5c84850 100644 --- a/Documentation/devicetree/bindings/sram/sunxi-sram.txt +++ b/Documentation/devicetree/bindings/sram/sunxi-sram.txt @@ -19,6 +19,7 @@ Required properties: - "allwinner,sun50i-a64-sram-controller" (deprecated) - "allwinner,sun50i-a64-system-control" - "allwinner,sun50i-h6-system-control", "allwinner,sun50i-a64-system-control" + - "allwinner,suniv-f1c100s-system-control", "allwinner,sun4i-a10-system-control" - reg : sram controller register offset + length SRAM nodes @@ -58,6 +59,9 @@ The valid sections compatible for A64 are: The valid sections compatible for H6 are: - allwinner,sun50i-h6-sram-c, allwinner,sun50i-a64-sram-c +The valid sections compatible for F1C100s are: + - allwinner,suniv-f1c100s-sram-d, allwinner,sun4i-a10-sram-d + Devices using SRAM sections --------------------------- From patchwork Sun Dec 2 20:23:49 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mesih Kilinc X-Patchwork-Id: 1006555 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="c86y217+"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 437KP83bnWz9sBh for ; Mon, 3 Dec 2018 07:25:00 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726033AbeLBUYo (ORCPT ); Sun, 2 Dec 2018 15:24:44 -0500 Received: from mail-wr1-f66.google.com ([209.85.221.66]:39845 "EHLO mail-wr1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726014AbeLBUYn (ORCPT ); Sun, 2 Dec 2018 15:24:43 -0500 Received: by mail-wr1-f66.google.com with SMTP id t27so10059696wra.6; Sun, 02 Dec 2018 12:24:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=iD1UyqjCCFF08dz9kmj5kIY680LVUEWD9EKoGw4tLF8=; b=c86y217+EssT553fPEG7MQk86eyrX1V0dx+1thpVElww3Eq9XhMrWqUUftlMnaQMU7 cyl/SAf/SCDJW/6GZsw8tY45EQBKY39LJNbzuB683A0vYdXF4/HvVZd7Kjuaq1wJbP02 MNwUU8ioNr88gS8Pjaxq2LBtrAgRnUiHyYajpi6sQH/2kESVb9xtBIdPUwNW8OfhlYu/ Vz7I4KRYyRTB1bWrHpjGaOo/T+t18EGm9p7AAdMQ8y8R9aFX93vM/axlAZpkRd+EtDS5 iAAHuCl/k1abRlRFQ7/i2niHjhJCk+n/bcD7yF9mslZAKr1E7Ej7+0Sf8GUxuYLM4B55 mnNg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=iD1UyqjCCFF08dz9kmj5kIY680LVUEWD9EKoGw4tLF8=; b=kEy9LocqWQgFqncrWAFyIMa6+50hhQmrepCErs1umlBVz5smpWfn+cvgUD/QMFoW3p wJ35gnhvaLSLCeVagL4DLSUU7H3JiUwJfi5TfwS2U5N97lltmwhprr/7e0z/h27Y6XTz r5m7VBtrJVgRWyq7M60Re8GfNs5kVBPG4n1537vwhbj4ix5El2jqfOfUGuzhokI+cP3L f6seD8tLoG7Q8e48vaDN+/UsXtN0g8yTxONDM2VLNWLgEpwCwOH/H+tS+5/3r43jxT33 lissA/+aOdPscpSTxhGmHXL7CerC3lDwLbayXpXaNKt6WkoxbimPOEbpWWVC9M0Knn9T n7ug== X-Gm-Message-State: AA+aEWYgrWLfSh8UfpImvGmGJSLp8IVqeKCht74BjAYqgix01a/Gkus0 BtAXaP47MjYDbxTvzFI/jb+qr15hs00= X-Google-Smtp-Source: AFSGD/VPOOrnSKr8mzkgmLIdvSF++Z35odAHG4iAbEXTnXRN6wJoOxIskM6YjD5v5O+I7amaREuxQg== X-Received: by 2002:adf:b201:: with SMTP id u1mr11711337wra.165.1543782277021; Sun, 02 Dec 2018 12:24:37 -0800 (PST) Received: from ThinkPad.home ([185.219.177.152]) by smtp.gmail.com with ESMTPSA id l3sm14451510wma.44.2018.12.02.12.24.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 02 Dec 2018 12:24:36 -0800 (PST) From: Mesih Kilinc To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com Cc: Mesih Kilinc , Maxime Ripard , Chen-Yu Tsai , Russell King , Daniel Lezcano , Marc Zyngier , Linus Walleij , Icenowy Zheng , Rob Herring , Julian Calaby Subject: [PATCH v6 15/17] dt-bindings: watchdog: Add Allwinner ARMv5 F1C100s wdt Date: Sun, 2 Dec 2018 23:23:49 +0300 Message-Id: X-Mailer: git-send-email 2.7.4 In-Reply-To: References: Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Allwinner ARMv5 F1C100s has similar watchdog timer to sun6i A31. Add definition for it. Signed-off-by: Mesih Kilinc Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt b/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt index ed11ce0..4605525 100644 --- a/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt +++ b/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt @@ -6,6 +6,7 @@ Required properties: "allwinner,sun4i-a10-wdt" "allwinner,sun6i-a31-wdt" "allwinner,sun50i-a64-wdt","allwinner,sun6i-a31-wdt" + "allwinner,suniv-f1c100s-wdt", "allwinner,sun4i-a10-wdt" - reg : Specifies base physical address and size of the registers. Optional properties: From patchwork Sun Dec 2 20:23:50 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mesih Kilinc X-Patchwork-Id: 1006552 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="T2skOmWU"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 437KNq5k48z9sB7 for ; Mon, 3 Dec 2018 07:24:43 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726061AbeLBUYp (ORCPT ); Sun, 2 Dec 2018 15:24:45 -0500 Received: from mail-wr1-f67.google.com ([209.85.221.67]:45375 "EHLO mail-wr1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725984AbeLBUYp (ORCPT ); Sun, 2 Dec 2018 15:24:45 -0500 Received: by mail-wr1-f67.google.com with SMTP id v6so10023020wrr.12; Sun, 02 Dec 2018 12:24:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=9WG2eU/ejG4wAWToKoueA27/6ygzN1rLZLWAo8LIhNE=; b=T2skOmWUlvAkqf6eBm9og5ZfS9jT1KI23fo/nbKhhS856UmFfaUb8HwHgXouxyXthM sqoQ7sQP2T4sVDfkt+m/FOjxKdEwXC4uMOTqofGMZYfg3pHItllfWhd26mB9eeFbg1FC nN8elPRFBkCLS6+x3mMhqyVYB4IsnEhDMk/0nXmBVrB1rp60vpT4pxOmsdScTjjoTt0g y78LIjXNmm/ATEgZSit7wigak9HNNVPqEVJRruahzGnjCn0FOLQ6vzdxjgLU1ywH5ecz BitLT4LVFASPkDx3Wt9iVEtDFmlGMWFDqasRXxj9y8vnUwe9x/Y/fMBNhUSVPS8aSJwF OL0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=9WG2eU/ejG4wAWToKoueA27/6ygzN1rLZLWAo8LIhNE=; b=Cp8lRJWWA6rXts9843l9AEzwUoYFHv2CT7NbZjcS+785DdBIIr90w5pweqfMxWJlVV RyagDJT57wvWbqfysqnJx0MymIznp8x0dPXt1EKMVCj22rtjVSuV8iMx/LkPO0+ShmHC vQCTrUUtal1s8DBtsqIGN3R9HD/mo1mNhvpIXZSH5y9faeq6k6oLhfCor9TytBU0pIp1 RNu3tbt2pYDHrebnU5GUhLdWbBl5i3CP5qv9fAlz9xzkBH72rohQx1t9PImQHrIdYAZr EQYtDGGSQ3vep+EDz94P1ZgahYuRCZbLobgaXS2H0BEycTOVDaHfyTYx8AuUSMQl5RDO RHyg== X-Gm-Message-State: AA+aEWZnJu+3YZtzlX9Ar/1eigoUoNMM9QZDgU37Jhn1fQznlNxePDm/ A1LNTCgR0FVLoD/6mV6ncvqAMMITPYE= X-Google-Smtp-Source: AFSGD/XRntLJPSM0w/Zsn7h1n0X9PgvCcz+6P5fwxaPwEuoO7d0rpyeQLePdNF9RAuMCz6TteCsl2Q== X-Received: by 2002:adf:82e4:: with SMTP id 91mr12176031wrc.131.1543782278799; Sun, 02 Dec 2018 12:24:38 -0800 (PST) Received: from ThinkPad.home ([185.219.177.152]) by smtp.gmail.com with ESMTPSA id l3sm14451510wma.44.2018.12.02.12.24.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 02 Dec 2018 12:24:38 -0800 (PST) From: Mesih Kilinc To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com Cc: Mesih Kilinc , Maxime Ripard , Chen-Yu Tsai , Russell King , Daniel Lezcano , Marc Zyngier , Linus Walleij , Icenowy Zheng , Rob Herring , Julian Calaby Subject: [PATCH v6 16/17] ARM: dts: suniv: add initial DTSI file for F1C100s Date: Sun, 2 Dec 2018 23:23:50 +0300 Message-Id: X-Mailer: git-send-email 2.7.4 In-Reply-To: References: Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org F1C100s is one product with the suniv die, which has a 32MiB co-packaged DDR1 DRAM chip. As we have the support for suniv pin controller and CCU now, add a initial DTSI for it. Signed-off-by: Mesih Kilinc --- arch/arm/boot/dts/suniv-f1c100s.dtsi | 147 +++++++++++++++++++++++++++++++++++ 1 file changed, 147 insertions(+) create mode 100644 arch/arm/boot/dts/suniv-f1c100s.dtsi diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi new file mode 100644 index 0000000..aff5f90 --- /dev/null +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi @@ -0,0 +1,147 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR X11) +/* + * Copyright 2018 Icenowy Zheng + * Copyright 2018 Mesih Kilinc + */ + +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + + clocks { + osc24M: clk-24M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "osc24M"; + }; + + osc32k: clk-32k { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "osc32k"; + }; + }; + + cpus { + cpu { + compatible = "arm,arm926ej-s"; + device_type = "cpu"; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sram-controller@1c00000 { + compatible = "allwinner,suniv-f1c100s-system-control", + "allwinner,sun4i-a10-system-control"; + reg = <0x01c00000 0x30>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sram_d: sram@10000 { + compatible = "mmio-sram"; + reg = <0x00010000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00010000 0x1000>; + + otg_sram: sram-section@0 { + compatible = "allwinner,suniv-f1c100s-sram-d", + "allwinner,sun4i-a10-sram-d"; + reg = <0x0000 0x1000>; + status = "disabled"; + }; + }; + }; + + ccu: clock@1c20000 { + compatible = "allwinner,suniv-f1c100s-ccu"; + reg = <0x01c20000 0x400>; + clocks = <&osc24M>, <&osc32k>; + clock-names = "hosc", "losc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + intc: interrupt-controller@1c20400 { + compatible = "allwinner,suniv-f1c100s-ic"; + reg = <0x01c20400 0x400>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + pio: pinctrl@1c20800 { + compatible = "allwinner,suniv-f1c100s-pinctrl"; + reg = <0x01c20800 0x400>; + interrupts = <38>, <39>, <40>; + clocks = <&ccu 37>, <&osc24M>, <&osc32k>; + clock-names = "apb", "hosc", "losc"; + gpio-controller; + interrupt-controller; + #interrupt-cells = <3>; + #gpio-cells = <3>; + + uart0_pe_pins: uart0-pe-pins { + pins = "PE0", "PE1"; + function = "uart0"; + }; + }; + + timer@1c20c00 { + compatible = "allwinner,suniv-f1c100s-timer"; + reg = <0x01c20c00 0x90>; + interrupts = <13>; + clocks = <&osc24M>; + }; + + wdt: watchdog@1c20ca0 { + compatible = "allwinner,suniv-f1c100s-wdt", + "allwinner,sun4i-a10-wdt"; + reg = <0x01c20ca0 0x20>; + }; + + uart0: serial@1c25000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c25000 0x400>; + interrupts = <1>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu 38>; + resets = <&ccu 24>; + status = "disabled"; + }; + + uart1: serial@1c25400 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c25400 0x400>; + interrupts = <2>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu 39>; + resets = <&ccu 25>; + status = "disabled"; + }; + + uart2: serial@1c25800 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c25800 0x400>; + interrupts = <3>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu 40>; + resets = <&ccu 26>; + status = "disabled"; + }; + }; +}; From patchwork Sun Dec 2 20:23:51 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mesih Kilinc X-Patchwork-Id: 1006553 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="MC/uSZjZ"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 437KNt1H4tz9sCs for ; Mon, 3 Dec 2018 07:24:46 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726077AbeLBUYs (ORCPT ); Sun, 2 Dec 2018 15:24:48 -0500 Received: from mail-wr1-f65.google.com ([209.85.221.65]:39850 "EHLO mail-wr1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725984AbeLBUYr (ORCPT ); Sun, 2 Dec 2018 15:24:47 -0500 Received: by mail-wr1-f65.google.com with SMTP id t27so10059781wra.6; Sun, 02 Dec 2018 12:24:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=tcTFGjWSUDe1a3RfhkbtIH7npTtVBEiYc3Nl7JTQJUI=; b=MC/uSZjZ7eRKFBAaN+33BMvkhzE5N4F60Bef5bi+CJ5Q1axeeIyMA3ePctjjb85bn7 F4HsvD6byMCepTr4LZnKSn5aHDIBNMPiwcuDFLkfCD3ZYAbgeE3B/2e3BPxZ2s0/ZaNj b/nvK3E78p+TprpDBPTZezlOeyZOriS6rSsFtJhO8deE/ROvxUGAj3dyGsvMhXawMzTS o7xupjwn9Ylhv4I732X22oeNg/WcwNK5q7KfJ65bcJbkcVujiMZ46t5/BGuoSD3MfPWy EPGtMC6iuQZvHGwKuV+mfnG0radtQrJXtJdhEzryiN3kEnlP6yuBxEBpS/UhOhIVvcxs pw+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=tcTFGjWSUDe1a3RfhkbtIH7npTtVBEiYc3Nl7JTQJUI=; b=LX15osXIo7xjpmVCF+IJIXacdaE3aN/U8/yfD+U68x0wM0njmR2NIUo41+NoOZ0dVB I1+PYDsaFps64d7IRvxY4OW0+srairCOjS0vdf9VC7xVKMULrdJDxVqfQb3lKUkav3nM GIxvU7hcfoxYNyIQxsodtJ/PzpR/BFDCRjjkOtqnDhZYjTn9mEIo4Cg1Ixgf6Vn73bfc EyrDYFUcmfN0pTcT1NKIoMalNEwIfFWlgcLzhei2k1422tlg5RECLUNvS+dwJ93f3NqT y+xwgZf00vTD1k1U2g9ypOEaVJuh4Tfkn6tx767vL0F2ryPdd1QqzFVRcWbUPAxkEVpK rd6g== X-Gm-Message-State: AA+aEWYH4S2bjtlep9f9RAMS8h2SXG6DLDCeVYAv+e4jtZE9s/PeR8Hv MP0BfkVZWVIz1N7BERL0Y3UvX3ZpGX8= X-Google-Smtp-Source: AFSGD/XCOkDZxjraQA52Ty23Cet8GSvlWVOKBCI002RoLX4C/iyPpbDhESnWACNj/xn6/Cr0FWnHGg== X-Received: by 2002:a5d:4acb:: with SMTP id y11mr11447772wrs.281.1543782280631; Sun, 02 Dec 2018 12:24:40 -0800 (PST) Received: from ThinkPad.home ([185.219.177.152]) by smtp.gmail.com with ESMTPSA id l3sm14451510wma.44.2018.12.02.12.24.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 02 Dec 2018 12:24:40 -0800 (PST) From: Mesih Kilinc To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com Cc: Mesih Kilinc , Maxime Ripard , Chen-Yu Tsai , Russell King , Daniel Lezcano , Marc Zyngier , Linus Walleij , Icenowy Zheng , Rob Herring , Julian Calaby Subject: [PATCH v6 17/17] ARM: suniv: f1c100s: add device tree for Lichee Pi Nano Date: Sun, 2 Dec 2018 23:23:51 +0300 Message-Id: <125b26f154ad1373179d67fcde30df056e883ac8.1543781680.git.mesihkilinc@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Lichee Pi Nano is a F1C100s board by Lichee Pi. Add initial device tree for it. Signed-off-by: Mesih Kilinc --- arch/arm/boot/dts/Makefile | 2 ++ arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts | 26 +++++++++++++++++++++++ 2 files changed, 28 insertions(+) create mode 100644 arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index b0e966d..2b96a5b 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1066,6 +1066,8 @@ dtb-$(CONFIG_MACH_SUN8I) += \ dtb-$(CONFIG_MACH_SUN9I) += \ sun9i-a80-optimus.dtb \ sun9i-a80-cubieboard4.dtb +dtb-$(CONFIG_MACH_SUNIV) += \ + suniv-f1c100s-licheepi-nano.dtb dtb-$(CONFIG_ARCH_TANGO) += \ tango4-vantage-1172.dtb dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \ diff --git a/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts b/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts new file mode 100644 index 0000000..a1154e6 --- /dev/null +++ b/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR X11) +/* + * Copyright 2018 Icenowy Zheng + */ + +/dts-v1/; +#include "suniv-f1c100s.dtsi" + +/ { + model = "Lichee Pi Nano"; + compatible = "licheepi,licheepi-nano", "allwinner,suniv-f1c100s"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pe_pins>; + status = "okay"; +};