From patchwork Tue Nov 27 07:42:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Icenowy Zheng X-Patchwork-Id: 1003653 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=aosc.io Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 433wkb3fQXz9s3l for ; Tue, 27 Nov 2018 18:43:19 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728920AbeK0SkR (ORCPT ); Tue, 27 Nov 2018 13:40:17 -0500 Received: from hermes.aosc.io ([199.195.250.187]:37320 "EHLO hermes.aosc.io" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728267AbeK0SkR (ORCPT ); Tue, 27 Nov 2018 13:40:17 -0500 Received: from localhost (localhost [127.0.0.1]) (Authenticated sender: icenowy@aosc.io) by hermes.aosc.io (Postfix) with ESMTPSA id 7212A11E6FA; Tue, 27 Nov 2018 07:43:13 +0000 (UTC) From: Icenowy Zheng To: Jernej Skrabec , Chen-Yu Tsai , Maxime Ripard , David Airlie , Rob Herring , Mark Rutland Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Icenowy Zheng Subject: [PATCH 1/2] dt-bindings: gpu: add bus clock for Mali Midgard GPUs Date: Tue, 27 Nov 2018 15:42:48 +0800 Message-Id: <20181127074249.15204-1-icenowy@aosc.io> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Some SoCs adds a bus clock gate to the Mali Midgard GPU. Add the binding for the bus clock. Signed-off-by: Icenowy Zheng --- Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt index 18a2cde2e5f3..02f870cd60e6 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt +++ b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt @@ -31,6 +31,12 @@ Optional properties: - clocks : Phandle to clock for the Mali Midgard device. +- clock-names : Specify the names of the clocks specified in clocks + when multiple clocks are present. + * bus: bus clock for the GPU + * core: clock driving the GPU itself (When only one clock is present, + assume it's this clock.) + - mali-supply : Phandle to regulator for the Mali device. Refer to Documentation/devicetree/bindings/regulator/regulator.txt for details. From patchwork Tue Nov 27 07:42:49 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Icenowy Zheng X-Patchwork-Id: 1003654 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=aosc.io Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 433wkp4Rdxz9s3Z for ; Tue, 27 Nov 2018 18:43:30 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729198AbeK0Sk2 (ORCPT ); Tue, 27 Nov 2018 13:40:28 -0500 Received: from hermes.aosc.io ([199.195.250.187]:37346 "EHLO hermes.aosc.io" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729143AbeK0Sk2 (ORCPT ); Tue, 27 Nov 2018 13:40:28 -0500 Received: from localhost (localhost [127.0.0.1]) (Authenticated sender: icenowy@aosc.io) by hermes.aosc.io (Postfix) with ESMTPSA id 02DA611E7EF; Tue, 27 Nov 2018 07:43:24 +0000 (UTC) From: Icenowy Zheng To: Jernej Skrabec , Chen-Yu Tsai , Maxime Ripard , David Airlie , Rob Herring , Mark Rutland Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Icenowy Zheng Subject: [PATCH 2/2] dt-bindings: gpu: add Allwinner H6 Mali Midgard binding Date: Tue, 27 Nov 2018 15:42:49 +0800 Message-Id: <20181127074249.15204-2-icenowy@aosc.io> In-Reply-To: <20181127074249.15204-1-icenowy@aosc.io> References: <20181127074249.15204-1-icenowy@aosc.io> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Allwinner H6 SoC uses a Mali T720 GPU, which is one of the GPUs in the Midgard GPU product line. Add binding for the H6 Mali Midgard GPU. Signed-off-by: Icenowy Zheng --- .../devicetree/bindings/gpu/arm,mali-midgard.txt | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt index 02f870cd60e6..c897dd7be48f 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt +++ b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt @@ -18,6 +18,7 @@ Required properties: + "amlogic,meson-gxm-mali" + "rockchip,rk3288-mali" + "rockchip,rk3399-mali" + + "allwinner,sun50i-h6-mali" - reg : Physical base address of the device and length of the register area. @@ -44,6 +45,18 @@ Optional properties: for details. +Vendor-specific bindings +------------------------ + +The Mali GPU is integrated very differently from one SoC to +another. In order to accomodate those differences, you have the option +to specify one more vendor-specific compatible, among: + + - allwinner,sun50i-h6-mali + Required properties: + * resets: phandle to the reset line for the GPU + + Example for a Mali-T760: gpu@ffa30000 {