From patchwork Mon Nov 26 20:53:33 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Uros Bizjak X-Patchwork-Id: 1003485 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-490919-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="ULZIptZ5"; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="p8vYGHLa"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 433fKK51Qlz9s3C for ; Tue, 27 Nov 2018 07:53:57 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:content-type; q= dns; s=default; b=Bu56o53z5IqnEpClsDJ2PL2buCNh09oiV5cO9qDAxuu8B9 UCjcp8HONV+x4daRKsAGGw2RLImRb/Mt5T3lNpLMtSxpcQ/myecTr882r6yxIg4J /QPIY2dgacBWxVs4Wfq9cWjZRt4zbuvM9gfMEt/lsoL/+KcWvOp4c9hagS7OM= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:content-type; s= default; bh=voNE6zBL3EDQ3Wy6o5whiMZYKec=; b=ULZIptZ5FxmsOk42oEm7 vJ3UughTvXW47jSLPgbXVEk79zSlQHLQx9nkavDKMB63FOW8qIo4mSl67zI9+1kn HrdKw21dja8kDHivaLZDN46zsZArnKhXStrhhXmG/tdm63o4oe5QTcsbRbwcpG33 hXqp5WYpnvJMR+BrBSXFz0o= Received: (qmail 103601 invoked by alias); 26 Nov 2018 20:53:50 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 103584 invoked by uid 89); 26 Nov 2018 20:53:50 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-8.3 required=5.0 tests=BAYES_00, FREEMAIL_FROM, GIT_PATCH_2, GIT_PATCH_3, KAM_ASCII_DIVIDERS, RCVD_IN_DNSWL_NONE, SPF_PASS, UNWANTED_LANGUAGE_BODY autolearn=ham version=3.3.2 spammy= X-HELO: mail-it1-f170.google.com Received: from mail-it1-f170.google.com (HELO mail-it1-f170.google.com) (209.85.166.170) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 26 Nov 2018 20:53:48 +0000 Received: by mail-it1-f170.google.com with SMTP id o19so30584018itg.5 for ; Mon, 26 Nov 2018 12:53:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:from:date:message-id:subject:to; bh=PBtd/Kd7uF/vB2Js/4QmpHfV0ioUmjQwojrdk1fP7Tg=; b=p8vYGHLaC9j+cS3tvVe1WX7/k8hR+bJR2CHh4K9y0U+VqkafQHCu1zlATySYaxR+2u vWaQOAsoAjpSZEAzTpJj4nIByggoNuNUXODLTaSW6DoBknRGxATSbbzDN21s5+P8CZCW +L8tUuAo8jbr+2DQibN9Hhr4V6hwnkKFVrNDiR/E4u/Wgm4gLtFhhijGZz61ZqkBCY1B QLNOIEAV+ipsO8tdNuw2Aq1vx4ANgtPbbSL3YdXmO5zJ3jp/q+QdwKYUAHPFYg2w8t85 IuWLQ95XJSwp1Q9HFiKq+yOJx2P+qR+6e8KT97b6ELGD65W7gCFIdtPwIJ/9pc2ab28v oicQ== MIME-Version: 1.0 From: Uros Bizjak Date: Mon, 26 Nov 2018 21:53:33 +0100 Message-ID: Subject: [PATCH, i386]: Fix PR 88178, ICE in dbx_reg_number, at dwarf2out.c To: "gcc-patches@gcc.gnu.org" 2018-11-26 Uros Bizjak PR target/88178 * config/i386/i386.c (dbx_register_map): Use IGNORED_DWARF_REGNUM for registers for which no debug information can be generated. Use INVALID_REGNUM for non-existent registers. (dbx64_register_map): Ditto. (svr4_dbx_register_map): Ditto. testsuite/ChangeLog: 2018-11-26 Uros Bizjak PR target/88178 * gcc.target/pr88178.c: New test. Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}. Committed to mainline SVN. Uros. Index: config/i386/i386.c =================================================================== --- config/i386/i386.c (revision 266467) +++ config/i386/i386.c (working copy) @@ -271,16 +271,31 @@ int const dbx_register_map[FIRST_PSEUDO_REGISTER] = { - 0, 2, 1, 3, 6, 7, 4, 5, /* general regs */ - 12, 13, 14, 15, 16, 17, 18, 19, /* fp regs */ - -1, -1, -1, -1, /* arg, flags, fpsr, frame */ - 21, 22, 23, 24, 25, 26, 27, 28, /* SSE */ - 29, 30, 31, 32, 33, 34, 35, 36, /* MMX */ - -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */ - -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */ - -1, -1, -1, -1, -1, -1, -1, -1, /* AVX-512 registers 16-23*/ - -1, -1, -1, -1, -1, -1, -1, -1, /* AVX-512 registers 24-31*/ - 93, 94, 95, 96, 97, 98, 99, 100 /* Mask registers */ + /* general regs */ + 0, 2, 1, 3, 6, 7, 4, 5, + /* fp regs */ + 12, 13, 14, 15, 16, 17, 18, 19, + /* arg, flags, fpsr, frame */ + IGNORED_DWARF_REGNUM, IGNORED_DWARF_REGNUM, + IGNORED_DWARF_REGNUM, IGNORED_DWARF_REGNUM, + /* SSE */ + 21, 22, 23, 24, 25, 26, 27, 28, + /* MMX */ + 29, 30, 31, 32, 33, 34, 35, 36, + /* extended integer registers */ + INVALID_REGNUM, INVALID_REGNUM, INVALID_REGNUM, INVALID_REGNUM, + INVALID_REGNUM, INVALID_REGNUM, INVALID_REGNUM, INVALID_REGNUM, + /* extended sse registers */ + INVALID_REGNUM, INVALID_REGNUM, INVALID_REGNUM, INVALID_REGNUM, + INVALID_REGNUM, INVALID_REGNUM, INVALID_REGNUM, INVALID_REGNUM, + /* AVX-512 registers 16-23 */ + INVALID_REGNUM, INVALID_REGNUM, INVALID_REGNUM, INVALID_REGNUM, + INVALID_REGNUM, INVALID_REGNUM, INVALID_REGNUM, INVALID_REGNUM, + /* AVX-512 registers 24-31 */ + INVALID_REGNUM, INVALID_REGNUM, INVALID_REGNUM, INVALID_REGNUM, + INVALID_REGNUM, INVALID_REGNUM, INVALID_REGNUM, INVALID_REGNUM, + /* Mask registers */ + 93, 94, 95, 96, 97, 98, 99, 100 }; /* The "default" register map used in 64bit mode. */ @@ -287,16 +302,27 @@ int const dbx64_register_map[FIRST_PSEUDO_REGISTER] = { - 0, 1, 2, 3, 4, 5, 6, 7, /* general regs */ - 33, 34, 35, 36, 37, 38, 39, 40, /* fp regs */ - -1, -1, -1, -1, /* arg, flags, fpsr, frame */ - 17, 18, 19, 20, 21, 22, 23, 24, /* SSE */ - 41, 42, 43, 44, 45, 46, 47, 48, /* MMX */ - 8,9,10,11,12,13,14,15, /* extended integer registers */ - 25, 26, 27, 28, 29, 30, 31, 32, /* extended SSE registers */ - 67, 68, 69, 70, 71, 72, 73, 74, /* AVX-512 registers 16-23 */ - 75, 76, 77, 78, 79, 80, 81, 82, /* AVX-512 registers 24-31 */ - 118, 119, 120, 121, 122, 123, 124, 125 /* Mask registers */ + /* general regs */ + 0, 1, 2, 3, 4, 5, 6, 7, + /* fp regs */ + 33, 34, 35, 36, 37, 38, 39, 40, + /* arg, flags, fpsr, frame */ + IGNORED_DWARF_REGNUM, IGNORED_DWARF_REGNUM, + IGNORED_DWARF_REGNUM, IGNORED_DWARF_REGNUM, + /* SSE */ + 17, 18, 19, 20, 21, 22, 23, 24, + /* MMX */ + 41, 42, 43, 44, 45, 46, 47, 48, + /* extended integer registers */ + 8, 9, 10, 11, 12, 13, 14, 15, + /* extended SSE registers */ + 25, 26, 27, 28, 29, 30, 31, 32, + /* AVX-512 registers 16-23 */ + 67, 68, 69, 70, 71, 72, 73, 74, + /* AVX-512 registers 24-31 */ + 75, 76, 77, 78, 79, 80, 81, 82, + /* Mask registers */ + 118, 119, 120, 121, 122, 123, 124, 125 }; /* Define the register numbers to be used in Dwarf debugging information. @@ -355,16 +381,31 @@ */ int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER] = { - 0, 2, 1, 3, 6, 7, 5, 4, /* general regs */ - 11, 12, 13, 14, 15, 16, 17, 18, /* fp regs */ - -1, 9, -1, -1, /* arg, flags, fpsr, frame */ - 21, 22, 23, 24, 25, 26, 27, 28, /* SSE registers */ - 29, 30, 31, 32, 33, 34, 35, 36, /* MMX registers */ - -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */ - -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */ - -1, -1, -1, -1, -1, -1, -1, -1, /* AVX-512 registers 16-23*/ - -1, -1, -1, -1, -1, -1, -1, -1, /* AVX-512 registers 24-31*/ - 93, 94, 95, 96, 97, 98, 99, 100 /* Mask registers */ + /* general regs */ + 0, 2, 1, 3, 6, 7, 5, 4, + /* fp regs */ + 11, 12, 13, 14, 15, 16, 17, 18, + /* arg, flags, fpsr, frame */ + IGNORED_DWARF_REGNUM, 9, + IGNORED_DWARF_REGNUM, IGNORED_DWARF_REGNUM, + /* SSE registers */ + 21, 22, 23, 24, 25, 26, 27, 28, + /* MMX registers */ + 29, 30, 31, 32, 33, 34, 35, 36, + /* extended integer registers */ + INVALID_REGNUM, INVALID_REGNUM, INVALID_REGNUM, INVALID_REGNUM, + INVALID_REGNUM, INVALID_REGNUM, INVALID_REGNUM, INVALID_REGNUM, + /* extended sse registers */ + INVALID_REGNUM, INVALID_REGNUM, INVALID_REGNUM, INVALID_REGNUM, + INVALID_REGNUM, INVALID_REGNUM, INVALID_REGNUM, INVALID_REGNUM, + /* AVX-512 registers 16-23 */ + INVALID_REGNUM, INVALID_REGNUM, INVALID_REGNUM, INVALID_REGNUM, + INVALID_REGNUM, INVALID_REGNUM, INVALID_REGNUM, INVALID_REGNUM, + /* AVX-512 registers 24-31 */ + INVALID_REGNUM, INVALID_REGNUM, INVALID_REGNUM, INVALID_REGNUM, + INVALID_REGNUM, INVALID_REGNUM, INVALID_REGNUM, INVALID_REGNUM, + /* Mask registers */ + 93, 94, 95, 96, 97, 98, 99, 100 }; /* Define parameter passing and return registers. */ Index: testsuite/gcc.target/i386/pr88178.c =================================================================== --- testsuite/gcc.target/i386/pr88178.c (nonexistent) +++ testsuite/gcc.target/i386/pr88178.c (working copy) @@ -0,0 +1,8 @@ +/* PR target/88178 */ +/* { dg-do compile } */ +/* { dg-options "-g" } */ + +void foo (void) +{ + register int r19 asm ("19"); +}