From patchwork Wed Nov 21 10:41:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chee, Tien Fong" X-Patchwork-Id: 1001053 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=intel.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 430K0t1cLYz9s4s for ; Wed, 21 Nov 2018 21:43:10 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id D456BC222B3; Wed, 21 Nov 2018 10:42:30 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 865F9C22278; Wed, 21 Nov 2018 10:42:10 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 1FB45C22277; Wed, 21 Nov 2018 10:42:08 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by lists.denx.de (Postfix) with ESMTPS id 5DA06C22089 for ; Wed, 21 Nov 2018 10:42:01 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 21 Nov 2018 02:42:00 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,260,1539673200"; d="scan'208";a="93769120" Received: from pg-iccf0296.altera.com ([10.104.2.37]) by orsmga008.jf.intel.com with ESMTP; 21 Nov 2018 02:41:58 -0800 From: tien.fong.chee@intel.com To: u-boot@lists.denx.de Date: Wed, 21 Nov 2018 18:41:40 +0800 Message-Id: <1542796908-7947-2-git-send-email-tien.fong.chee@intel.com> X-Mailer: git-send-email 1.7.7.4 In-Reply-To: <1542796908-7947-1-git-send-email-tien.fong.chee@intel.com> References: <1542796908-7947-1-git-send-email-tien.fong.chee@intel.com> Cc: Marek Vasut , Tien Fong Chee , Ching Liang See , Westergteen Dalon Subject: [U-Boot] [PATCH 1/9] ARM: socfpga: Description on FPGA bitstream type and file name for Arria 10 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Tien Fong Chee This patch adds description on properties about file name used for both peripheral bitstream and core bitstream. Signed-off-by: Tien Fong Chee --- .../fpga/altera-socfpga-a10-fpga-mgr.txt | 6 ++++++ 1 files changed, 6 insertions(+), 0 deletions(-) diff --git a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt index 2fd8e7a..010322a 100644 --- a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt +++ b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt @@ -7,6 +7,10 @@ Required properties: - The second index is for writing FPGA configuration data. - resets : Phandle and reset specifier for the device's reset. - clocks : Clocks used by the device. +- altr,bitstream_periph : File name for FPGA peripheral raw binary which is used + to initialize FPGA IOs, PLL, IO48 and DDR. +- altr,bitstream_core : File name for core raw binary which contains FPGA design + which is used to program FPGA CRAM and ERAM. Example: @@ -16,4 +20,6 @@ Example: 0xffcfe400 0x20>; clocks = <&l4_mp_clk>; resets = <&rst FPGAMGR_RESET>; + altr,bitstream_periph = "ghrd_10as066n2.periph.rbf.mkimage"; + altr,bitstream_core = "ghrd_10as066n2.core.rbf.mkimage"; }; From patchwork Wed Nov 21 10:41:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chee, Tien Fong" X-Patchwork-Id: 1001055 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=intel.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 430K1269V4z9s8F for ; Wed, 21 Nov 2018 21:43:18 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id BCECAC2227E; Wed, 21 Nov 2018 10:42:50 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 594CBC2227F; Wed, 21 Nov 2018 10:42:13 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 8BA65C22254; Wed, 21 Nov 2018 10:42:12 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by lists.denx.de (Postfix) with ESMTPS id D08F1C22266 for ; Wed, 21 Nov 2018 10:42:04 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 21 Nov 2018 02:42:03 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,260,1539673200"; d="scan'208";a="93769132" Received: from pg-iccf0296.altera.com ([10.104.2.37]) by orsmga008.jf.intel.com with ESMTP; 21 Nov 2018 02:42:00 -0800 From: tien.fong.chee@intel.com To: u-boot@lists.denx.de Date: Wed, 21 Nov 2018 18:41:41 +0800 Message-Id: <1542796908-7947-3-git-send-email-tien.fong.chee@intel.com> X-Mailer: git-send-email 1.7.7.4 In-Reply-To: <1542796908-7947-1-git-send-email-tien.fong.chee@intel.com> References: <1542796908-7947-1-git-send-email-tien.fong.chee@intel.com> Cc: Marek Vasut , Tien Fong Chee , Ching Liang See , Westergteen Dalon Subject: [U-Boot] [PATCH 2/9] ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Tien Fong Chee Add FPGA driver to support program FPGA with FPGA bitstream loading from filesystem. The driver are designed based on generic firmware loader framework. The driver can handle FPGA program operation from loading FPGA bitstream in flash to memory and then to program FPGA. Signed-off-by: Tien Fong Chee --- arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 18 + .../include/mach/fpga_manager_arria10.h | 30 ++- configs/socfpga_arria10_defconfig | 9 + drivers/fpga/Kconfig | 9 + drivers/fpga/socfpga_arria10.c | 417 +++++++++++++++++++- 5 files changed, 471 insertions(+), 12 deletions(-) diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts index 998d811..f4764d4 100644 --- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts +++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts @@ -18,6 +18,24 @@ /dts-v1/; #include "socfpga_arria10_socdk.dtsi" +/ { + chosen { + firmware-loader = &fs_loader0; + }; + + fs_loader0: fs-loader@0 { + u-boot,dm-pre-reloc; + compatible = "u-boot,fs-loader"; + phandlepart = <&mmc 1>; + }; +}; + +&fpga_mgr { + u-boot,dm-pre-reloc; + altr,bitstream_periph = "ghrd_10as066n2.periph.rbf.mkimage"; + altr,bitstream_core = "ghrd_10as066n2.core.rbf.mkimage"; +}; + &mmc { u-boot,dm-pre-reloc; status = "okay"; diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h index 09d13f6..b48bc76 100644 --- a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h +++ b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h @@ -1,9 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2017 Intel Corporation + * Copyright (C) 2017-2018 Intel Corporation * All rights reserved. */ +#include +#include + #ifndef _FPGA_MANAGER_ARRIA10_H_ #define _FPGA_MANAGER_ARRIA10_H_ @@ -51,6 +54,8 @@ #define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK BIT(24) #define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB 16 +#define PERIPH_RBF 0 +#define CORE_RBF 1 #ifndef __ASSEMBLY__ struct socfpga_fpga_manager { @@ -88,12 +93,33 @@ struct socfpga_fpga_manager { u32 imgcfg_fifo_status; }; +enum rbf_type {unknown, periph_section, core_section}; +enum rbf_security {invalid, unencrypted, encrypted}; + +struct rbf_info { + enum rbf_type section; + enum rbf_security security; +}; + +struct fpga_loadfs_info { + fpga_fs_info *fpga_fsinfo; + u32 remaining; + u32 offset; + u32 datacrc; + struct rbf_info rbfinfo; + struct image_header header; +}; + /* Functions */ int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size); int fpgamgr_program_finish(void); int is_fpgamgr_user_mode(void); int fpgamgr_wait_early_user_mode(void); - +int is_fpgamgr_early_user_mode(void); +const char *get_fpga_filename(const void *fdt, int *len, u32 core); +void get_rbf_image_info(struct rbf_info *rbf, u16 *buffer); +int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void *buf, size_t bsize, + u32 offset); #endif /* __ASSEMBLY__ */ #endif /* _FPGA_MANAGER_ARRIA10_H_ */ diff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig index 6ebda81..f88910c 100644 --- a/configs/socfpga_arria10_defconfig +++ b/configs/socfpga_arria10_defconfig @@ -27,8 +27,17 @@ CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0" # CONFIG_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc" CONFIG_ENV_IS_IN_MMC=y +CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_DM_MMC=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_FS_SUPPORT=y +CONFIG_SPL_EXT_SUPPORT=y +CONFIG_SPL_FAT_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 +CONFIG_FS_LOADER=y CONFIG_FPGA_SOCFPGA=y CONFIG_DM_GPIO=y CONFIG_DWAPB_GPIO=y diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index 50e9019..06a8204 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -21,6 +21,15 @@ config FPGA_SOCFPGA This provides common functionality for Gen5 and Arria10 devices. +config CHECK_FPGA_DATA_CRC + bool "Enable CRC cheking on Arria10 FPGA bistream" + depends on FPGA_SOCFPGA + help + Say Y here to enable the CRC checking on Arria 10 FPGA bitstream + + This provides CRC checking to ensure integrated of Arria 10 FPGA + bitstream is programmed into FPGA. + config FPGA_CYCLON2 bool "Enable Altera FPGA driver for Cyclone II" depends on FPGA_ALTERA diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c index 114dd91..d9ad237 100644 --- a/drivers/fpga/socfpga_arria10.c +++ b/drivers/fpga/socfpga_arria10.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2017 Intel Corporation + * Copyright (C) 2017-2018 Intel Corporation */ #include @@ -10,8 +10,10 @@ #include #include #include +#include #include #include +#include #include #include @@ -21,6 +23,10 @@ #define COMPRESSION_OFFSET 229 #define FPGA_TIMEOUT_MSEC 1000 /* timeout in ms */ #define FPGA_TIMEOUT_CNT 0x1000000 +#define RBF_UNENCRYPTED 0xa65c +#define RBF_ENCRYPTED 0xa65d +#define ARRIA10RBF_PERIPH 0x0001 +#define ARRIA10RBF_CORE 0x8001 static const struct socfpga_fpga_manager *fpga_manager_base = (void *)SOCFPGA_FPGAMGRREGS_ADDRESS; @@ -64,7 +70,7 @@ static int wait_for_user_mode(void) 1, FPGA_TIMEOUT_MSEC, false); } -static int is_fpgamgr_early_user_mode(void) +int is_fpgamgr_early_user_mode(void) { return (readl(&fpga_manager_base->imgcfg_stat) & ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK) != 0; @@ -447,13 +453,393 @@ int fpgamgr_program_finish(void) return 0; } +const char *get_fpga_filename(const void *fdt, int *len, u32 core) +{ + const char *fpga_filename = NULL; + const char *cell; + int nodeoffset; + + nodeoffset = fdtdec_next_compatible(fdt, 0, + COMPAT_ALTERA_SOCFPGA_FPGA0); + if (nodeoffset >= 0) { + if (core) { + cell = fdt_getprop(fdt, + nodeoffset, + "altr,bitstream_core", + len); + } else { + cell = fdt_getprop(fdt, nodeoffset, + "altr,bitstream_periph", len); + } + + if (cell) + fpga_filename = cell; + } + + return fpga_filename; +} + +void get_rbf_image_info(struct rbf_info *rbf, u16 *buffer) +{ + /* + * Magic ID starting at: + * -> 1st dword[15:0] in periph.rbf + * -> 2nd dword[15:0] in core.rbf + * Note: dword == 32 bits + */ + u32 word_reading_max = 2; + u32 i; + + for (i = 0; i < word_reading_max; i++) { + if (*(buffer + i) == RBF_UNENCRYPTED) { + rbf->security = unencrypted; + } else if (*(buffer + i) == RBF_ENCRYPTED) { + rbf->security = encrypted; + } else if (*(buffer + i + 1) == RBF_UNENCRYPTED) { + rbf->security = unencrypted; + } else if (*(buffer + i + 1) == RBF_ENCRYPTED) { + rbf->security = encrypted; + } else { + rbf->security = invalid; + continue; + } + + /* PERIPH RBF(buffer + i + 1), CORE RBF(buffer + i + 2) */ + if (*(buffer + i + 1) == ARRIA10RBF_PERIPH) { + rbf->section = periph_section; + break; + } else if (*(buffer + i + 1) == ARRIA10RBF_CORE) { + rbf->section = core_section; + break; + } else if (*(buffer + i + 2) == ARRIA10RBF_PERIPH) { + rbf->section = periph_section; + break; + } else if (*(buffer + i + 2) == ARRIA10RBF_CORE) { + rbf->section = core_section; + break; + } + + rbf->section = unknown; + break; + + WATCHDOG_RESET(); + } +} + +static struct firmware *fw; + +int first_loading_rbf_to_buffer(struct device_platdata *plat, + struct fpga_loadfs_info *fpga_loadfs, + u32 *buffer, u32 *buffer_bsize) +{ + u32 *buffer_p_after_header = NULL; + u32 buffersz_after_header = 0; + u32 totalsz_header_rbf = 0; + u32 *buffer_p = (u32 *)*buffer; + struct image_header *header = &(fpga_loadfs->header); + size_t buffer_size = *buffer_bsize; + int ret = 0; + + /* Load mkimage header into buffer */ + ret = request_firmware_into_buf(plat, + fpga_loadfs->fpga_fsinfo->filename, + header, + sizeof(struct image_header), + fpga_loadfs->offset, + &fw); + if (ret < 0) { + debug("FPGA: Failed to read RBF mkimage header from flash.\n"); + return -ENOENT; + } + + WATCHDOG_RESET(); + + if (!image_check_magic(header)) { + debug("FPGA: Bad Magic Number.\n"); + return -EBADF; + } + + if (!image_check_hcrc(header)) { + debug("FPGA: Bad Header Checksum.\n"); + return -EPERM; + } + + /* Getting RBF data size from mkimage header */ + fpga_loadfs->remaining = image_get_data_size(header); + + /* Calculate total size of both RBF with mkimage header */ + totalsz_header_rbf = fpga_loadfs->remaining + + sizeof(struct image_header); + + /* + * Determine buffer size vs RBF size, and calculating number of + * chunk by chunk transfer is required due to smaller buffer size + * compare to RBF + */ + if (totalsz_header_rbf > buffer_size) { + /* Calculate size of RBF in the buffer */ + buffersz_after_header = + buffer_size - sizeof(struct image_header); + fpga_loadfs->remaining -= buffersz_after_header; + } else { + /* Loading whole RBF into buffer */ + buffer_size = totalsz_header_rbf; + /* Calculate size of RBF in the buffer */ + buffersz_after_header = + buffer_size - sizeof(struct image_header); + fpga_loadfs->remaining = 0; + } + + /* Loading mkimage header and RBFinto buffer */ + ret = request_firmware_into_buf(plat, + fpga_loadfs->fpga_fsinfo->filename, + buffer_p, + buffer_size, + fpga_loadfs->offset, + &fw); + if (ret < 0) { + debug("FPGA: Failed to read RBF mkimage header and RBF from "); + debug("flash.\n"); + return -ENOENT; + } + + /* + * Getting pointer of RBF starting address where it's + * right after mkimage header + */ + buffer_p_after_header = + (u32 *)((u_char *)buffer_p + sizeof(struct image_header)); + + /* Update next reading RBF offset */ + fpga_loadfs->offset += buffer_size; + + /* Getting info about RBF types */ + get_rbf_image_info(&fpga_loadfs->rbfinfo, (u16 *)buffer_p_after_header); + + /* + * Update the starting addr of RBF to init FPGA & programming RBF + * into FPGA + */ + *buffer = (u32)buffer_p_after_header; + + /* Update the size of RBF to be programmed into FPGA */ + *buffer_bsize = buffersz_after_header; + +#ifdef CONFIG_CHECK_FPGA_DATA_CRC + fpga_loadfs->datacrc = crc32(fpga_loadfs->datacrc, + (u_char *)buffer_p_after_header, + buffersz_after_header); +#endif + +if (fpga_loadfs->remaining == 0) { +#ifdef CONFIG_CHECK_FPGA_DATA_CRC + if (fpga_loadfs->datacrc != image_get_dcrc(&(fpga_loadfs->header))) { + debug("FPGA: Bad Data Checksum.\n"); + return -EPERM; + } +#endif +} + return 0; +} + +int subsequent_loading_rbf_to_buffer(struct device_platdata *plat, + struct fpga_loadfs_info *fpga_loadfs, + u32 *buffer, u32 *buffer_bsize) +{ + int ret = 0; + u32 *buffer_p = (u32 *)*buffer; + + /* Read the RBF chunk by chunk. */ + if (fpga_loadfs->remaining > *buffer_bsize) { + fpga_loadfs->remaining -= *buffer_bsize; + } else { + *buffer_bsize = fpga_loadfs->remaining; + fpga_loadfs->remaining = 0; + } + + ret = request_firmware_into_buf(plat, + fpga_loadfs->fpga_fsinfo->filename, + buffer_p, + *buffer_bsize, + fpga_loadfs->offset, + &fw); + if (ret < 0) { + debug("FPGA: Failed to read RBF from flash.\n"); + return -ENOENT; + } + +#ifdef CONFIG_CHECK_FPGA_DATA_CRC + fpga_loadfs->datacrc = crc32(fpga_loadfs->datacrc, + (unsigned char *)buffer_p, + *buffer_bsize); +#endif + +if (fpga_loadfs->remaining == 0) { +#ifdef CONFIG_CHECK_FPGA_DATA_CRC + if (fpga_loadfs->datacrc != image_get_dcrc(&(fpga_loadfs->header))) { + debug("FPGA: Bad Data Checksum.\n"); + return -EPERM; + } +#endif +} + + /* Update next reading RBF offset */ + fpga_loadfs->offset += *buffer_bsize; + + return 0; +} + +int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void *buf, size_t bsize, + u32 offset) +{ + struct fpga_loadfs_info fpga_loadfs; + int status = 0; + int ret = 0; + u32 buffer = (u32) buf; + u32 buffer_ori = (u32) buf; + size_t buffer_sizebytes = bsize; + size_t buffer_sizebytes_ori = bsize; + size_t total_sizeof_mkimage = sizeof(struct image_header); + struct udevice *dev; + + ret = uclass_get_device(UCLASS_FS_FIRMWARE_LOADER, 0, &dev); + if (ret) + return ret; + + memset(&fpga_loadfs, 0, sizeof(fpga_loadfs)); + + WATCHDOG_RESET(); + + fpga_loadfs.fpga_fsinfo = fpga_fsinfo; + fpga_loadfs.offset = offset; + + printf("Start to program FPGA ...\n"); + + /* + * Note: Both buffer and buffer_sizebytes values can be altered by + * function below. + */ + ret = first_loading_rbf_to_buffer(dev->platdata, &fpga_loadfs, &buffer, + &buffer_sizebytes); + if (ret) { + release_firmware(fw); + fw = NULL; + return ret; + } + + if ((fpga_loadfs.rbfinfo.section == core_section) && + !(is_fpgamgr_early_user_mode() && !is_fpgamgr_user_mode())) { + debug("FPGA : FPGA must be in Early Release mode to program "); + debug("core.\n"); + release_firmware(fw); + fw = NULL; + return 0; + } + + /* Disable all signals from hps peripheral controller to fpga */ + writel(0, &system_manager_base->fpgaintf_en_global); + + /* Disable all axi bridges (hps2fpga, lwhps2fpga & fpga2hps) */ + socfpga_bridges_reset(); + + if (fpga_loadfs.rbfinfo.section == periph_section) { + /* Initialize the FPGA Manager */ + status = fpgamgr_program_init((u32 *)buffer, buffer_sizebytes); + if (status) { + debug("FPGA: Init with periph rbf failed.\n"); + release_firmware(fw); + fw = NULL; + return -EPERM; + } + } + + WATCHDOG_RESET(); + + /* Transfer RBF to FPGA Manager */ + fpgamgr_program_write((void *)buffer, buffer_sizebytes); + + total_sizeof_mkimage += buffer_sizebytes; + + WATCHDOG_RESET(); + + while (fpga_loadfs.remaining) { + ret = subsequent_loading_rbf_to_buffer(dev->platdata, + &fpga_loadfs, + &buffer_ori, + &buffer_sizebytes_ori); + + if (ret) { + release_firmware(fw); + fw = NULL; + return ret; + } + + /* Transfer data to FPGA Manager */ + fpgamgr_program_write((void *)buffer_ori, + buffer_sizebytes_ori); + + total_sizeof_mkimage += buffer_sizebytes_ori; + + WATCHDOG_RESET(); + } + + if (fpga_loadfs.rbfinfo.section == periph_section) { + if (fpgamgr_wait_early_user_mode() != -ETIMEDOUT) { + config_pins(gd->fdt_blob, "shared"); + puts("FPGA: Early Release Succeeded.\n"); + } else { + debug("FPGA: Failed to see Early Release.\n"); + release_firmware(fw); + fw = NULL; + return -EIO; + } + + /* For monolithic bitstream */ + if (is_fpgamgr_user_mode()) { + /* Ensure the FPGA entering config done */ + status = fpgamgr_program_finish(); + if (status) { + release_firmware(fw); + fw = NULL; + return status; + } + + config_pins(gd->fdt_blob, "fpga"); + puts("FPGA: Enter user mode.\n"); + } + } else if (fpga_loadfs.rbfinfo.section == core_section) { + /* Ensure the FPGA entering config done */ + status = fpgamgr_program_finish(); + if (status) { + release_firmware(fw); + fw = NULL; + return status; + } + + config_pins(gd->fdt_blob, "fpga"); + puts("FPGA: Enter user mode.\n"); + } else { + debug("Config Error: Unsupported FGPA RBF type.\n"); + release_firmware(fw); + fw = NULL; + return -ENOEXEC; + } + + release_firmware(fw); + fw = NULL; + + return (int)total_sizeof_mkimage; +} + /* - * FPGA Manager to program the FPGA. This is the interface used by FPGA driver. - * Return 0 for sucess, non-zero for error. + * This function is used to load the core RBF from the OCRAM where the location + * of the image is defined in the load property in the FIT image source file + * (.its) */ int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size) { - int status; + unsigned long status; + struct rbf_info rbfinfo; /* disable all signals from hps peripheral controller to fpga */ writel(0, &system_manager_base->fpgaintf_en_global); @@ -461,13 +847,24 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size) /* disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */ socfpga_bridges_reset(); - /* Initialize the FPGA Manager */ - status = fpgamgr_program_init((u32 *)rbf_data, rbf_size); - if (status) - return status; + /* Getting info about RBF types */ + get_rbf_image_info(&rbfinfo, (u16 *)rbf_data); + + if (rbfinfo.section == periph_section) { + /* Initialize the FPGA Manager */ + status = fpgamgr_program_init((u32 *)rbf_data, rbf_size); + if (status) + return status; + } /* Write the RBF data to FPGA Manager */ fpgamgr_program_write(rbf_data, rbf_size); - return fpgamgr_program_finish(); + status = fpgamgr_program_finish(); + if (status) { + config_pins(gd->fdt_blob, "fpga"); + puts("FPGA: Enter user mode.\n"); + } + + return status; } From patchwork Wed Nov 21 10:41:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chee, Tien Fong" X-Patchwork-Id: 1001059 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=intel.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 430K5T3lDZz9s0t for ; Wed, 21 Nov 2018 21:47:09 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 14F6CC22285; Wed, 21 Nov 2018 10:43:27 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 24BE7C2227A; Wed, 21 Nov 2018 10:42:16 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 41AA8C22274; Wed, 21 Nov 2018 10:42:12 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by lists.denx.de (Postfix) with ESMTPS id 08FB8C22267 for ; Wed, 21 Nov 2018 10:42:05 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 21 Nov 2018 02:42:05 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,260,1539673200"; d="scan'208";a="93769144" Received: from pg-iccf0296.altera.com ([10.104.2.37]) by orsmga008.jf.intel.com with ESMTP; 21 Nov 2018 02:42:03 -0800 From: tien.fong.chee@intel.com To: u-boot@lists.denx.de Date: Wed, 21 Nov 2018 18:41:42 +0800 Message-Id: <1542796908-7947-4-git-send-email-tien.fong.chee@intel.com> X-Mailer: git-send-email 1.7.7.4 In-Reply-To: <1542796908-7947-1-git-send-email-tien.fong.chee@intel.com> References: <1542796908-7947-1-git-send-email-tien.fong.chee@intel.com> Cc: Marek Vasut , Tien Fong Chee , Ching Liang See , Westergteen Dalon Subject: [U-Boot] [PATCH 3/9] spl : socfpga: Implement fpga bitstream loading with socfpga loadfs X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Tien Fong Chee Add support for loading FPGA bitstream to get DDR up running before U-Boot is loaded into DDR. Boot device initialization, generic firmware loader and SPL FAT support are required for this whole mechanism to work. Signed-off-by: Tien Fong Chee --- arch/arm/mach-socfpga/spl_a10.c | 49 ++++++++++++++++++++++++++++++++++++++- common/spl/spl_mmc.c | 2 +- include/mmc.h | 1 + 3 files changed, 50 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c index 3ea64f7..67a4fac 100644 --- a/arch/arm/mach-socfpga/spl_a10.c +++ b/arch/arm/mach-socfpga/spl_a10.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2012 Altera Corporation + * Copyright (C) 2012-2018 Altera Corporation */ #include @@ -23,6 +23,10 @@ #include #include #include +#include +#include + +#define RBF 0 DECLARE_GLOBAL_DATA_PTR; @@ -73,6 +77,49 @@ void spl_board_init(void) WATCHDOG_RESET(); arch_early_init_r(); + + /* If the full FPGA is already loaded, ie.from EPCQ, config fpga pins */ + if (is_fpgamgr_user_mode()) { + config_pins(gd->fdt_blob, "shared"); + config_pins(gd->fdt_blob, "fpga"); + } else if (!is_fpgamgr_early_user_mode()) { + /* Program IOSSM(early IO release) or full FPGA */ + fpga_fs_info fpga_fsinfo; + char buf[16 * 1024] __aligned(ARCH_DMA_MINALIGN); + struct spl_boot_device bootdev; + int len = 0; + + bootdev.boot_device = spl_boot_device(); + + /* Init MMC driver before reading FPGA bitstream from flash */ + if (bootdev.boot_device == BOOT_DEVICE_MMC1) { + struct mmc *mmc = NULL; + int err = 0; + + err = spl_mmc_find_device(&mmc, bootdev.boot_device); + if (err) + return; + + err = mmc_init(mmc); + + if (err) { + debug("spl: mmc init failed with error: %d\n", + err); + + return; + } + } + + fpga_fsinfo.filename = (char *)get_fpga_filename(gd->fdt_blob, + &len, + RBF); + + socfpga_loadfs(&fpga_fsinfo, buf, sizeof(buf), 0); + } + + /* If the IOSSM/full FPGA is already loaded, start DDR */ + if (is_fpgamgr_early_user_mode() || is_fpgamgr_user_mode()) + ddr_calibration_sequence(); } void board_init_f(ulong dummy) diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c index 4d55dcc..b85e146 100644 --- a/common/spl/spl_mmc.c +++ b/common/spl/spl_mmc.c @@ -111,7 +111,7 @@ static int spl_mmc_get_device_index(u32 boot_device) return -ENODEV; } -static int spl_mmc_find_device(struct mmc **mmcp, u32 boot_device) +int spl_mmc_find_device(struct mmc **mmcp, u32 boot_device) { #if CONFIG_IS_ENABLED(DM_MMC) struct udevice *dev; diff --git a/include/mmc.h b/include/mmc.h index 95548e9..de92909 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -829,6 +829,7 @@ int board_mmc_init(bd_t *bis); int cpu_mmc_init(bd_t *bis); int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr); int mmc_get_env_dev(void); +int spl_mmc_find_device(struct mmc **mmcp, u32 boot_device); /* Set block count limit because of 16 bit register limit on some hardware*/ #ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT From patchwork Wed Nov 21 10:41:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chee, Tien Fong" X-Patchwork-Id: 1001056 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=intel.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 430K4D3R78z9s4s for ; Wed, 21 Nov 2018 21:46:01 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id A09FCC22275; Wed, 21 Nov 2018 10:43:44 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id F30D5C2228F; Wed, 21 Nov 2018 10:42:17 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id D3683C2228F; Wed, 21 Nov 2018 10:42:12 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by lists.denx.de (Postfix) with ESMTPS id 179E9C22268 for ; Wed, 21 Nov 2018 10:42:07 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 21 Nov 2018 02:42:07 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,260,1539673200"; d="scan'208";a="93769154" Received: from pg-iccf0296.altera.com ([10.104.2.37]) by orsmga008.jf.intel.com with ESMTP; 21 Nov 2018 02:42:05 -0800 From: tien.fong.chee@intel.com To: u-boot@lists.denx.de Date: Wed, 21 Nov 2018 18:41:43 +0800 Message-Id: <1542796908-7947-5-git-send-email-tien.fong.chee@intel.com> X-Mailer: git-send-email 1.7.7.4 In-Reply-To: <1542796908-7947-1-git-send-email-tien.fong.chee@intel.com> References: <1542796908-7947-1-git-send-email-tien.fong.chee@intel.com> Cc: Marek Vasut , Tien Fong Chee , Ching Liang See , Westergteen Dalon Subject: [U-Boot] [PATCH 4/9] ARM: socfpga: Bundle U-Boot fitImage into SFP on Arria10 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Tien Fong Chee Bundle U-Boot fitImage containing U-Boot and FPGA bitstream into the u-boot-with-spl.sfp on Arria10. This lets U-Boot operate in a very similar fashion to Gen5, where the U-Boot binary got loaded by the SPL from a uImage concatenated at the end of the SPL SFP image. On Gen10, the U-Boot is in fitImage which contains the FPGA bitstream as well. In this case, the SPL can load the FPGA bitstream first and load the U-Boot afterward in the same manner. This is nonetheless a stopgap measure until there is a proper firmware loader in U-Boot. Signed-off-by: Marek Vasut Signed-off-by: Tien Fong Chee --- Makefile | 9 +++++++-- include/configs/socfpga_common.h | 4 ++++ 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index a55915d..4ecc19d 100644 --- a/Makefile +++ b/Makefile @@ -1212,9 +1212,14 @@ ifneq ($(CONFIG_ARCH_SOCFPGA),) quiet_cmd_socboot = SOCBOOT $@ cmd_socboot = cat spl/u-boot-spl.sfp spl/u-boot-spl.sfp \ spl/u-boot-spl.sfp spl/u-boot-spl.sfp \ - u-boot.img > $@ || rm -f $@ + $2 > $@ || rm -f $@ +ifdef CONFIG_TARGET_SOCFPGA_ARRIA10 +u-boot-with-spl.sfp: spl/u-boot-spl.sfp u-boot.itb FORCE + $(call if_changed,socboot,u-boot.itb) +else u-boot-with-spl.sfp: spl/u-boot-spl.sfp u-boot.img FORCE - $(call if_changed,socboot) + $(call if_changed,socboot,u-boot.img) +endif endif ifeq ($(CONFIG_MPC85xx)$(CONFIG_OF_SEPARATE),yy) diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index bd8f5c8..ffdc6eb 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -268,7 +268,11 @@ unsigned int cm_get_qspi_controller_clk_hz(void); /* SPL SDMMC boot support */ #ifdef CONFIG_SPL_MMC_SUPPORT #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) +#if CONFIG_SPL_FIT +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.itb" +#else #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img" +#endif #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #endif #else From patchwork Wed Nov 21 10:41:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chee, Tien Fong" X-Patchwork-Id: 1001057 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=intel.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 430K4f5CCTz9s0t for ; Wed, 21 Nov 2018 21:46:26 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 5064BC2228D; Wed, 21 Nov 2018 10:44:17 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 42D7AC22294; Wed, 21 Nov 2018 10:42:28 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 9405BC22267; Wed, 21 Nov 2018 10:42:14 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by lists.denx.de (Postfix) with ESMTPS id 5EC2DC22281 for ; Wed, 21 Nov 2018 10:42:10 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 21 Nov 2018 02:42:10 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,260,1539673200"; d="scan'208";a="93769173" Received: from pg-iccf0296.altera.com ([10.104.2.37]) by orsmga008.jf.intel.com with ESMTP; 21 Nov 2018 02:42:07 -0800 From: tien.fong.chee@intel.com To: u-boot@lists.denx.de Date: Wed, 21 Nov 2018 18:41:44 +0800 Message-Id: <1542796908-7947-6-git-send-email-tien.fong.chee@intel.com> X-Mailer: git-send-email 1.7.7.4 In-Reply-To: <1542796908-7947-1-git-send-email-tien.fong.chee@intel.com> References: <1542796908-7947-1-git-send-email-tien.fong.chee@intel.com> Cc: Marek Vasut , Tien Fong Chee , Ching Liang See , Westergteen Dalon Subject: [U-Boot] [PATCH 5/9] ARM: socfpga: Add SPL fitImage config match X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Tien Fong Chee Add empty SPL fitImage configuration match. This can be extended if there is ever need to support multiple boards with single SFP image. Signed-off-by: Marek Vasut --- arch/arm/mach-socfpga/spl_a10.c | 10 ++++++++++ 1 files changed, 10 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c index 67a4fac..2baeba6 100644 --- a/arch/arm/mach-socfpga/spl_a10.c +++ b/arch/arm/mach-socfpga/spl_a10.c @@ -148,3 +148,13 @@ void board_init_f(ulong dummy) config_dedicated_pins(gd->fdt_blob); WATCHDOG_RESET(); } + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif From patchwork Wed Nov 21 10:41:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chee, Tien Fong" X-Patchwork-Id: 1001061 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=intel.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 430K6M2l57z9s4s for ; Wed, 21 Nov 2018 21:47:55 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id E7130C22281; Wed, 21 Nov 2018 10:44:00 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id BFE55C222A0; Wed, 21 Nov 2018 10:42:25 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id B7C25C22277; Wed, 21 Nov 2018 10:42:16 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by lists.denx.de (Postfix) with ESMTPS id 9EA60C22277 for ; Wed, 21 Nov 2018 10:42:12 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 21 Nov 2018 02:42:12 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,260,1539673200"; d="scan'208";a="93769191" Received: from pg-iccf0296.altera.com ([10.104.2.37]) by orsmga008.jf.intel.com with ESMTP; 21 Nov 2018 02:42:10 -0800 From: tien.fong.chee@intel.com To: u-boot@lists.denx.de Date: Wed, 21 Nov 2018 18:41:45 +0800 Message-Id: <1542796908-7947-7-git-send-email-tien.fong.chee@intel.com> X-Mailer: git-send-email 1.7.7.4 In-Reply-To: <1542796908-7947-1-git-send-email-tien.fong.chee@intel.com> References: <1542796908-7947-1-git-send-email-tien.fong.chee@intel.com> Cc: Marek Vasut , Tien Fong Chee , Ching Liang See , Westergteen Dalon Subject: [U-Boot] [PATCH 6/9] ARM: socfpga: Set default DTB address on A10 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Tien Fong Chee Set default DT blob address on A10 SoCDK, since this SoC uses OF separate configuration. The 0xf0000 address is just below the text base and still leaves enough room for the DT to grow. Signed-off-by: Marek Vasut Signed-off-by: Tien Fong Chee --- arch/arm/mach-socfpga/board.c | 8 ++++++++ 1 files changed, 8 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c index 7c8c05c..436a8a8 100644 --- a/arch/arm/mach-socfpga/board.c +++ b/arch/arm/mach-socfpga/board.c @@ -86,3 +86,11 @@ int g_dnl_board_usb_cable_connected(void) return 1; } #endif + +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10) && \ +!defined(CONFIG_SPL_BUILD) && defined(CONFIG_OF_SEPARATE) +void *board_fdt_blob_setup(void) +{ + return (void *)0xf00000; +} +#endif From patchwork Wed Nov 21 10:41:46 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chee, Tien Fong" X-Patchwork-Id: 1001068 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=intel.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 430KB94s0Vz9s0t for ; Wed, 21 Nov 2018 21:51:13 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 6AA0AC22265; Wed, 21 Nov 2018 10:45:08 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id AE43CC222B6; Wed, 21 Nov 2018 10:42:53 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 41351C222A3; Wed, 21 Nov 2018 10:42:19 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by lists.denx.de (Postfix) with ESMTPS id E10CBC22288 for ; Wed, 21 Nov 2018 10:42:14 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 21 Nov 2018 02:42:14 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,260,1539673200"; d="scan'208";a="93769197" Received: from pg-iccf0296.altera.com ([10.104.2.37]) by orsmga008.jf.intel.com with ESMTP; 21 Nov 2018 02:42:12 -0800 From: tien.fong.chee@intel.com To: u-boot@lists.denx.de Date: Wed, 21 Nov 2018 18:41:46 +0800 Message-Id: <1542796908-7947-8-git-send-email-tien.fong.chee@intel.com> X-Mailer: git-send-email 1.7.7.4 In-Reply-To: <1542796908-7947-1-git-send-email-tien.fong.chee@intel.com> References: <1542796908-7947-1-git-send-email-tien.fong.chee@intel.com> Cc: Marek Vasut , Tien Fong Chee , Ching Liang See , Westergteen Dalon Subject: [U-Boot] [PATCH 7/9] ARM: socfpga: Use custom header target buffer in SPL X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Tien Fong Chee Allocate buffers from OCRAM heap for the image headers in SPL on Arria10, since DRAM is not available at that point. This allows U-Boot to load the fitImage header, parse it, extract the FPGA bitstream section from it, program the FPGA and make DRAM available. Signed-off-by: Marek Vasut --- arch/arm/mach-socfpga/spl_a10.c | 11 +++++++++++ 1 files changed, 11 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c index 2baeba6..7fe9790 100644 --- a/arch/arm/mach-socfpga/spl_a10.c +++ b/arch/arm/mach-socfpga/spl_a10.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -157,4 +158,14 @@ int board_fit_config_name_match(const char *name) return 0; } + +struct image_header *spl_get_load_buffer(int offset, size_t size) +{ + struct image_header *mem = memalign(4, size); + + if (!mem) + hang(); + + return mem; +} #endif From patchwork Wed Nov 21 10:41:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chee, Tien Fong" X-Patchwork-Id: 1001069 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=intel.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 430KCw01wnz9s0t for ; Wed, 21 Nov 2018 21:52:43 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id AEF17C22265; Wed, 21 Nov 2018 10:44:35 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 77A72C22286; Wed, 21 Nov 2018 10:42:45 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id B573DC221E7; Wed, 21 Nov 2018 10:42:21 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by lists.denx.de (Postfix) with ESMTPS id 331C9C22266 for ; Wed, 21 Nov 2018 10:42:17 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 21 Nov 2018 02:42:16 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,260,1539673200"; d="scan'208";a="93769211" Received: from pg-iccf0296.altera.com ([10.104.2.37]) by orsmga008.jf.intel.com with ESMTP; 21 Nov 2018 02:42:14 -0800 From: tien.fong.chee@intel.com To: u-boot@lists.denx.de Date: Wed, 21 Nov 2018 18:41:47 +0800 Message-Id: <1542796908-7947-9-git-send-email-tien.fong.chee@intel.com> X-Mailer: git-send-email 1.7.7.4 In-Reply-To: <1542796908-7947-1-git-send-email-tien.fong.chee@intel.com> References: <1542796908-7947-1-git-send-email-tien.fong.chee@intel.com> Cc: Marek Vasut , Tien Fong Chee , Ching Liang See , Westergteen Dalon Subject: [U-Boot] [PATCH 8/9] ARM: socfpga: Add default fitImage for Arria10 SoCDK X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Tien Fong Chee Add default fitImage file bundling U-Boot and FPGA bitstream for Arria10. Signed-off-by: Marek Vasut Signed-off-by: Tien Fong Chee --- board/altera/arria10-socdk/fit_spl_fpga.its | 54 +++++++++++++++++++++++++++ 1 files changed, 54 insertions(+), 0 deletions(-) create mode 100644 board/altera/arria10-socdk/fit_spl_fpga.its diff --git a/board/altera/arria10-socdk/fit_spl_fpga.its b/board/altera/arria10-socdk/fit_spl_fpga.its new file mode 100644 index 0000000..7782740 --- /dev/null +++ b/board/altera/arria10-socdk/fit_spl_fpga.its @@ -0,0 +1,54 @@ +/* + * The fitImage source for Arria 10 SoCDK loading FPGA bitstream and U-Boot + * + * Copyright (C) 2018 Marek Vasut + * + * SPDX-License-Identifier: GPL-2.0+ X11 + */ + +/dts-v1/; + +/ { + description = "FIT image with U-Boot proper and FPGA bitstream"; + #address-cells = <1>; + + images { + uboot { + description = "U-Boot (32-bit)"; + data = /incbin/("../../../u-boot-nodtb.bin"); + type = "standalone"; + os = "U-Boot"; + arch = "arm"; + compression = "none"; + load = <0x01000040>; + entry = <0x01000040>; + }; + + fdt { + description = "Arria10 SoCDK flat device-tree"; + data = /incbin/("../../../u-boot.dtb"); + type = "flat_dt"; + arch = "arm"; + compression = "none"; + load = <0x00f00000>; + }; + + fpga { + description = "FPGA bitstream"; + data = /incbin/("../../../ghrd_10as066n2.core.rbf"); + type = "fpga"; + compression = "none"; + load = <0x1000>; + }; + }; + + configurations { + default = "conf"; + conf { + description = "Altera Arria10 SoCDK"; + loadables = "uboot"; + fdt = "fdt"; + fpga = "fpga"; + }; + }; +}; From patchwork Wed Nov 21 10:41:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chee, Tien Fong" X-Patchwork-Id: 1001058 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=intel.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 430K4m2fJfz9s0t for ; Wed, 21 Nov 2018 21:46:32 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 1B508C2229B; Wed, 21 Nov 2018 10:44:52 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.8 required=5.0 tests=UPPERCASE_50_75 autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id B6345C222A9; Wed, 21 Nov 2018 10:42:47 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id DCC90C22266; Wed, 21 Nov 2018 10:42:23 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by lists.denx.de (Postfix) with ESMTPS id 73421C22296 for ; Wed, 21 Nov 2018 10:42:19 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 21 Nov 2018 02:42:19 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,260,1539673200"; d="scan'208";a="93769226" Received: from pg-iccf0296.altera.com ([10.104.2.37]) by orsmga008.jf.intel.com with ESMTP; 21 Nov 2018 02:42:17 -0800 From: tien.fong.chee@intel.com To: u-boot@lists.denx.de Date: Wed, 21 Nov 2018 18:41:48 +0800 Message-Id: <1542796908-7947-10-git-send-email-tien.fong.chee@intel.com> X-Mailer: git-send-email 1.7.7.4 In-Reply-To: <1542796908-7947-1-git-send-email-tien.fong.chee@intel.com> References: <1542796908-7947-1-git-send-email-tien.fong.chee@intel.com> Cc: Marek Vasut , Tien Fong Chee , Ching Liang See , Westergteen Dalon Subject: [U-Boot] [PATCH 9/9] ARM: socfpga: Synchronize the configuration for A10 SoCDK X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Tien Fong Chee Update the default configuration file to enable the necessary functionality the get the kit working. That includes fitImage loading in SPL, SPL SD/MMC support, USB, I2C. Signed-off-by: Marek Vasut Signed-off-by: Tien Fong Chee --- configs/socfpga_arria10_defconfig | 42 +++++++++++++++++++++++++++++++----- 1 files changed, 36 insertions(+), 6 deletions(-) diff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig index f88910c..86f078b 100644 --- a/configs/socfpga_arria10_defconfig +++ b/configs/socfpga_arria10_defconfig @@ -1,35 +1,48 @@ CONFIG_ARM=y CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_TEXT_BASE=0x01000040 -CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SYS_MALLOC_F_LEN=0x8000 CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y CONFIG_SPL=y CONFIG_IDENT_STRING="socfpga_arria10" CONFIG_DISTRO_DEFAULTS=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_SOURCE="board/altera/arria10-socdk/fit_spl_fpga.its" CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200" # CONFIG_USE_BOOTCOMMAND is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y CONFIG_DEFAULT_FDT_FILE="socfpga_arria10_socdk_sdmmc.dtb" +CONFIG_VERSION_VARIABLE=y CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800 CONFIG_SPL_FPGA_SUPPORT=y -CONFIG_SPL_SPI_LOAD=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4_WRITE=y CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0" -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_ISO_PARTITION is not set -# CONFIG_EFI_PARTITION is not set +CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names" CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc" CONFIG_ENV_IS_IN_MMC=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_DFU_MMC=y CONFIG_SPL_DM_MMC=y CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_FS_SUPPORT=y @@ -41,13 +54,30 @@ CONFIG_FS_LOADER=y CONFIG_FPGA_SOCFPGA=y CONFIG_DM_GPIO=y CONFIG_DWAPB_GPIO=y +CONFIG_SYS_I2C_DW=y CONFIG_DM_MMC=y CONFIG_MTD_DEVICE=y +CONFIG_MTD_PARTITIONS=y +CONFIG_MMC_DW=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y +CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_TIMER=y CONFIG_SPL_TIMER=y CONFIG_DESIGNWARE_APB_TIMER=y -CONFIG_USE_TINY_PRINTF=y +CONFIG_DESIGNWARE_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_DWC2=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USB_GADGET_DOWNLOAD=y