From patchwork Tue Nov 20 09:25:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Z.Q. Hou" X-Patchwork-Id: 1000326 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=nxp.com header.i=@nxp.com header.b="SdnxsQ1l"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42zgL80rlQz9s8F for ; Tue, 20 Nov 2018 20:25:52 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727522AbeKTTx6 (ORCPT ); Tue, 20 Nov 2018 14:53:58 -0500 Received: from mail-eopbgr10082.outbound.protection.outlook.com ([40.107.1.82]:5555 "EHLO EUR02-HE1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727008AbeKTTx6 (ORCPT ); Tue, 20 Nov 2018 14:53:58 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=OLTcpwun8vauetbG2lYFQO++8wm+IH1mKhk6LkHhDms=; b=SdnxsQ1lhwpmu4IiG8N2gw/jLmkdKUQpfwrN4IzGdI3+RZh8SBe3YortjHajm9OvJqF0/d7JkNY10PbfzXZEwwzpZW3Q8/1VNeYqmRT521aour2VpB8wA0gmNYjudomDdo5OO5UCjWCfphkxeDoKxLOeIBjVsApinKOGfFlDgFU= Received: from AM6PR04MB5781.eurprd04.prod.outlook.com (20.179.2.80) by AM6PR04MB4871.eurprd04.prod.outlook.com (20.177.33.146) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1339.25; Tue, 20 Nov 2018 09:25:41 +0000 Received: from AM6PR04MB5781.eurprd04.prod.outlook.com ([fe80::29b5:b3ed:3854:cf1c]) by AM6PR04MB5781.eurprd04.prod.outlook.com ([fe80::29b5:b3ed:3854:cf1c%4]) with mapi id 15.20.1339.026; Tue, 20 Nov 2018 09:25:41 +0000 From: "Z.q. Hou" To: "linux-pci@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "bhelgaas@google.com" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "l.subrahmanya@mobiveil.co.in" , "shawnguo@kernel.org" , Leo Li , "lorenzo.pieralisi@arm.com" , "catalin.marinas@arm.com" , "will.deacon@arm.com" CC: Mingkai Hu , "M.h. Lian" , Xiaowei Bao , "Z.q. Hou" Subject: [PATCHv2 01/25] PCI: mobiveil: uniform the register accessors Thread-Topic: [PATCHv2 01/25] PCI: mobiveil: uniform the register accessors Thread-Index: AQHUgLMBpsVARsSl+E+erRC6ybL4qw== Date: Tue, 20 Nov 2018 09:25:41 +0000 Message-ID: <20181120092615.11680-2-Zhiqiang.Hou@nxp.com> References: <20181120092615.11680-1-Zhiqiang.Hou@nxp.com> In-Reply-To: <20181120092615.11680-1-Zhiqiang.Hou@nxp.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: HK2PR03CA0050.apcprd03.prod.outlook.com (2603:1096:202:17::20) To AM6PR04MB5781.eurprd04.prod.outlook.com (2603:10a6:20b:aa::16) authentication-results: spf=none (sender IP is ) smtp.mailfrom=zhiqiang.hou@nxp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [119.31.174.73] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; AM6PR04MB4871; 6:XBRqgQc/59AcU//uDVu5nHKWDcz3e5KDsLoZ2ZN+Z+PMnMEC05s78wd+0XKP3ebY2zwFDGCkFW4B15+pz0dj0UScvoBE7gxHMiA4Fjl910/++keJanopBeKHf9ru/pzD77M0zsgqQNv38jhHThEICU/AQ2is7UsAmz9yXXky5/nAlRbO1J3JnmaNLuUuSqHF2YoQfcUGfyBRaMnfjz/oI0BdLv4Sie0p4JzjFs2ZRzzC8Blh1s/rKlxZI8jZ0BWeoAi028BDoxyQcYG6OZUwGocSo6oNjlaKv31fm9/9vxcViSt9DilCoDzHLuOJKh7rgBS+xL+BsHL2Cxkf1VOoYWI/bxcAZBoh6i4TKSAsZsjqu7abVAcGoOHowlOT44doGLr91c7FUmoNBtVeAZJVE4FZXqPkXjhfiALbNo93vl0S74B+lhYceCw7nGdKuJD0XltYF1GByOjzBarqbs2a/g==; 5:B5/kboEOdtvZ+wpeTTGBk7WiDfb5FwuD9InKVA7dJlvNImOpQded96HuYLi9+YG0JeOvyL1XaJMetYlr0FIqSRBM+5mPuyDHhSYAzuiLHMNZndzT+JN0CJefJZPd2efMfcCl4E+izh8BsEUEuclc1EfFkrjkhJWoFOZVqP5afI8=; 7:U48JJAssWLr59jUZh8r5pjEOK7FWtABeZpftOQPG6Zk0JrZdmXxP0TnspHSdWVHJ5ECiS50/A28u173MJy7rwNlPCy3x3M7dGPJX+xegnpUXhWeCVZLccKD5HcsrcmwD0IWJIHCK8y0rG9NcE1AmUw== x-ms-office365-filtering-correlation-id: 29a67e3d-ee6d-42fa-24d6-08d64eca2406 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390098)(7020095)(4652040)(8989299)(5600074)(711020)(4618075)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7153060)(7193020); SRVR:AM6PR04MB4871; x-ms-traffictypediagnostic: AM6PR04MB4871: x-microsoft-antispam-prvs: x-ms-exchange-senderadcheck: 1 x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(8211001083)(6040522)(2401047)(5005006)(8121501046)(3231442)(944501410)(52105112)(3002001)(10201501046)(93006095)(93001095)(6055026)(148016)(149066)(150057)(6041310)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123558120)(20161123564045)(20161123560045)(20161123562045)(201708071742011)(7699051)(76991095); SRVR:AM6PR04MB4871; BCL:0; PCL:0; RULEID:; SRVR:AM6PR04MB4871; x-forefront-prvs: 08626BE3A5 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(39860400002)(346002)(376002)(396003)(366004)(136003)(199004)(189003)(2501003)(97736004)(6486002)(256004)(6506007)(68736007)(386003)(14444005)(86362001)(575784001)(2906002)(7416002)(2201001)(478600001)(106356001)(71190400001)(71200400001)(305945005)(105586002)(6436002)(66066001)(8676002)(8936002)(7736002)(81156014)(81166006)(4326008)(102836004)(2900100001)(316002)(14454004)(53936002)(6512007)(186003)(26005)(25786009)(11346002)(446003)(2616005)(36756003)(99286004)(476003)(3846002)(110136005)(1076002)(52116002)(5660300001)(6116002)(76176011)(486006)(54906003)(921003)(1121003); DIR:OUT; SFP:1101; SCL:1; SRVR:AM6PR04MB4871; H:AM6PR04MB5781.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: ZVZmwjpVRXp9oxmNFg6BqLP+4oLObTKh4Kl5MxJJ9bw6tNpHYTEhTXsCHzvXq6GCbyAITKjCsibk6cgO+sMUakoN+CjDfNt5VzXvHA53+tdMnUTVdJs4b/ucDNKsqRsAn74ZPGayRDlTpxTR/bTYBSpHR8hXsBdSTFQm/ut+VqHRnfJrEnV59ke+WW3l+aaKf/VRYDgRusHUPdMuiEMOw1madwUzf5NgICfdQqtzsvJ4QbaHbzyXUeHylT4PLzvM1OI63nm7aFOgnIyG02fR8Pzw0OSyTVvDbIVcwPY32yQ7MaGwmfPj1S8uSqp/cWvy1Rs2tjsCzG+zncU3TxMFx9rGvX6guR2Cxqvg8qebtV4= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 29a67e3d-ee6d-42fa-24d6-08d64eca2406 X-MS-Exchange-CrossTenant-originalarrivaltime: 20 Nov 2018 09:25:41.6746 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR04MB4871 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Hou Zhiqiang It's confused that R/W some registers by csr_readl()/csr_writel(), while others by read_paged_register()/write_paged_register(). Actually the low 3KB of 4KB PCIe configure space can be accessed directly and high 1KB is paging area. So this patch uniformed the register accessors to csr_readl() and csr_writel() by comparing the register offset with page access boundary 3KB in the accessor internal. Signed-off-by: Hou Zhiqiang reviewed-by: Minghuan Lian --- V2: - no change drivers/pci/controller/pcie-mobiveil.c | 179 +++++++++++++++++-------- 1 file changed, 124 insertions(+), 55 deletions(-) diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c index 77052a0712d0..d55c7e780c6e 100644 --- a/drivers/pci/controller/pcie-mobiveil.c +++ b/drivers/pci/controller/pcie-mobiveil.c @@ -47,7 +47,6 @@ #define PAGE_SEL_SHIFT 13 #define PAGE_SEL_MASK 0x3f #define PAGE_LO_MASK 0x3ff -#define PAGE_SEL_EN 0xc00 #define PAGE_SEL_OFFSET_SHIFT 10 #define PAB_AXI_PIO_CTRL 0x0840 @@ -117,6 +116,12 @@ #define LINK_WAIT_MIN 90000 #define LINK_WAIT_MAX 100000 +#define PAGED_ADDR_BNDRY 0xc00 +#define OFFSET_TO_PAGE_ADDR(off) \ + ((off & PAGE_LO_MASK) | PAGED_ADDR_BNDRY) +#define OFFSET_TO_PAGE_IDX(off) \ + ((off >> PAGE_SEL_OFFSET_SHIFT) & PAGE_SEL_MASK) + struct mobiveil_msi { /* MSI information */ struct mutex lock; /* protect bitmap variable */ struct irq_domain *msi_domain; @@ -145,15 +150,119 @@ struct mobiveil_pcie { struct mobiveil_msi msi; }; -static inline void csr_writel(struct mobiveil_pcie *pcie, const u32 value, - const u32 reg) +/* + * mobiveil_pcie_sel_page - routine to access paged register + * + * Registers whose address greater than PAGED_ADDR_BNDRY (0xc00) are paged, + * for this scheme to work extracted higher 6 bits of the offset will be + * written to pg_sel field of PAB_CTRL register and rest of the lower 10 + * bits enabled with PAGED_ADDR_BNDRY are used as offset of the register. + */ +static void mobiveil_pcie_sel_page(struct mobiveil_pcie *pcie, u8 pg_idx) { - writel_relaxed(value, pcie->csr_axi_slave_base + reg); + u32 val; + + val = readl(pcie->csr_axi_slave_base + PAB_CTRL); + val &= ~(PAGE_SEL_MASK << PAGE_SEL_SHIFT); + val |= (pg_idx & PAGE_SEL_MASK) << PAGE_SEL_SHIFT; + + writel(val, pcie->csr_axi_slave_base + PAB_CTRL); } -static inline u32 csr_readl(struct mobiveil_pcie *pcie, const u32 reg) +static void *mobiveil_pcie_comp_addr(struct mobiveil_pcie *pcie, u32 off) { - return readl_relaxed(pcie->csr_axi_slave_base + reg); + if (off < PAGED_ADDR_BNDRY) { + /* For directly accessed registers, clear the pg_sel field */ + mobiveil_pcie_sel_page(pcie, 0); + return pcie->csr_axi_slave_base + off; + } + + mobiveil_pcie_sel_page(pcie, OFFSET_TO_PAGE_IDX(off)); + return pcie->csr_axi_slave_base + OFFSET_TO_PAGE_ADDR(off); +} + +static int mobiveil_pcie_read(void __iomem *addr, int size, u32 *val) +{ + if ((uintptr_t)addr & (size - 1)) { + *val = 0; + return PCIBIOS_BAD_REGISTER_NUMBER; + } + + switch (size) { + case 4: + *val = readl(addr); + break; + case 2: + *val = readw(addr); + break; + case 1: + *val = readb(addr); + break; + default: + *val = 0; + return PCIBIOS_BAD_REGISTER_NUMBER; + } + + return PCIBIOS_SUCCESSFUL; +} + +static int mobiveil_pcie_write(void __iomem *addr, int size, u32 val) +{ + if ((uintptr_t)addr & (size - 1)) + return PCIBIOS_BAD_REGISTER_NUMBER; + + switch (size) { + case 4: + writel(val, addr); + break; + case 2: + writew(val, addr); + break; + case 1: + writeb(val, addr); + break; + default: + return PCIBIOS_BAD_REGISTER_NUMBER; + } + + return PCIBIOS_SUCCESSFUL; +} + +static u32 csr_read(struct mobiveil_pcie *pcie, u32 off, size_t size) +{ + void *addr; + u32 val; + int ret; + + addr = mobiveil_pcie_comp_addr(pcie, off); + + ret = mobiveil_pcie_read(addr, size, &val); + if (ret) + dev_err(&pcie->pdev->dev, "read CSR address failed\n"); + + return val; +} + +static void csr_write(struct mobiveil_pcie *pcie, u32 val, u32 off, size_t size) +{ + void *addr; + int ret; + + addr = mobiveil_pcie_comp_addr(pcie, off); + + ret = mobiveil_pcie_write(addr, size, val); + if (ret) + dev_err(&pcie->pdev->dev, "write CSR address failed\n"); +} + +static u32 csr_readl(struct mobiveil_pcie *pcie, u32 off) +{ + return csr_read(pcie, off, 0x4); +} + +static void csr_writel(struct mobiveil_pcie *pcie, u32 val, u32 off) +{ + csr_write(pcie, val, off, 0x4); } static bool mobiveil_pcie_link_up(struct mobiveil_pcie *pcie) @@ -342,45 +451,6 @@ static int mobiveil_pcie_parse_dt(struct mobiveil_pcie *pcie) return 0; } -/* - * select_paged_register - routine to access paged register of root complex - * - * registers of RC are paged, for this scheme to work - * extracted higher 6 bits of the offset will be written to pg_sel - * field of PAB_CTRL register and rest of the lower 10 bits enabled with - * PAGE_SEL_EN are used as offset of the register. - */ -static void select_paged_register(struct mobiveil_pcie *pcie, u32 offset) -{ - int pab_ctrl_dw, pg_sel; - - /* clear pg_sel field */ - pab_ctrl_dw = csr_readl(pcie, PAB_CTRL); - pab_ctrl_dw = (pab_ctrl_dw & ~(PAGE_SEL_MASK << PAGE_SEL_SHIFT)); - - /* set pg_sel field */ - pg_sel = (offset >> PAGE_SEL_OFFSET_SHIFT) & PAGE_SEL_MASK; - pab_ctrl_dw |= ((pg_sel << PAGE_SEL_SHIFT)); - csr_writel(pcie, pab_ctrl_dw, PAB_CTRL); -} - -static void write_paged_register(struct mobiveil_pcie *pcie, - u32 val, u32 offset) -{ - u32 off = (offset & PAGE_LO_MASK) | PAGE_SEL_EN; - - select_paged_register(pcie, offset); - csr_writel(pcie, val, off); -} - -static u32 read_paged_register(struct mobiveil_pcie *pcie, u32 offset) -{ - u32 off = (offset & PAGE_LO_MASK) | PAGE_SEL_EN; - - select_paged_register(pcie, offset); - return csr_readl(pcie, off); -} - static void program_ib_windows(struct mobiveil_pcie *pcie, int win_num, int pci_addr, u32 type, u64 size) { @@ -397,19 +467,19 @@ static void program_ib_windows(struct mobiveil_pcie *pcie, int win_num, pio_ctrl_val = csr_readl(pcie, PAB_PEX_PIO_CTRL); csr_writel(pcie, pio_ctrl_val | (1 << PIO_ENABLE_SHIFT), PAB_PEX_PIO_CTRL); - amap_ctrl_dw = read_paged_register(pcie, PAB_PEX_AMAP_CTRL(win_num)); + amap_ctrl_dw = csr_readl(pcie, PAB_PEX_AMAP_CTRL(win_num)); amap_ctrl_dw = (amap_ctrl_dw | (type << AMAP_CTRL_TYPE_SHIFT)); amap_ctrl_dw = (amap_ctrl_dw | (1 << AMAP_CTRL_EN_SHIFT)); - write_paged_register(pcie, amap_ctrl_dw | lower_32_bits(size64), - PAB_PEX_AMAP_CTRL(win_num)); + csr_writel(pcie, amap_ctrl_dw | lower_32_bits(size64), + PAB_PEX_AMAP_CTRL(win_num)); - write_paged_register(pcie, upper_32_bits(size64), - PAB_EXT_PEX_AMAP_SIZEN(win_num)); + csr_writel(pcie, upper_32_bits(size64), + PAB_EXT_PEX_AMAP_SIZEN(win_num)); - write_paged_register(pcie, pci_addr, PAB_PEX_AMAP_AXI_WIN(win_num)); - write_paged_register(pcie, pci_addr, PAB_PEX_AMAP_PEX_WIN_L(win_num)); - write_paged_register(pcie, 0, PAB_PEX_AMAP_PEX_WIN_H(win_num)); + csr_writel(pcie, pci_addr, PAB_PEX_AMAP_AXI_WIN(win_num)); + csr_writel(pcie, pci_addr, PAB_PEX_AMAP_PEX_WIN_L(win_num)); + csr_writel(pcie, 0, PAB_PEX_AMAP_PEX_WIN_H(win_num)); } /* @@ -437,8 +507,7 @@ static void program_ob_windows(struct mobiveil_pcie *pcie, int win_num, csr_writel(pcie, 1 << WIN_ENABLE_SHIFT | type << WIN_TYPE_SHIFT | lower_32_bits(size64), PAB_AXI_AMAP_CTRL(win_num)); - write_paged_register(pcie, upper_32_bits(size64), - PAB_EXT_AXI_AMAP_SIZE(win_num)); + csr_writel(pcie, upper_32_bits(size64), PAB_EXT_AXI_AMAP_SIZE(win_num)); /* * program AXI window base with appropriate value in From patchwork Tue Nov 20 09:25:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Z.Q. Hou" X-Patchwork-Id: 1000356 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=nxp.com header.i=@nxp.com header.b="bO+o7pUP"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42zgPZ6CTJz9s1x for ; Tue, 20 Nov 2018 20:28:50 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727604AbeKTTyD (ORCPT ); Tue, 20 Nov 2018 14:54:03 -0500 Received: from mail-eopbgr10082.outbound.protection.outlook.com ([40.107.1.82]:5555 "EHLO EUR02-HE1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727641AbeKTTyD (ORCPT ); Tue, 20 Nov 2018 14:54:03 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=vlsI1ugQK9tvFngzXXcgSmBSEN0AF/2JN/zQYQwIkI0=; b=bO+o7pUPkB5Q7L4JbY3u3Sfqj8EXdgDo8ouKqvD1tKX0G0n6yvacAuq12AIVvQaF3AqqT0jN650OhINSLZQrq3gJxZW3qKrlyleiuOhxYavu8D7hVFoZrc0Suoy2Z1v2zSakyX+oMFH8icyS0iR3xcqJ1d2JkRVp3hKFxSEkSWc= Received: from AM6PR04MB5781.eurprd04.prod.outlook.com (20.179.2.80) by AM6PR04MB4871.eurprd04.prod.outlook.com (20.177.33.146) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1339.25; Tue, 20 Nov 2018 09:25:48 +0000 Received: from AM6PR04MB5781.eurprd04.prod.outlook.com ([fe80::29b5:b3ed:3854:cf1c]) by AM6PR04MB5781.eurprd04.prod.outlook.com ([fe80::29b5:b3ed:3854:cf1c%4]) with mapi id 15.20.1339.026; Tue, 20 Nov 2018 09:25:48 +0000 From: "Z.q. Hou" To: "linux-pci@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "bhelgaas@google.com" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "l.subrahmanya@mobiveil.co.in" , "shawnguo@kernel.org" , Leo Li , "lorenzo.pieralisi@arm.com" , "catalin.marinas@arm.com" , "will.deacon@arm.com" CC: Mingkai Hu , "M.h. Lian" , Xiaowei Bao , "Z.q. Hou" Subject: [PATCHv2 02/25] PCI: mobiveil: format the code without function change Thread-Topic: [PATCHv2 02/25] PCI: mobiveil: format the code without function change Thread-Index: AQHUgLMFvFzDg9q420mtQmEYYSsylg== Date: Tue, 20 Nov 2018 09:25:48 +0000 Message-ID: <20181120092615.11680-3-Zhiqiang.Hou@nxp.com> References: <20181120092615.11680-1-Zhiqiang.Hou@nxp.com> In-Reply-To: <20181120092615.11680-1-Zhiqiang.Hou@nxp.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: HK2PR03CA0050.apcprd03.prod.outlook.com (2603:1096:202:17::20) To AM6PR04MB5781.eurprd04.prod.outlook.com (2603:10a6:20b:aa::16) authentication-results: spf=none (sender IP is ) smtp.mailfrom=zhiqiang.hou@nxp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [119.31.174.73] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; AM6PR04MB4871; 6:f0EMlvW1oi3Mi89HuSNrxwptHTa0mtZM0UdgQ9GhwTUTLrVt6R1rCKNb2tIxo3bnYeZ6jP9hRcwETbZj//DIdAQIlRU6BkxO2ifLdorHWqZT62jGfzbr9dRiL/Xh2fY9jsWx8dfGot5tIxoZ5/spHI7ZhdiHKZ+89FjNYzgl2p0QPoz+RjQuYy9QBcaCvTwKg7wGtO4ONvKrPgOrIt13Bm2o42bFaGK8y5mUsCATNM7EQML/BOlwTJhrd4JWnSMvR0/j7mj6hxKHDjMyQ26ESZ+iLODm8syR8ZJJKuTmmBhSgFyqNPUhUA8jUypLG3ayWUZfnunjKU0yWvMmdiSicnjDRo9yRrC4XkcRftJb5Z/zpB/Uj3sQYqHPsKNFEuatqclMW0EtR05q+MI09tK1Omw6OStwogLAQobIpFhUJ6eDwMFexW/wWCrNT3wTf2BsEE26li/zu2U8w4ZVL6ZYPA==; 5:W+d8MYxM3CZLnIwFYQcf5/v876viIIUSP1lAkguOSaGawKQ41/kwuab1UbEc7Xwg61b2tWl0ucp9Yb+TDlued4+nUCPHfZH3aXYQbgu1DMurqyrvnhMe10jK9UfFpT/EXiVGkV3YTALL2ZAfOFhUeMqtMiKzrDqjC7+t0Btm4OE=; 7:ZGrriD/HoO9N34SbIwNqZe5FNnkA7vfikctOa2YybsWyKo9mg+p8JGnDSx29F1LW5ooSPzfo9D7a9o1fLe+svNYlfUvxSWf44eGgBafqamdt22e6Gg4zzdEfaurQOdtW4O5AKNoa+YolUja7DzEoEg== x-ms-office365-filtering-correlation-id: 53a6f05e-7460-4767-85ec-08d64eca27b1 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390098)(7020095)(4652040)(8989299)(5600074)(711020)(4618075)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7153060)(7193020); SRVR:AM6PR04MB4871; x-ms-traffictypediagnostic: AM6PR04MB4871: x-microsoft-antispam-prvs: x-ms-exchange-senderadcheck: 1 x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(8211001083)(6040522)(2401047)(5005006)(8121501046)(3231442)(944501410)(52105112)(3002001)(10201501046)(93006095)(93001095)(6055026)(148016)(149066)(150057)(6041310)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123558120)(20161123564045)(20161123560045)(20161123562045)(201708071742011)(7699051)(76991095); SRVR:AM6PR04MB4871; BCL:0; PCL:0; RULEID:; SRVR:AM6PR04MB4871; x-forefront-prvs: 08626BE3A5 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(39860400002)(346002)(376002)(396003)(366004)(136003)(199004)(189003)(2501003)(97736004)(6486002)(256004)(6506007)(68736007)(386003)(14444005)(86362001)(575784001)(2906002)(7416002)(2201001)(478600001)(4744004)(106356001)(71190400001)(71200400001)(305945005)(105586002)(6436002)(66066001)(8676002)(8936002)(7736002)(81156014)(81166006)(4326008)(102836004)(2900100001)(316002)(14454004)(53936002)(53946003)(6512007)(186003)(26005)(25786009)(11346002)(446003)(2616005)(36756003)(99286004)(476003)(3846002)(110136005)(1076002)(52116002)(5660300001)(6116002)(76176011)(486006)(54906003)(921003)(1121003); DIR:OUT; SFP:1101; SCL:1; SRVR:AM6PR04MB4871; H:AM6PR04MB5781.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: MNHEDjqG3J8+H7u1ZJ+biu0HiEMGzRGCGsFZtAAG17KKyXNgQoaxqBi5eUOmL2p8nWBCeprm5TJjxlaW/ruxM7+CvxpO8+qmgq0j7YrsNrQPdvoZJ3CXLYcG9LJWvhwmYMn3Ci10wO3uG6BlhbT/BhGp9nuVt1XZzYviv2rsOsbxamAcTzIZSoC1/ExdCjxTs3VeoyJlVtmrVXCXLaqzgyKl0m82JLIsBoGEeErO/kLVQe6P2dhuh7TpPt7LweOnupW33AnQQimiei5uVZQeTqfbJD703cV0n3+h+1P1Nm7c6Iay2G7LJzrXTgnlkQp+SCMJMZWcjCGaTH/jNARlPBR8jGDHy4Yn0y/UUMXrNAw= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 53a6f05e-7460-4767-85ec-08d64eca27b1 X-MS-Exchange-CrossTenant-originalarrivaltime: 20 Nov 2018 09:25:48.0184 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR04MB4871 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Hou Zhiqiang Just format the code without functionality change. Signed-off-by: Hou Zhiqiang reviewed-by: Minghuan Lian --- V2: - no change drivers/pci/controller/pcie-mobiveil.c | 261 +++++++++++++------------ 1 file changed, 137 insertions(+), 124 deletions(-) diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c index d55c7e780c6e..b87471f08a40 100644 --- a/drivers/pci/controller/pcie-mobiveil.c +++ b/drivers/pci/controller/pcie-mobiveil.c @@ -31,38 +31,40 @@ * translation tables are grouped into windows, each window registers are * grouped into blocks of 4 or 16 registers each */ -#define PAB_REG_BLOCK_SIZE 16 -#define PAB_EXT_REG_BLOCK_SIZE 4 +#define PAB_REG_BLOCK_SIZE 16 +#define PAB_EXT_REG_BLOCK_SIZE 4 -#define PAB_REG_ADDR(offset, win) (offset + (win * PAB_REG_BLOCK_SIZE)) -#define PAB_EXT_REG_ADDR(offset, win) (offset + (win * PAB_EXT_REG_BLOCK_SIZE)) +#define PAB_REG_ADDR(offset, win) \ + (offset + (win * PAB_REG_BLOCK_SIZE)) +#define PAB_EXT_REG_ADDR(offset, win) \ + (offset + (win * PAB_EXT_REG_BLOCK_SIZE)) -#define LTSSM_STATUS 0x0404 -#define LTSSM_STATUS_L0_MASK 0x3f -#define LTSSM_STATUS_L0 0x2d +#define LTSSM_STATUS 0x0404 +#define LTSSM_STATUS_L0_MASK 0x3f +#define LTSSM_STATUS_L0 0x2d -#define PAB_CTRL 0x0808 -#define AMBA_PIO_ENABLE_SHIFT 0 -#define PEX_PIO_ENABLE_SHIFT 1 -#define PAGE_SEL_SHIFT 13 -#define PAGE_SEL_MASK 0x3f -#define PAGE_LO_MASK 0x3ff -#define PAGE_SEL_OFFSET_SHIFT 10 +#define PAB_CTRL 0x0808 +#define AMBA_PIO_ENABLE_SHIFT 0 +#define PEX_PIO_ENABLE_SHIFT 1 +#define PAGE_SEL_SHIFT 13 +#define PAGE_SEL_MASK 0x3f +#define PAGE_LO_MASK 0x3ff +#define PAGE_SEL_OFFSET_SHIFT 10 -#define PAB_AXI_PIO_CTRL 0x0840 -#define APIO_EN_MASK 0xf +#define PAB_AXI_PIO_CTRL 0x0840 +#define APIO_EN_MASK 0xf -#define PAB_PEX_PIO_CTRL 0x08c0 -#define PIO_ENABLE_SHIFT 0 +#define PAB_PEX_PIO_CTRL 0x08c0 +#define PIO_ENABLE_SHIFT 0 #define PAB_INTP_AMBA_MISC_ENB 0x0b0c -#define PAB_INTP_AMBA_MISC_STAT 0x0b1c +#define PAB_INTP_AMBA_MISC_STAT 0x0b1c #define PAB_INTP_INTX_MASK 0x01e0 #define PAB_INTP_MSI_MASK 0x8 -#define PAB_AXI_AMAP_CTRL(win) PAB_REG_ADDR(0x0ba0, win) -#define WIN_ENABLE_SHIFT 0 -#define WIN_TYPE_SHIFT 1 +#define PAB_AXI_AMAP_CTRL(win) PAB_REG_ADDR(0x0ba0, win) +#define WIN_ENABLE_SHIFT 0 +#define WIN_TYPE_SHIFT 1 #define PAB_EXT_AXI_AMAP_SIZE(win) PAB_EXT_REG_ADDR(0xbaf0, win) @@ -70,16 +72,16 @@ #define AXI_WINDOW_ALIGN_MASK 3 #define PAB_AXI_AMAP_PEX_WIN_L(win) PAB_REG_ADDR(0x0ba8, win) -#define PAB_BUS_SHIFT 24 -#define PAB_DEVICE_SHIFT 19 -#define PAB_FUNCTION_SHIFT 16 +#define PAB_BUS_SHIFT 24 +#define PAB_DEVICE_SHIFT 19 +#define PAB_FUNCTION_SHIFT 16 #define PAB_AXI_AMAP_PEX_WIN_H(win) PAB_REG_ADDR(0x0bac, win) #define PAB_INTP_AXI_PIO_CLASS 0x474 -#define PAB_PEX_AMAP_CTRL(win) PAB_REG_ADDR(0x4ba0, win) -#define AMAP_CTRL_EN_SHIFT 0 -#define AMAP_CTRL_TYPE_SHIFT 1 +#define PAB_PEX_AMAP_CTRL(win) PAB_REG_ADDR(0x4ba0, win) +#define AMAP_CTRL_EN_SHIFT 0 +#define AMAP_CTRL_TYPE_SHIFT 1 #define PAB_EXT_PEX_AMAP_SIZEN(win) PAB_EXT_REG_ADDR(0xbef0, win) #define PAB_PEX_AMAP_AXI_WIN(win) PAB_REG_ADDR(0x4ba4, win) @@ -87,39 +89,39 @@ #define PAB_PEX_AMAP_PEX_WIN_H(win) PAB_REG_ADDR(0x4bac, win) /* starting offset of INTX bits in status register */ -#define PAB_INTX_START 5 +#define PAB_INTX_START 5 /* supported number of MSI interrupts */ -#define PCI_NUM_MSI 16 +#define PCI_NUM_MSI 16 /* MSI registers */ -#define MSI_BASE_LO_OFFSET 0x04 -#define MSI_BASE_HI_OFFSET 0x08 -#define MSI_SIZE_OFFSET 0x0c -#define MSI_ENABLE_OFFSET 0x14 -#define MSI_STATUS_OFFSET 0x18 -#define MSI_DATA_OFFSET 0x20 -#define MSI_ADDR_L_OFFSET 0x24 -#define MSI_ADDR_H_OFFSET 0x28 +#define MSI_BASE_LO_OFFSET 0x04 +#define MSI_BASE_HI_OFFSET 0x08 +#define MSI_SIZE_OFFSET 0x0c +#define MSI_ENABLE_OFFSET 0x14 +#define MSI_STATUS_OFFSET 0x18 +#define MSI_DATA_OFFSET 0x20 +#define MSI_ADDR_L_OFFSET 0x24 +#define MSI_ADDR_H_OFFSET 0x28 /* outbound and inbound window definitions */ -#define WIN_NUM_0 0 -#define WIN_NUM_1 1 -#define CFG_WINDOW_TYPE 0 -#define IO_WINDOW_TYPE 1 -#define MEM_WINDOW_TYPE 2 -#define IB_WIN_SIZE ((u64)256 * 1024 * 1024 * 1024) -#define MAX_PIO_WINDOWS 8 +#define WIN_NUM_0 0 +#define WIN_NUM_1 1 +#define CFG_WINDOW_TYPE 0 +#define IO_WINDOW_TYPE 1 +#define MEM_WINDOW_TYPE 2 +#define IB_WIN_SIZE ((u64)256 * 1024 * 1024 * 1024) +#define MAX_PIO_WINDOWS 8 /* Parameters for the waiting for link up routine */ -#define LINK_WAIT_MAX_RETRIES 10 -#define LINK_WAIT_MIN 90000 -#define LINK_WAIT_MAX 100000 +#define LINK_WAIT_MAX_RETRIES 10 +#define LINK_WAIT_MIN 90000 +#define LINK_WAIT_MAX 100000 -#define PAGED_ADDR_BNDRY 0xc00 -#define OFFSET_TO_PAGE_ADDR(off) \ +#define PAGED_ADDR_BNDRY 0xc00 +#define OFFSET_TO_PAGE_ADDR(off) \ ((off & PAGE_LO_MASK) | PAGED_ADDR_BNDRY) -#define OFFSET_TO_PAGE_IDX(off) \ +#define OFFSET_TO_PAGE_IDX(off) \ ((off >> PAGE_SEL_OFFSET_SHIFT) & PAGE_SEL_MASK) struct mobiveil_msi { /* MSI information */ @@ -297,14 +299,14 @@ static void __iomem *mobiveil_pcie_map_bus(struct pci_bus *bus, unsigned int devfn, int where) { struct mobiveil_pcie *pcie = bus->sysdata; + u32 value; if (!mobiveil_pcie_valid_device(bus, devfn)) return NULL; - if (bus->number == pcie->root_bus_nr) { - /* RC config access */ + /* RC config access */ + if (bus->number == pcie->root_bus_nr) return pcie->csr_axi_slave_base + where; - } /* * EP config access (in Config/APIO space) @@ -312,10 +314,12 @@ static void __iomem *mobiveil_pcie_map_bus(struct pci_bus *bus, * (BDF) in PAB_AXI_AMAP_PEX_WIN_L0 Register. * Relies on pci_lock serialization */ - csr_writel(pcie, bus->number << PAB_BUS_SHIFT | - PCI_SLOT(devfn) << PAB_DEVICE_SHIFT | - PCI_FUNC(devfn) << PAB_FUNCTION_SHIFT, - PAB_AXI_AMAP_PEX_WIN_L(WIN_NUM_0)); + value = bus->number << PAB_BUS_SHIFT | + PCI_SLOT(devfn) << PAB_DEVICE_SHIFT | + PCI_FUNC(devfn) << PAB_FUNCTION_SHIFT; + + csr_writel(pcie, value, PAB_AXI_AMAP_PEX_WIN_L(WIN_NUM_0)); + return pcie->config_axi_slave_base + where; } @@ -350,22 +354,22 @@ static void mobiveil_pcie_isr(struct irq_desc *desc) /* Handle INTx */ if (intr_status & PAB_INTP_INTX_MASK) { - shifted_status = csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT) >> - PAB_INTX_START; + shifted_status = csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT); + shifted_status >>= PAB_INTX_START; do { for_each_set_bit(bit, &shifted_status, PCI_NUM_INTX) { virq = irq_find_mapping(pcie->intx_domain, - bit + 1); + bit + 1); if (virq) generic_handle_irq(virq); else - dev_err_ratelimited(dev, - "unexpected IRQ, INT%d\n", bit); + dev_err_ratelimited(dev, "unexpected IRQ, INT%d\n", + bit); /* clear interrupt */ csr_writel(pcie, - shifted_status << PAB_INTX_START, - PAB_INTP_AMBA_MISC_STAT); + shifted_status << PAB_INTX_START, + PAB_INTP_AMBA_MISC_STAT); } } while ((shifted_status >> PAB_INTX_START) != 0); } @@ -375,8 +379,7 @@ static void mobiveil_pcie_isr(struct irq_desc *desc) /* handle MSI interrupts */ while (msi_status & 1) { - msi_data = readl_relaxed(pcie->apb_csr_base - + MSI_DATA_OFFSET); + msi_data = readl_relaxed(pcie->apb_csr_base + MSI_DATA_OFFSET); /* * MSI_STATUS_OFFSET register gets updated to zero @@ -385,18 +388,18 @@ static void mobiveil_pcie_isr(struct irq_desc *desc) * two dummy reads. */ msi_addr_lo = readl_relaxed(pcie->apb_csr_base + - MSI_ADDR_L_OFFSET); + MSI_ADDR_L_OFFSET); msi_addr_hi = readl_relaxed(pcie->apb_csr_base + - MSI_ADDR_H_OFFSET); + MSI_ADDR_H_OFFSET); dev_dbg(dev, "MSI registers, data: %08x, addr: %08x:%08x\n", - msi_data, msi_addr_hi, msi_addr_lo); + msi_data, msi_addr_hi, msi_addr_lo); virq = irq_find_mapping(msi->dev_domain, msi_data); if (virq) generic_handle_irq(virq); msi_status = readl_relaxed(pcie->apb_csr_base + - MSI_STATUS_OFFSET); + MSI_STATUS_OFFSET); } /* Clear the interrupt status */ @@ -413,7 +416,7 @@ static int mobiveil_pcie_parse_dt(struct mobiveil_pcie *pcie) /* map config resource */ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, - "config_axi_slave"); + "config_axi_slave"); pcie->config_axi_slave_base = devm_pci_remap_cfg_resource(dev, res); if (IS_ERR(pcie->config_axi_slave_base)) return PTR_ERR(pcie->config_axi_slave_base); @@ -421,7 +424,7 @@ static int mobiveil_pcie_parse_dt(struct mobiveil_pcie *pcie) /* map csr resource */ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, - "csr_axi_slave"); + "csr_axi_slave"); pcie->csr_axi_slave_base = devm_pci_remap_cfg_resource(dev, res); if (IS_ERR(pcie->csr_axi_slave_base)) return PTR_ERR(pcie->csr_axi_slave_base); @@ -452,7 +455,7 @@ static int mobiveil_pcie_parse_dt(struct mobiveil_pcie *pcie) } static void program_ib_windows(struct mobiveil_pcie *pcie, int win_num, - int pci_addr, u32 type, u64 size) + int pci_addr, u32 type, u64 size) { int pio_ctrl_val; int amap_ctrl_dw; @@ -465,19 +468,20 @@ static void program_ib_windows(struct mobiveil_pcie *pcie, int win_num, } pio_ctrl_val = csr_readl(pcie, PAB_PEX_PIO_CTRL); - csr_writel(pcie, - pio_ctrl_val | (1 << PIO_ENABLE_SHIFT), PAB_PEX_PIO_CTRL); - amap_ctrl_dw = csr_readl(pcie, PAB_PEX_AMAP_CTRL(win_num)); - amap_ctrl_dw = (amap_ctrl_dw | (type << AMAP_CTRL_TYPE_SHIFT)); - amap_ctrl_dw = (amap_ctrl_dw | (1 << AMAP_CTRL_EN_SHIFT)); + pio_ctrl_val |= 1 << PIO_ENABLE_SHIFT; + csr_writel(pcie, pio_ctrl_val, PAB_PEX_PIO_CTRL); - csr_writel(pcie, amap_ctrl_dw | lower_32_bits(size64), - PAB_PEX_AMAP_CTRL(win_num)); + amap_ctrl_dw = csr_readl(pcie, PAB_PEX_AMAP_CTRL(win_num)); + amap_ctrl_dw |= (type << AMAP_CTRL_TYPE_SHIFT) | + (1 << AMAP_CTRL_EN_SHIFT) | + lower_32_bits(size64); + csr_writel(pcie, amap_ctrl_dw, PAB_PEX_AMAP_CTRL(win_num)); csr_writel(pcie, upper_32_bits(size64), PAB_EXT_PEX_AMAP_SIZEN(win_num)); csr_writel(pcie, pci_addr, PAB_PEX_AMAP_AXI_WIN(win_num)); + csr_writel(pcie, pci_addr, PAB_PEX_AMAP_PEX_WIN_L(win_num)); csr_writel(pcie, 0, PAB_PEX_AMAP_PEX_WIN_H(win_num)); } @@ -486,7 +490,8 @@ static void program_ib_windows(struct mobiveil_pcie *pcie, int win_num, * routine to program the outbound windows */ static void program_ob_windows(struct mobiveil_pcie *pcie, int win_num, - u64 cpu_addr, u64 pci_addr, u32 config_io_bit, u64 size) + u64 cpu_addr, u64 pci_addr, + u32 config_io_bit, u64 size) { u32 value, type; @@ -505,7 +510,7 @@ static void program_ob_windows(struct mobiveil_pcie *pcie, int win_num, type = config_io_bit; value = csr_readl(pcie, PAB_AXI_AMAP_CTRL(win_num)); csr_writel(pcie, 1 << WIN_ENABLE_SHIFT | type << WIN_TYPE_SHIFT | - lower_32_bits(size64), PAB_AXI_AMAP_CTRL(win_num)); + lower_32_bits(size64), PAB_AXI_AMAP_CTRL(win_num)); csr_writel(pcie, upper_32_bits(size64), PAB_EXT_AXI_AMAP_SIZE(win_num)); @@ -515,14 +520,14 @@ static void program_ob_windows(struct mobiveil_pcie *pcie, int win_num, */ value = csr_readl(pcie, PAB_AXI_AMAP_AXI_WIN(win_num)); csr_writel(pcie, cpu_addr & (~AXI_WINDOW_ALIGN_MASK), - PAB_AXI_AMAP_AXI_WIN(win_num)); + PAB_AXI_AMAP_AXI_WIN(win_num)); value = csr_readl(pcie, PAB_AXI_AMAP_PEX_WIN_H(win_num)); csr_writel(pcie, lower_32_bits(pci_addr), - PAB_AXI_AMAP_PEX_WIN_L(win_num)); + PAB_AXI_AMAP_PEX_WIN_L(win_num)); csr_writel(pcie, upper_32_bits(pci_addr), - PAB_AXI_AMAP_PEX_WIN_H(win_num)); + PAB_AXI_AMAP_PEX_WIN_H(win_num)); pcie->ob_wins_configured++; } @@ -538,7 +543,9 @@ static int mobiveil_bringup_link(struct mobiveil_pcie *pcie) usleep_range(LINK_WAIT_MIN, LINK_WAIT_MAX); } + dev_err(&pcie->pdev->dev, "link never came up\n"); + return -ETIMEDOUT; } @@ -551,16 +558,16 @@ static void mobiveil_pcie_enable_msi(struct mobiveil_pcie *pcie) msi->msi_pages_phys = (phys_addr_t)msg_addr; writel_relaxed(lower_32_bits(msg_addr), - pcie->apb_csr_base + MSI_BASE_LO_OFFSET); + pcie->apb_csr_base + MSI_BASE_LO_OFFSET); writel_relaxed(upper_32_bits(msg_addr), - pcie->apb_csr_base + MSI_BASE_HI_OFFSET); + pcie->apb_csr_base + MSI_BASE_HI_OFFSET); writel_relaxed(4096, pcie->apb_csr_base + MSI_SIZE_OFFSET); writel_relaxed(1, pcie->apb_csr_base + MSI_ENABLE_OFFSET); } static int mobiveil_host_init(struct mobiveil_pcie *pcie) { - u32 value, pab_ctrl, type = 0; + u32 value, pab_ctrl, type; int err; struct resource_entry *win, *tmp; @@ -575,26 +582,27 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie) * Space */ value = csr_readl(pcie, PCI_COMMAND); - csr_writel(pcie, value | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER, PCI_COMMAND); + value |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; + csr_writel(pcie, value, PCI_COMMAND); /* * program PIO Enable Bit to 1 (and PEX PIO Enable to 1) in PAB_CTRL * register */ pab_ctrl = csr_readl(pcie, PAB_CTRL); - csr_writel(pcie, pab_ctrl | (1 << AMBA_PIO_ENABLE_SHIFT) | - (1 << PEX_PIO_ENABLE_SHIFT), PAB_CTRL); + pab_ctrl |= (1 << AMBA_PIO_ENABLE_SHIFT) | (1 << PEX_PIO_ENABLE_SHIFT); + csr_writel(pcie, pab_ctrl, PAB_CTRL); csr_writel(pcie, (PAB_INTP_INTX_MASK | PAB_INTP_MSI_MASK), - PAB_INTP_AMBA_MISC_ENB); + PAB_INTP_AMBA_MISC_ENB); /* * program PIO Enable Bit to 1 and Config Window Enable Bit to 1 in * PAB_AXI_PIO_CTRL Register */ value = csr_readl(pcie, PAB_AXI_PIO_CTRL); - csr_writel(pcie, value | APIO_EN_MASK, PAB_AXI_PIO_CTRL); + value |= APIO_EN_MASK; + csr_writel(pcie, value, PAB_AXI_PIO_CTRL); /* * we'll program one outbound window for config reads and @@ -605,25 +613,25 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie) /* config outbound translation window */ program_ob_windows(pcie, pcie->ob_wins_configured, - pcie->ob_io_res->start, 0, CFG_WINDOW_TYPE, - resource_size(pcie->ob_io_res)); + pcie->ob_io_res->start, 0, CFG_WINDOW_TYPE, + resource_size(pcie->ob_io_res)); /* memory inbound translation window */ program_ib_windows(pcie, WIN_NUM_1, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE); /* Get the I/O and memory ranges from DT */ resource_list_for_each_entry_safe(win, tmp, &pcie->resources) { - type = 0; if (resource_type(win->res) == IORESOURCE_MEM) type = MEM_WINDOW_TYPE; - if (resource_type(win->res) == IORESOURCE_IO) + else if (resource_type(win->res) == IORESOURCE_IO) type = IO_WINDOW_TYPE; - if (type) { - /* configure outbound translation window */ - program_ob_windows(pcie, pcie->ob_wins_configured, - win->res->start, 0, type, - resource_size(win->res)); - } + else + continue; + + /* configure outbound translation window */ + program_ob_windows(pcie, pcie->ob_wins_configured, + win->res->start, 0, type, + resource_size(win->res)); } /* setup MSI hardware registers */ @@ -643,7 +651,8 @@ static void mobiveil_mask_intx_irq(struct irq_data *data) mask = 1 << ((data->hwirq + PAB_INTX_START) - 1); raw_spin_lock_irqsave(&pcie->intx_mask_lock, flags); shifted_val = csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB); - csr_writel(pcie, (shifted_val & (~mask)), PAB_INTP_AMBA_MISC_ENB); + shifted_val &= ~mask; + csr_writel(pcie, shifted_val, PAB_INTP_AMBA_MISC_ENB); raw_spin_unlock_irqrestore(&pcie->intx_mask_lock, flags); } @@ -658,7 +667,8 @@ static void mobiveil_unmask_intx_irq(struct irq_data *data) mask = 1 << ((data->hwirq + PAB_INTX_START) - 1); raw_spin_lock_irqsave(&pcie->intx_mask_lock, flags); shifted_val = csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB); - csr_writel(pcie, (shifted_val | mask), PAB_INTP_AMBA_MISC_ENB); + shifted_val |= mask; + csr_writel(pcie, shifted_val, PAB_INTP_AMBA_MISC_ENB); raw_spin_unlock_irqrestore(&pcie->intx_mask_lock, flags); } @@ -672,10 +682,11 @@ static struct irq_chip intx_irq_chip = { /* routine to setup the INTx related data */ static int mobiveil_pcie_intx_map(struct irq_domain *domain, unsigned int irq, - irq_hw_number_t hwirq) + irq_hw_number_t hwirq) { irq_set_chip_and_handler(irq, &intx_irq_chip, handle_level_irq); irq_set_chip_data(irq, domain->host_data); + return 0; } @@ -692,7 +703,7 @@ static struct irq_chip mobiveil_msi_irq_chip = { static struct msi_domain_info mobiveil_msi_domain_info = { .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | - MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX), + MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX), .chip = &mobiveil_msi_irq_chip, }; @@ -710,7 +721,7 @@ static void mobiveil_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) } static int mobiveil_msi_set_affinity(struct irq_data *irq_data, - const struct cpumask *mask, bool force) + const struct cpumask *mask, bool force) { return -EINVAL; } @@ -722,7 +733,8 @@ static struct irq_chip mobiveil_msi_bottom_irq_chip = { }; static int mobiveil_irq_msi_domain_alloc(struct irq_domain *domain, - unsigned int virq, unsigned int nr_irqs, void *args) + unsigned int virq, + unsigned int nr_irqs, void *args) { struct mobiveil_pcie *pcie = domain->host_data; struct mobiveil_msi *msi = &pcie->msi; @@ -742,13 +754,13 @@ static int mobiveil_irq_msi_domain_alloc(struct irq_domain *domain, mutex_unlock(&msi->lock); irq_domain_set_info(domain, virq, bit, &mobiveil_msi_bottom_irq_chip, - domain->host_data, handle_level_irq, - NULL, NULL); + domain->host_data, handle_level_irq, NULL, NULL); return 0; } static void mobiveil_irq_msi_domain_free(struct irq_domain *domain, - unsigned int virq, unsigned int nr_irqs) + unsigned int virq, + unsigned int nr_irqs) { struct irq_data *d = irq_domain_get_irq_data(domain, virq); struct mobiveil_pcie *pcie = irq_data_get_irq_chip_data(d); @@ -756,12 +768,11 @@ static void mobiveil_irq_msi_domain_free(struct irq_domain *domain, mutex_lock(&msi->lock); - if (!test_bit(d->hwirq, msi->msi_irq_in_use)) { + if (!test_bit(d->hwirq, msi->msi_irq_in_use)) dev_err(&pcie->pdev->dev, "trying to free unused MSI#%lu\n", d->hwirq); - } else { + else __clear_bit(d->hwirq, msi->msi_irq_in_use); - } mutex_unlock(&msi->lock); } @@ -785,12 +796,14 @@ static int mobiveil_allocate_msi_domains(struct mobiveil_pcie *pcie) } msi->msi_domain = pci_msi_create_irq_domain(fwnode, - &mobiveil_msi_domain_info, msi->dev_domain); + &mobiveil_msi_domain_info, + msi->dev_domain); if (!msi->msi_domain) { dev_err(dev, "failed to create MSI domain\n"); irq_domain_remove(msi->dev_domain); return -ENOMEM; } + return 0; } @@ -801,8 +814,8 @@ static int mobiveil_pcie_init_irq_domain(struct mobiveil_pcie *pcie) int ret; /* setup INTx */ - pcie->intx_domain = irq_domain_add_linear(node, - PCI_NUM_INTX, &intx_domain_ops, pcie); + pcie->intx_domain = irq_domain_add_linear(node, PCI_NUM_INTX, + &intx_domain_ops, pcie); if (!pcie->intx_domain) { dev_err(dev, "Failed to get a INTx IRQ domain\n"); @@ -917,10 +930,10 @@ MODULE_DEVICE_TABLE(of, mobiveil_pcie_of_match); static struct platform_driver mobiveil_pcie_driver = { .probe = mobiveil_pcie_probe, .driver = { - .name = "mobiveil-pcie", - .of_match_table = mobiveil_pcie_of_match, - .suppress_bind_attrs = true, - }, + .name = "mobiveil-pcie", + .of_match_table = mobiveil_pcie_of_match, + .suppress_bind_attrs = true, + }, }; builtin_platform_driver(mobiveil_pcie_driver); From patchwork Tue Nov 20 09:25:54 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Z.Q. Hou" X-Patchwork-Id: 1000328 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=nxp.com header.i=@nxp.com header.b="jrLAHKY6"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42zgLX55kjz9s3l for ; Tue, 20 Nov 2018 20:26:12 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727641AbeKTTyG (ORCPT ); Tue, 20 Nov 2018 14:54:06 -0500 Received: from mail-eopbgr70071.outbound.protection.outlook.com ([40.107.7.71]:41201 "EHLO EUR04-HE1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727665AbeKTTyF (ORCPT ); Tue, 20 Nov 2018 14:54:05 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=207bZctsaspP2NcQBvDjBhbfvMsfFNtrs/iINaCGaMc=; b=jrLAHKY6H7hivNWTzOmh/DQ22MJ8Os1iCgfyKy83bVvEXrt6blLvrkaTET1A56rDiILFfbAtr/4/H1+Wjc3J0aoyp6Go1Iy1Rysw3qYhsKJx73QPmVfej19D+X266ISOdv5yyN8os17HY3W7Uk9FxLQmjEeN5naMOFVyWMC9rD4= Received: from AM6PR04MB5781.eurprd04.prod.outlook.com (20.179.2.80) by AM6PR04MB5269.eurprd04.prod.outlook.com (20.177.35.214) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1339.21; Tue, 20 Nov 2018 09:25:54 +0000 Received: from AM6PR04MB5781.eurprd04.prod.outlook.com ([fe80::29b5:b3ed:3854:cf1c]) by AM6PR04MB5781.eurprd04.prod.outlook.com ([fe80::29b5:b3ed:3854:cf1c%4]) with mapi id 15.20.1339.026; Tue, 20 Nov 2018 09:25:54 +0000 From: "Z.q. Hou" To: "linux-pci@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "bhelgaas@google.com" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "l.subrahmanya@mobiveil.co.in" , "shawnguo@kernel.org" , Leo Li , "lorenzo.pieralisi@arm.com" , "catalin.marinas@arm.com" , "will.deacon@arm.com" CC: Mingkai Hu , "M.h. Lian" , Xiaowei Bao , "Z.q. Hou" Subject: [PATCHv2 03/25] PCI: mobiveil: correct the returned error number Thread-Topic: [PATCHv2 03/25] PCI: mobiveil: correct the returned error number Thread-Index: AQHUgLMJImnOqCelXkOVBM9i5/Oj3Q== Date: Tue, 20 Nov 2018 09:25:54 +0000 Message-ID: <20181120092615.11680-4-Zhiqiang.Hou@nxp.com> References: <20181120092615.11680-1-Zhiqiang.Hou@nxp.com> In-Reply-To: <20181120092615.11680-1-Zhiqiang.Hou@nxp.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: HK2PR03CA0050.apcprd03.prod.outlook.com (2603:1096:202:17::20) To AM6PR04MB5781.eurprd04.prod.outlook.com (2603:10a6:20b:aa::16) authentication-results: spf=none (sender IP is ) smtp.mailfrom=zhiqiang.hou@nxp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [119.31.174.73] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; AM6PR04MB5269; 6:qlAiHWuQYcTNZQazPCgENJqv+V4NN6NyzKaTq5hvUC0H38UnrDCxi4TA2MaFtRTrPt40AgCsbXUaZbHw7gtzoEF44VUvg3qsTSBlN1fr6P8OH6i+V0FfFXgWwnZl8kVw4M8h9kwi2SKhRoDRNg76q8RpPOexB4QPsm71Y2uFrvvQEZEPmqic2oGkFOMW7SmQsDay5qtTKMFyiKCuEHU+rpzIk2MSeN4Rqjp2/ZWSYT6gftVorx7p6gLchAuPEywtgEd+WF9gRQrgwQpYwSjkH++vW5N1dtOt2q82G7oPqFeIyuq3GFGXUvcqH7xUs4xWAG8LJrPJF8IlHUXeKVhWbLNaI/GsuYwQD7A7sPCiB3hxv6MOSPjqnCoIkx7dhskBWb8YC1n4gf79KhTER1BJraDUpDnr9O70xQm48aa5BK7zpQlO5tkle62p+HmOqukT9okVNd6KKQZ957WWyXsL2w==; 5:AsHGVrufRGBsCS3LATUSy0mdH/E6gunlZZWoZlF1l6mGiJq29GFeOyp9sudI+j0vCObUKx1qmUM7eZo/BAvR/soYQXdWFlGs+8bNCBV+StxH/Ldf8dLmNzj53WADAg1XzuDnk+y7XcOB5EMmlPIqb1n84/bObuZaC/jLHRYTa14=; 7:avWUYj15j3SxjRSsiac3h1UZncAPo/a+R1DoBAtUc5VBU81NCeXZPa5jWbJrfrqozqGBeQCxzJEJdSPu+bPvdomhq4Zt4WhJwB4nt+YC9/6Rarck0NzWeDfcSlulv0oWdl/SIHXNWG/+9Vp3UDvm6A== x-ms-office365-filtering-correlation-id: de4b0381-89a7-4104-fd0f-08d64eca2b6f x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390098)(7020095)(4652040)(8989299)(5600074)(711020)(4618075)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7153060)(7193020); SRVR:AM6PR04MB5269; x-ms-traffictypediagnostic: AM6PR04MB5269: x-microsoft-antispam-prvs: x-ms-exchange-senderadcheck: 1 x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(8211001083)(6040522)(2401047)(5005006)(8121501046)(3231442)(944501410)(52105112)(3002001)(10201501046)(93006095)(93001095)(6055026)(148016)(149066)(150057)(6041310)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123558120)(20161123564045)(20161123560045)(20161123562045)(201708071742011)(7699051)(76991095); SRVR:AM6PR04MB5269; BCL:0; PCL:0; RULEID:; SRVR:AM6PR04MB5269; x-forefront-prvs: 08626BE3A5 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(346002)(376002)(136003)(396003)(366004)(39860400002)(189003)(199004)(305945005)(7736002)(36756003)(5660300001)(7416002)(68736007)(2906002)(4326008)(8936002)(14454004)(256004)(54906003)(14444005)(53936002)(6436002)(71200400001)(110136005)(71190400001)(6512007)(316002)(2616005)(476003)(446003)(11346002)(486006)(25786009)(2501003)(2201001)(86362001)(52116002)(76176011)(6506007)(102836004)(386003)(186003)(106356001)(26005)(2900100001)(81156014)(81166006)(105586002)(6486002)(8676002)(99286004)(66066001)(6116002)(3846002)(1076002)(478600001)(97736004)(921003)(1121003); DIR:OUT; SFP:1101; SCL:1; SRVR:AM6PR04MB5269; H:AM6PR04MB5781.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: sq5Z7lWZsFrPH929iThi+4e/pmT0wd2B/6AxcQTnRjpkP9z54a/Zwwu5u9GTsSvApQOZ/KuuI+wxLZeaXTuLT6Uwi48b9HJ3PkYmEVjx388XItORKI31XDcE9C2MWFjGDIEzK1HpBmEARqY25tm0NNxs+tQp3jgX04lsdOttfRzgcY78TZD6FAmjOOn9+BwvZyFEBvYQ+cvyUYYV55k1V6Ifo4BHUuAgVgRZ/RyrX3aA45D9z/JQnpNCiNjbIkJ5Mx4WzCxAtGl24Warq56WE++i9NXtrmt16TDY/DJMCC3+Bw8DrCaCv184Ny2mZv4/t+dB7cmwyUA7nrvLFEXIB+HX136g14+KZexG4geIW7c= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: de4b0381-89a7-4104-fd0f-08d64eca2b6f X-MS-Exchange-CrossTenant-originalarrivaltime: 20 Nov 2018 09:25:54.1281 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR04MB5269 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Hou Zhiqiang This patch corrected the returned error number by convention, and removed a unnecessary error check. Signed-off-by: Hou Zhiqiang reviewed-by: Minghuan Lian --- V2: - no change drivers/pci/controller/pcie-mobiveil.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c index b87471f08a40..563210e731d3 100644 --- a/drivers/pci/controller/pcie-mobiveil.c +++ b/drivers/pci/controller/pcie-mobiveil.c @@ -819,7 +819,7 @@ static int mobiveil_pcie_init_irq_domain(struct mobiveil_pcie *pcie) if (!pcie->intx_domain) { dev_err(dev, "Failed to get a INTx IRQ domain\n"); - return -ENODEV; + return -ENOMEM; } raw_spin_lock_init(&pcie->intx_mask_lock); @@ -845,11 +845,9 @@ static int mobiveil_pcie_probe(struct platform_device *pdev) /* allocate the PCIe port */ bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie)); if (!bridge) - return -ENODEV; + return -ENOMEM; pcie = pci_host_bridge_priv(bridge); - if (!pcie) - return -ENOMEM; pcie->pdev = pdev; @@ -866,7 +864,7 @@ static int mobiveil_pcie_probe(struct platform_device *pdev) &pcie->resources, &iobase); if (ret) { dev_err(dev, "Getting bridge resources failed\n"); - return -ENOMEM; + return ret; } /* From patchwork Tue Nov 20 09:26:00 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Z.Q. Hou" X-Patchwork-Id: 1000327 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=nxp.com header.i=@nxp.com header.b="VHZVqdaM"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42zgLQ4lBjz9s3l for ; Tue, 20 Nov 2018 20:26:06 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727723AbeKTTyM (ORCPT ); Tue, 20 Nov 2018 14:54:12 -0500 Received: from mail-eopbgr50087.outbound.protection.outlook.com ([40.107.5.87]:59609 "EHLO EUR03-VE1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727547AbeKTTyL (ORCPT ); Tue, 20 Nov 2018 14:54:11 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=dNzbdEqE1qipGnEObhKS3c4N64JZ70P/NIiJ5BPIPfw=; b=VHZVqdaMc3l1qo7U4rf08WnyiYAylL2bY6+tafl6xmn+3CpOMxy0uo9lcu2dzjKB1zcm2mkkBR7uv1mNBMABYLUd0aSMvet1p8tKUUbLIWF78aoc/6cye1np//+R29ccB8zT811pfNuRB/dHvEA5HogKrWwAjt9ng1DPz6ubfM0= Received: from AM6PR04MB5781.eurprd04.prod.outlook.com (20.179.2.80) by AM6PR04MB4775.eurprd04.prod.outlook.com (20.177.32.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1339.21; Tue, 20 Nov 2018 09:26:00 +0000 Received: from AM6PR04MB5781.eurprd04.prod.outlook.com ([fe80::29b5:b3ed:3854:cf1c]) by AM6PR04MB5781.eurprd04.prod.outlook.com ([fe80::29b5:b3ed:3854:cf1c%4]) with mapi id 15.20.1339.026; Tue, 20 Nov 2018 09:26:00 +0000 From: "Z.q. Hou" To: "linux-pci@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "bhelgaas@google.com" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "l.subrahmanya@mobiveil.co.in" , "shawnguo@kernel.org" , Leo Li , "lorenzo.pieralisi@arm.com" , "catalin.marinas@arm.com" , "will.deacon@arm.com" CC: Mingkai Hu , "M.h. Lian" , Xiaowei Bao , "Z.q. Hou" Subject: [PATCHv2 04/25] PCI: mobiveil: remove flag MSI_FLAG_MULTI_PCI_MSI Thread-Topic: [PATCHv2 04/25] PCI: mobiveil: remove flag MSI_FLAG_MULTI_PCI_MSI Thread-Index: AQHUgLMM8rqm4Urwp0KDUbnccd0M/Q== Date: Tue, 20 Nov 2018 09:26:00 +0000 Message-ID: <20181120092615.11680-5-Zhiqiang.Hou@nxp.com> References: <20181120092615.11680-1-Zhiqiang.Hou@nxp.com> In-Reply-To: <20181120092615.11680-1-Zhiqiang.Hou@nxp.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: HK2PR03CA0050.apcprd03.prod.outlook.com (2603:1096:202:17::20) To AM6PR04MB5781.eurprd04.prod.outlook.com (2603:10a6:20b:aa::16) authentication-results: spf=none (sender IP is ) smtp.mailfrom=zhiqiang.hou@nxp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [119.31.174.73] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; AM6PR04MB4775; 6:bOmvRoQx5ZoxcwCRaylhMlcs58vqc8W88BcIgrX2ISrzUIhLqfbEgqvJXsR+HCAmTzqPSegWRRHLTL3NS6Mw19YRI92O1redhowCYU3/BQTdtTIpxXjD5BpBhqQ9I7Oty543gFxWH63i6gQNI/0akjw/v9Q9sIykiDFcgojJTw9dTZbn/rdvFGHRkZhMCFKVg9RBISr6bMtGzykb3zd0q+oLHXi7msfkeZaC1PPevgDEh6/XzRnO0fmlqZd/sj7/2xpSLWhBCS4q+NENk0HfT//zUbpT9FxH8M1M0rzgS8xPu7ag254au99I4g7puVqBDeAMj0t7g8BOH1Ym/2cr7lI0oUqHXAsJDK5WWKR5b4c1WUFuMSfr13yYIgZ3jNV0ca39Tjga3dooPJfVUl6I39mbF8ZwQJFf3zQVy83Y46ql5bAVMwzuD58AOuQsFZ4qk+LAaPGd/qRTvdNNzM+wHQ==; 5:0txG6/PW51Qtkq/SpnZUPQLsg95Xtub6woOy12pHkHGDLPiF+ZPdfFrThMzQirpj4Bm3CHqAhPKVP1C9VztBv+5L7DuMh3vBPSRKFgtHgZe5u3LZ7ccTTAZ5DvCUi+whCu+WiySg2ACDLHxODTsyYIxC5o2H3SUr5pwYeAemNlc=; 7:dF/vNjlocVuG5O9VxRgCH2qwRjqdSx9bQQ9aKK7mT4gyu3O4Gn0xNX64S5lmIBPMFbESCkO9dh4M+K9xBgmrqj2Oma3UJ2qcq18+UrJ1XrgLYw4FOaaFSo9ysxa48TIR0l9gfxDPtzq4KNG6n5xkjw== x-ms-office365-filtering-correlation-id: 54671870-8d39-43d9-737b-08d64eca2f0f x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390098)(7020095)(4652040)(8989299)(5600074)(711020)(4618075)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7153060)(7193020); SRVR:AM6PR04MB4775; x-ms-traffictypediagnostic: AM6PR04MB4775: x-microsoft-antispam-prvs: x-ms-exchange-senderadcheck: 1 x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(8211001083)(6040522)(2401047)(8121501046)(5005006)(93006095)(93001095)(3231442)(944501410)(52105112)(3002001)(10201501046)(6055026)(148016)(149066)(150057)(6041310)(20161123562045)(20161123564045)(20161123560045)(20161123558120)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(201708071742011)(7699051)(76991095); SRVR:AM6PR04MB4775; BCL:0; PCL:0; RULEID:; SRVR:AM6PR04MB4775; x-forefront-prvs: 08626BE3A5 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(366004)(39860400002)(136003)(376002)(396003)(346002)(189003)(199004)(66066001)(1076002)(2900100001)(68736007)(8676002)(6486002)(5660300001)(8936002)(6116002)(3846002)(2501003)(97736004)(81166006)(26005)(186003)(81156014)(105586002)(7416002)(102836004)(2906002)(386003)(6506007)(7736002)(305945005)(106356001)(6512007)(76176011)(36756003)(4326008)(99286004)(52116002)(14444005)(25786009)(575784001)(110136005)(54906003)(2616005)(86362001)(53936002)(446003)(11346002)(256004)(2201001)(6436002)(486006)(71190400001)(71200400001)(478600001)(316002)(476003)(14454004)(921003)(1121003); DIR:OUT; SFP:1101; SCL:1; SRVR:AM6PR04MB4775; H:AM6PR04MB5781.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: kwFM8UJyryBFD1o21m1mUAnuERHvagn+l6K6Uwwlp3SKrII8nUzNghaCp49gr4zPiwMKmqwS/nrRJEVu9SucF+RMnk3pDh5C+tlKk8w+94DZF+go/8L/BItVO+WO8OuPI/SceY0CqdV977rk3HlfnVMvQOK5avCjq4bt2LquiCSTmVnR8PFSS/meqD4bQ9XFYmA/udcTQIZHYyiLdUWOzQx1spZCDcR9KbJOEYEe8GC0DeNwBwXGpOFer1cms00cd6QPeBVCcLOHMCAeBxitjKb7Gfw3fb6l/ECbYPvRu60oYqHINbSt4V4vDjOt9XBo/3YUAguZrsiGzGy63PvGWTNCDkG/ut0k4g+JGnfXIU0= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 54671870-8d39-43d9-737b-08d64eca2f0f X-MS-Exchange-CrossTenant-originalarrivaltime: 20 Nov 2018 09:26:00.4249 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR04MB4775 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Hou Zhiqiang The current code does not support multiple MSIs, so remove the corresponding flag from the msi_domain_info structure. Fixes: 1e913e58335f ("PCI: mobiveil: Add MSI support") Signed-off-by: Hou Zhiqiang reviewed-by: Minghuan Lian --- V2: - Added fixes entry. drivers/pci/controller/pcie-mobiveil.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c index 563210e731d3..a0dd337c6214 100644 --- a/drivers/pci/controller/pcie-mobiveil.c +++ b/drivers/pci/controller/pcie-mobiveil.c @@ -703,7 +703,7 @@ static struct irq_chip mobiveil_msi_irq_chip = { static struct msi_domain_info mobiveil_msi_domain_info = { .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | - MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX), + MSI_FLAG_PCI_MSIX), .chip = &mobiveil_msi_irq_chip, }; From patchwork Tue Nov 20 09:26:06 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Z.Q. Hou" X-Patchwork-Id: 1000334 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=nxp.com header.i=@nxp.com header.b="LHpg8pCT"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42zgM36HXMz9s3l for ; Tue, 20 Nov 2018 20:26:39 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727565AbeKTTyT (ORCPT ); Tue, 20 Nov 2018 14:54:19 -0500 Received: from mail-eopbgr70087.outbound.protection.outlook.com ([40.107.7.87]:4817 "EHLO EUR04-HE1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727547AbeKTTyS (ORCPT ); Tue, 20 Nov 2018 14:54:18 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=zAD3kxHDvjp1OmBu2cBMgN2QuND/G0T1GuVoIwyVdu8=; b=LHpg8pCTxI4ZBDyA0+xtdQDg24vRyfq9Onrba+b891yyFXGKXUWiw3tfZz05Ou9MmErD9gS1nvWTlNeyC3+DO4UvUeOncI4RyijNrlHpW7icHJs11E3qwBbMuQjpRENrE2RdhjQnEnLoHHVTd1tFre5COj7UqZ865KFq3nZ9mdg= Received: from AM6PR04MB5781.eurprd04.prod.outlook.com (20.179.2.80) by AM6PR04MB4775.eurprd04.prod.outlook.com (20.177.32.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1339.21; Tue, 20 Nov 2018 09:26:06 +0000 Received: from AM6PR04MB5781.eurprd04.prod.outlook.com ([fe80::29b5:b3ed:3854:cf1c]) by AM6PR04MB5781.eurprd04.prod.outlook.com ([fe80::29b5:b3ed:3854:cf1c%4]) with mapi id 15.20.1339.026; Tue, 20 Nov 2018 09:26:06 +0000 From: "Z.q. Hou" To: "linux-pci@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "bhelgaas@google.com" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "l.subrahmanya@mobiveil.co.in" , "shawnguo@kernel.org" , Leo Li , "lorenzo.pieralisi@arm.com" , "catalin.marinas@arm.com" , "will.deacon@arm.com" CC: Mingkai Hu , "M.h. Lian" , Xiaowei Bao , "Z.q. Hou" Subject: [PATCHv2 05/25] PCI: mobiveil: correct PCI base address in MEM/IO outbound windows Thread-Topic: [PATCHv2 05/25] PCI: mobiveil: correct PCI base address in MEM/IO outbound windows Thread-Index: AQHUgLMQmG1Z3R34uUiTxXvVV6ligg== Date: Tue, 20 Nov 2018 09:26:06 +0000 Message-ID: <20181120092615.11680-6-Zhiqiang.Hou@nxp.com> References: <20181120092615.11680-1-Zhiqiang.Hou@nxp.com> In-Reply-To: <20181120092615.11680-1-Zhiqiang.Hou@nxp.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: HK2PR03CA0050.apcprd03.prod.outlook.com (2603:1096:202:17::20) To AM6PR04MB5781.eurprd04.prod.outlook.com (2603:10a6:20b:aa::16) authentication-results: spf=none (sender IP is ) smtp.mailfrom=zhiqiang.hou@nxp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [119.31.174.73] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; AM6PR04MB4775; 6:MzXS5UcYDQrLmD5LwQTF4OYLzB8SqIF40CepbVfXwd8HScy6OGJ3gIOodEmyiCDJc1x0MTwjffbOl+nESjMbkZPannAgcWneL2pqUwSmqxipLF7QcOM3wKRNQtKl16qyOcVFpT2k9qonGw+WlGifzHT++VQu0wn+/v/Wp+PS3u9Gpe2aZ3hooIp3gZjZbnHGx6vHnl2v1rs/dieDT813hc4lTLpaTO9AcU1OQLCFM7A3qLzMpCMR50z3Iki/aWUmU9sQkIAENrMRojxZd5gwoubyvKAn/ZcFdzomYe4c8cNxK6xc+xi/D6wgCOo/epCBNcUpBLGTNsXW+ThkNG0t9i5y6/ILlg58Gw9h82UDqSOPQUBuuabQINXMygC2ZhpeFEdm9tuXKBS6dQOTS+4rE+i7rL7WRZIwH2rmZisbjlB70p4RExh8vVgusNvjsG9lpMeEM1ZpTIqkgpBOT+qZcg==; 5:NIoYgAsc/MuvRO2ulAvp7aVR4/2MkPYLNT0SxF+8U/v1TNr2Eozd+uPa8k5iKQiYLIj1yZZvOV7n6MenBtLQqbv1nsSnrx4AMteR6uFayNkrwbpCcmDh/vG4fEvmfG123ZSWppa6PV4F/6LDTUbtU0Xp3fQU+rZ7XPkPyJFAKJo=; 7:ctokFemqnnFTU3Fr2rU4u5pQYcDFOKEX0KiW+J8Afr9iX3XMIVioyQkDG9GHQal5SgBP8+a2svNE0bBRnDYSfgBaw6wMayhN/69LJnvriYy8Z6kZgjnRXBMt5eAT+2rPGMYWArwvwGeaXRxy/R41WA== x-ms-office365-filtering-correlation-id: 8f528068-d404-4643-49ca-08d64eca32d0 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390098)(7020095)(4652040)(8989299)(5600074)(711020)(4618075)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7153060)(7193020); SRVR:AM6PR04MB4775; x-ms-traffictypediagnostic: AM6PR04MB4775: x-microsoft-antispam-prvs: x-ms-exchange-senderadcheck: 1 x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(8211001083)(6040522)(2401047)(8121501046)(5005006)(93006095)(93001095)(3231442)(944501410)(52105112)(3002001)(10201501046)(6055026)(148016)(149066)(150057)(6041310)(20161123562045)(20161123564045)(20161123560045)(20161123558120)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(201708071742011)(7699051)(76991095); SRVR:AM6PR04MB4775; BCL:0; PCL:0; RULEID:; SRVR:AM6PR04MB4775; x-forefront-prvs: 08626BE3A5 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(366004)(39860400002)(136003)(376002)(396003)(346002)(189003)(199004)(66066001)(1076002)(2900100001)(68736007)(8676002)(6486002)(5660300001)(8936002)(6116002)(3846002)(2501003)(97736004)(81166006)(26005)(186003)(81156014)(105586002)(7416002)(102836004)(2906002)(386003)(6506007)(7736002)(305945005)(106356001)(6512007)(76176011)(36756003)(4326008)(99286004)(52116002)(25786009)(575784001)(110136005)(54906003)(2616005)(86362001)(53936002)(446003)(11346002)(256004)(2201001)(6436002)(486006)(71190400001)(71200400001)(478600001)(316002)(476003)(14454004)(921003)(1121003); DIR:OUT; SFP:1101; SCL:1; SRVR:AM6PR04MB4775; H:AM6PR04MB5781.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: gyK0PvXxtmIGhY8aL3bK8Ubdo3JlRQ6bztAdHm0eR+plqIhiZQnPChKvy2sVI+rQmw/o3EaZSXQT7IQ42DfF8q9GXhQ9+raKL5nW7Km7hwn3cuWGnQzlhtnAGXC5aa9jXhnlWKHZK8d6HOh9qi0nFZROsLGNh4E7MezIRmXJnoUDZ8/8oeKbqHbvq7UbMcoOJpe1apcJLwpvMFdpHWMFpZ+gOo+ApZneulK4Vx2YsckDTEUAfrUJraDo7h66MJg/Djo8+PBajwq6eCqB+RKfiZs9OQPPUiDpwPDVR1UlPDTMAnENj3TwhQfXZQFlafUzOpsl8OW1K2wip8unFF9vqH19Cl9tSVw0lsl9eIvqpjM= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 8f528068-d404-4643-49ca-08d64eca32d0 X-MS-Exchange-CrossTenant-originalarrivaltime: 20 Nov 2018 09:26:06.6594 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR04MB4775 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Hou Zhiqiang It should get PCI base address from the DT node property 'ranges' to setup MEM/IO outbound windows instead of always zero. Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP driver") Signed-off-by: Hou Zhiqiang reviewed-by: Minghuan Lian --- V2: - Added fixes entry. drivers/pci/controller/pcie-mobiveil.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c index a0dd337c6214..8ff873023b5f 100644 --- a/drivers/pci/controller/pcie-mobiveil.c +++ b/drivers/pci/controller/pcie-mobiveil.c @@ -630,8 +630,9 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie) /* configure outbound translation window */ program_ob_windows(pcie, pcie->ob_wins_configured, - win->res->start, 0, type, - resource_size(win->res)); + win->res->start, + win->res->start - win->offset, + type, resource_size(win->res)); } /* setup MSI hardware registers */ From patchwork Tue Nov 20 09:26:12 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Z.Q. Hou" X-Patchwork-Id: 1000329 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=nxp.com header.i=@nxp.com header.b="DrviNT9a"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42zgLm5BHSz9s1x for ; Tue, 20 Nov 2018 20:26:24 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727760AbeKTTyZ (ORCPT ); Tue, 20 Nov 2018 14:54:25 -0500 Received: from mail-eopbgr70082.outbound.protection.outlook.com ([40.107.7.82]:52352 "EHLO EUR04-HE1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727547AbeKTTyY (ORCPT ); Tue, 20 Nov 2018 14:54:24 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=R4Zo4Mj6JXKZ4oucpy8J0Wxt3IRTZqgIbMtmIickVkI=; b=DrviNT9aw3k3CBi04vLHaBOxxOXsImqhuA7HkHytTJyWugyJw8ZHs27kjfB4nBVVOQOszcLDqa53sqW3DLYvjsGZqr42CaSv89qNcRrzyp/cPvMXNZXFcdPHRtqSkXAucU4fkffwqe5/ksBJ33yg18KJ9i+xbprM5iIWk2Ji/XU= Received: from AM6PR04MB5781.eurprd04.prod.outlook.com (20.179.2.80) by AM6PR04MB4775.eurprd04.prod.outlook.com (20.177.32.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1339.21; Tue, 20 Nov 2018 09:26:13 +0000 Received: from AM6PR04MB5781.eurprd04.prod.outlook.com ([fe80::29b5:b3ed:3854:cf1c]) by AM6PR04MB5781.eurprd04.prod.outlook.com ([fe80::29b5:b3ed:3854:cf1c%4]) with mapi id 15.20.1339.026; Tue, 20 Nov 2018 09:26:13 +0000 From: "Z.q. Hou" To: "linux-pci@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "bhelgaas@google.com" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "l.subrahmanya@mobiveil.co.in" , "shawnguo@kernel.org" , Leo Li , "lorenzo.pieralisi@arm.com" , "catalin.marinas@arm.com" , "will.deacon@arm.com" CC: Mingkai Hu , "M.h. Lian" , Xiaowei Bao , "Z.q. Hou" Subject: [PATCHv2 06/25] PCI: mobiveil: replace the resource list iteration function Thread-Topic: [PATCHv2 06/25] PCI: mobiveil: replace the resource list iteration function Thread-Index: AQHUgLMUKfnITgMTzECPBg3sVfbaQw== Date: Tue, 20 Nov 2018 09:26:12 +0000 Message-ID: <20181120092615.11680-7-Zhiqiang.Hou@nxp.com> References: <20181120092615.11680-1-Zhiqiang.Hou@nxp.com> In-Reply-To: <20181120092615.11680-1-Zhiqiang.Hou@nxp.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: HK2PR03CA0050.apcprd03.prod.outlook.com (2603:1096:202:17::20) To AM6PR04MB5781.eurprd04.prod.outlook.com (2603:10a6:20b:aa::16) authentication-results: spf=none (sender IP is ) smtp.mailfrom=zhiqiang.hou@nxp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [119.31.174.73] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; AM6PR04MB4775; 6:bkXKpfWQPBS9BrrzC6Wb7qzzj0Vy8abFMbNUEWX6r+vlbitkhonmUb6xlCWAM8RCCOLfkpc9oPkjK79y40re8iYjFxC/C1Acmq3PgzhrZ47+OV1iIMAQW0JQ5Wmq7+14GiZZfHZw3R/V+XnXU7Jr1O46BxCYpziP0Vu7ucDjT8PXcabLWgwG8899m6jqugGlzzs3aSL8AHa/rqTP2j1GfdCZ3T6JgnGQTDoJYy+ORvjAzS++3e1l+T/Beq4GmY44Zd8SIHU5WrSMTGaSUr8daf5dpiUxqgYHXFU45e44VKA5LS5fQ+nW+xjta5HcddUqmLytFXaEVd4ipuk+tz5ydZ/H/ZRCK586tzT65BHzt528xFOmBYw2yXpFQsGBEb46BeotsatXSlIX+DJSe/3VkjsxLQ0QLYmyMqT6h5mUUNMw3wShW+F+dhaQixKgRyqezR9moW6cR0S2OV31R+2/hg==; 5:0JADgLybGjGcqk+VXS1yS7URPiGoANtAqWgZOSB0+7re01bzcyEqMz8ZJwQB56muYRyGP/brIXwXcxvLuWQ2SHDLVH81FDsF+Xti5JB875NP8s9vD+BJV/N10r4ITa0kAqA7q2Y9NWfO1m2iiD/oHzjXnz2YjcUXyDSGeMj+BIw=; 7:0MhbixpxdCAAZ31xl65wN94JAzc0L7gk/TmUwx6nxaazvFw/ud4kzowndtlrrqGbw+QkBWsh1jEva4EbZs8AQLJDsw3sI4wpEL8JAhcLP3k2KYnxZIRdZkPnc4jNAAejL0Twdmg8Xc0496UilqREAw== x-ms-office365-filtering-correlation-id: bb71b786-3f35-4e85-3425-08d64eca3685 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390098)(7020095)(4652040)(8989299)(5600074)(711020)(4618075)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7153060)(7193020); SRVR:AM6PR04MB4775; x-ms-traffictypediagnostic: AM6PR04MB4775: x-microsoft-antispam-prvs: x-ms-exchange-senderadcheck: 1 x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(8211001083)(6040522)(2401047)(8121501046)(5005006)(93006095)(93001095)(3231442)(944501410)(52105112)(3002001)(10201501046)(6055026)(148016)(149066)(150057)(6041310)(20161123562045)(20161123564045)(20161123560045)(20161123558120)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(201708071742011)(7699051)(76991095); SRVR:AM6PR04MB4775; BCL:0; PCL:0; RULEID:; SRVR:AM6PR04MB4775; x-forefront-prvs: 08626BE3A5 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(366004)(39860400002)(136003)(376002)(396003)(346002)(189003)(199004)(66066001)(1076002)(2900100001)(68736007)(8676002)(6486002)(5660300001)(8936002)(6116002)(3846002)(2501003)(97736004)(81166006)(26005)(186003)(81156014)(105586002)(7416002)(102836004)(2906002)(386003)(6506007)(7736002)(305945005)(106356001)(6512007)(76176011)(36756003)(4326008)(99286004)(52116002)(14444005)(25786009)(110136005)(54906003)(2616005)(86362001)(53936002)(446003)(11346002)(256004)(2201001)(6436002)(486006)(71190400001)(71200400001)(478600001)(316002)(476003)(14454004)(921003)(1121003); DIR:OUT; SFP:1101; SCL:1; SRVR:AM6PR04MB4775; H:AM6PR04MB5781.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: h9Tjj4Deu2/YjB3jQvVjaxm8aB7rSeezgxy5K07oDbTGSNJ/GMMvxSqgz1zCnDCC2kcvwUE6mpC7mEDBl8O6LF+eJljjpry0UatucgWWRYYAQxioad6QW1YejcD3wz8tL2eowqUSadkPMWK9HSfxQk0pC7yu67yxX+2wdxbcBa8bbLzSqn2x4v5yBOB9dRmF/Y+WxFhk9RmnzLlmOOoSPealkwe5daJ+Y1qlboypkPL3QViFh3uEr7Kbgym4Cdm81DfqOsfnQwaRDS+LNwziZaFPHNAIZJE9SBlAKiOiTyJ/WUZ5xQ0nNAbh2/bcPmA/viyx2cuhMb01PI98lZfN+xwaE2y/xHOQhNbERhumTy0= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: bb71b786-3f35-4e85-3425-08d64eca3685 X-MS-Exchange-CrossTenant-originalarrivaltime: 20 Nov 2018 09:26:12.9251 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR04MB4775 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Hou Zhiqiang As it won't delete any node in this iteration, replaced the function resource_list_for_each_entry_safe() with the resource_list_for_each_entry(). Signed-off-by: Hou Zhiqiang reviewed-by: Minghuan Lian --- V2: - no change drivers/pci/controller/pcie-mobiveil.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c index 8ff873023b5f..b2cc9c097fc9 100644 --- a/drivers/pci/controller/pcie-mobiveil.c +++ b/drivers/pci/controller/pcie-mobiveil.c @@ -569,7 +569,7 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie) { u32 value, pab_ctrl, type; int err; - struct resource_entry *win, *tmp; + struct resource_entry *win; err = mobiveil_bringup_link(pcie); if (err) { @@ -620,7 +620,7 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie) program_ib_windows(pcie, WIN_NUM_1, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE); /* Get the I/O and memory ranges from DT */ - resource_list_for_each_entry_safe(win, tmp, &pcie->resources) { + resource_list_for_each_entry(win, &pcie->resources) { if (resource_type(win->res) == IORESOURCE_MEM) type = MEM_WINDOW_TYPE; else if (resource_type(win->res) == IORESOURCE_IO) From patchwork Tue Nov 20 09:26:19 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Z.Q. Hou" X-Patchwork-Id: 1000330 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=nxp.com header.i=@nxp.com header.b="YhpmWXtG"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42zgLt4wcjz9s3l for ; Tue, 20 Nov 2018 20:26:30 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727547AbeKTTyb (ORCPT ); Tue, 20 Nov 2018 14:54:31 -0500 Received: from mail-eopbgr50066.outbound.protection.outlook.com ([40.107.5.66]:23008 "EHLO EUR03-VE1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727783AbeKTTyb (ORCPT ); Tue, 20 Nov 2018 14:54:31 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Opcavfh7LbCo/FyhKpAdYH6KWmnO2HYLEKI4lROkpaQ=; b=YhpmWXtGWaWPvfFn1hJD39q6TupBc7YlGOMgqykRC91HzelVfwczeH97vkj9yLX6QhAOmM7cIzP/uzVNkH+tyTfPWyr8JCo3dbqkxxQMz8DfR9q/UuGoXRzDjm7nMXrnIX2WTjut86XfE5eRP47PEJR1xtCkLkuicKAch1BnLcw= Received: from AM6PR04MB5781.eurprd04.prod.outlook.com (20.179.2.80) by AM6PR04MB4775.eurprd04.prod.outlook.com (20.177.32.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1339.21; Tue, 20 Nov 2018 09:26:19 +0000 Received: from AM6PR04MB5781.eurprd04.prod.outlook.com ([fe80::29b5:b3ed:3854:cf1c]) by AM6PR04MB5781.eurprd04.prod.outlook.com ([fe80::29b5:b3ed:3854:cf1c%4]) with mapi id 15.20.1339.026; Tue, 20 Nov 2018 09:26:19 +0000 From: "Z.q. Hou" To: "linux-pci@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "bhelgaas@google.com" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "l.subrahmanya@mobiveil.co.in" , "shawnguo@kernel.org" , Leo Li , "lorenzo.pieralisi@arm.com" , "catalin.marinas@arm.com" , "will.deacon@arm.com" CC: Mingkai Hu , "M.h. Lian" , Xiaowei Bao , "Z.q. Hou" Subject: [PATCHv2 07/25] PCI: mobiveil: use WIN_NUM_0 explicitly for CFG outbound window Thread-Topic: [PATCHv2 07/25] PCI: mobiveil: use WIN_NUM_0 explicitly for CFG outbound window Thread-Index: AQHUgLMYsPuS+O3rE0qxjRmQ5zrttQ== Date: Tue, 20 Nov 2018 09:26:19 +0000 Message-ID: <20181120092615.11680-8-Zhiqiang.Hou@nxp.com> References: <20181120092615.11680-1-Zhiqiang.Hou@nxp.com> In-Reply-To: <20181120092615.11680-1-Zhiqiang.Hou@nxp.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: HK2PR03CA0050.apcprd03.prod.outlook.com (2603:1096:202:17::20) To AM6PR04MB5781.eurprd04.prod.outlook.com (2603:10a6:20b:aa::16) authentication-results: spf=none (sender IP is ) smtp.mailfrom=zhiqiang.hou@nxp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [119.31.174.73] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; AM6PR04MB4775; 6:7h5ZhVmOJmhJt0/obafyV59dsLZRPHy8H5KPzBSKv1wr7MbROLuiC7qDUQTvihymklZ6iBV1lsFMXA0cnwxC64a6ysv6WnjIF/bP8tb3gGAM1PG4BeYk1d4+kLK1t/+hc+fuKHBRWeoSYkBOSVZK/1nXQJ6lfgdUnRJlUI2QsIws9L1OqcUKXt23GsfI+CDwo+5UBV+8tFObYctpwxxXHswfLqcQFwUeIda2FFl6uqz9D0wCH8aO4PLV7hs8udxcK12etpVRTZtytm2G7o1KFXHZE6IFBmOcwhO4xNufbozVJjEcAu75tdoICqaNkhYqj7XT2rjoQ1ViP9BAKr5eyZXubEFITr1eAFST7QRFbc7TGfJ5tW4SOSGgeYfJeSaC/EVnAMaTO8m6y1JuOaczRpgrHaD6Iu0SVQsUNgMJ9wbnhp5gTq7B1cH5AaetPo4BP18cCLAa8NCzEfS86uuRsQ==; 5:7ICbZSGvcdCpO+Wq+i0kfTS1tjJ8se/TgnlkZtceRpmtbMyBLzoOwcP7iuq6nVDVIjndxi4TMkv0t+K2p7l3yzcGQkzkFBhvMvvbLdaugWUD4Droof5c7T5s8L6W2xa0V2yLRESuXu8OS3/jN3IYYsDbrWctnij/hEX+pVkZGB8=; 7:cafdTG6hC8fNuTBy5Pj5E9EHQYJDzBx1YFfNBXEorm/e1s57ofJ+2VKk0wsUIB7WkcxHxs0fuxBfL7+sgP7Mq9gsLo1LggbL3tjmR8Z8VdNfZEPz2wr7gfOcD/N3yP4PYIBe8otTWVJd44sMCZevOQ== x-ms-office365-filtering-correlation-id: 21ce356a-fa2d-4c3b-45c8-08d64eca3a41 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390098)(7020095)(4652040)(8989299)(5600074)(711020)(4618075)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7153060)(7193020); SRVR:AM6PR04MB4775; x-ms-traffictypediagnostic: AM6PR04MB4775: x-microsoft-antispam-prvs: x-ms-exchange-senderadcheck: 1 x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(8211001083)(6040522)(2401047)(8121501046)(5005006)(93006095)(93001095)(3231442)(944501410)(52105112)(3002001)(10201501046)(6055026)(148016)(149066)(150057)(6041310)(20161123562045)(20161123564045)(20161123560045)(20161123558120)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(201708071742011)(7699051)(76991095); SRVR:AM6PR04MB4775; BCL:0; PCL:0; RULEID:; SRVR:AM6PR04MB4775; x-forefront-prvs: 08626BE3A5 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(366004)(39860400002)(136003)(376002)(396003)(346002)(189003)(199004)(66066001)(1076002)(2900100001)(68736007)(8676002)(6486002)(5660300001)(8936002)(6116002)(3846002)(2501003)(97736004)(81166006)(26005)(186003)(81156014)(105586002)(7416002)(102836004)(2906002)(386003)(6506007)(7736002)(305945005)(106356001)(6512007)(76176011)(36756003)(4326008)(99286004)(52116002)(25786009)(110136005)(54906003)(2616005)(86362001)(53936002)(446003)(11346002)(256004)(2201001)(6436002)(486006)(71190400001)(71200400001)(478600001)(316002)(476003)(14454004)(921003)(1121003); DIR:OUT; SFP:1101; SCL:1; SRVR:AM6PR04MB4775; H:AM6PR04MB5781.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: kV3165BGsJkeyshI1GmIKC1sk8ctsmb3B/Ed6JkxmRwTjnwNz7DJdPXun2MjOgo/Opn018/IibuE2rRm8ywjYgEbpdawpwIxy0jVM7xKFP9bIDnnxjgXTIh6cqKr1f2YgMEbyR5yfcy6Ow/v+WOtdVJWB9yGGRTjeIyppkopmm1HWdhI26VSnKVmn5QMeHaJk0y0ArYN60Qr1NFmR36f6xDG+b+uyMi6B0I6IZAdDwLCU5FucH59qX0WIpcW3vpGxsPhGdzvGLlOJp4b8J2PsEkvfH7rlmiDzMbmyS2Ett471aONBmqL2mFgSjSmui+Bs8wHhXD6hEa9PCEYmyccILL1izPNrJxK9A7X+pRUmI0= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 21ce356a-fa2d-4c3b-45c8-08d64eca3a41 X-MS-Exchange-CrossTenant-originalarrivaltime: 20 Nov 2018 09:26:19.3157 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR04MB4775 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Hou Zhiqiang As the .map_bus() use the WIN_NUM_0 for CFG transactions, it's better passing WIN_NUM_0 explicitly when initialize the CFG outbound window. Signed-off-by: Hou Zhiqiang reviewed-by: Minghuan Lian --- V2: - no change drivers/pci/controller/pcie-mobiveil.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c index b2cc9c097fc9..df71c11b4810 100644 --- a/drivers/pci/controller/pcie-mobiveil.c +++ b/drivers/pci/controller/pcie-mobiveil.c @@ -612,9 +612,8 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie) */ /* config outbound translation window */ - program_ob_windows(pcie, pcie->ob_wins_configured, - pcie->ob_io_res->start, 0, CFG_WINDOW_TYPE, - resource_size(pcie->ob_io_res)); + program_ob_windows(pcie, WIN_NUM_0, pcie->ob_io_res->start, 0, + CFG_WINDOW_TYPE, resource_size(pcie->ob_io_res)); /* memory inbound translation window */ program_ib_windows(pcie, WIN_NUM_1, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE); From patchwork Tue Nov 20 09:26:25 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Z.Q. Hou" X-Patchwork-Id: 1000332 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=nxp.com header.i=@nxp.com header.b="WEECG5ZB"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42zgM16V8Jz9s1x for ; Tue, 20 Nov 2018 20:26:37 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727785AbeKTTyi (ORCPT ); Tue, 20 Nov 2018 14:54:38 -0500 Received: from mail-eopbgr70088.outbound.protection.outlook.com ([40.107.7.88]:43952 "EHLO EUR04-HE1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727783AbeKTTyh (ORCPT ); Tue, 20 Nov 2018 14:54:37 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ZtBbuMrmWGxhwN+xAsr4ZYgWEAafahk94nP828Rkgmw=; b=WEECG5ZB/q2qtpZNmCKc7rq6tw6XP44m7Bd2J7FR1UEkpoOl7woFsg+oZteiSkiM84RlgBOzelZ29THPm7KPLXEmWGeZ973hRzMRvazY2w2TgLl72NTn0hi+53p7T/oCZViQO1ecr/Q+CXm97U2niQx+LA9Df5a146gPBl1PBxU= Received: from AM6PR04MB5781.eurprd04.prod.outlook.com (20.179.2.80) by AM6PR04MB4775.eurprd04.prod.outlook.com (20.177.32.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1339.21; Tue, 20 Nov 2018 09:26:25 +0000 Received: from AM6PR04MB5781.eurprd04.prod.outlook.com ([fe80::29b5:b3ed:3854:cf1c]) by AM6PR04MB5781.eurprd04.prod.outlook.com ([fe80::29b5:b3ed:3854:cf1c%4]) with mapi id 15.20.1339.026; Tue, 20 Nov 2018 09:26:25 +0000 From: "Z.q. Hou" To: "linux-pci@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "bhelgaas@google.com" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "l.subrahmanya@mobiveil.co.in" , "shawnguo@kernel.org" , Leo Li , "lorenzo.pieralisi@arm.com" , "catalin.marinas@arm.com" , "will.deacon@arm.com" CC: Mingkai Hu , "M.h. Lian" , Xiaowei Bao , "Z.q. Hou" Subject: [PATCHv2 08/25] PCI: mobiveil: use the 1st inbound window for MEM inbound transactions Thread-Topic: [PATCHv2 08/25] PCI: mobiveil: use the 1st inbound window for MEM inbound transactions Thread-Index: AQHUgLMbULVFEh4b3Eub11F03FJn4Q== Date: Tue, 20 Nov 2018 09:26:25 +0000 Message-ID: <20181120092615.11680-9-Zhiqiang.Hou@nxp.com> References: <20181120092615.11680-1-Zhiqiang.Hou@nxp.com> In-Reply-To: <20181120092615.11680-1-Zhiqiang.Hou@nxp.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: HK2PR03CA0050.apcprd03.prod.outlook.com (2603:1096:202:17::20) To AM6PR04MB5781.eurprd04.prod.outlook.com (2603:10a6:20b:aa::16) authentication-results: spf=none (sender IP is ) smtp.mailfrom=zhiqiang.hou@nxp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [119.31.174.73] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; AM6PR04MB4775; 6:ZzPJfNWnnsYI53S+iAdYVG7aoyPEbTkHKzn3pfISH4/1TVBZ8WBTPd9c+QYHZepNtQ0uul+rcjDKKznpHM0zdfN1M94WRWuwiQCN3zX6z+tzsdwG3wvqK+85MkKsqHS1JTQ9fpCHynaFNk17Y5ie073/PHRAADhqZ0G1hPXUey9SDDFCT/vz/YSyLHKmgr8jYqsB6PNL8OY8B5Bszn6my/27Ma9hp36vaMc50hmjo/FIDAqCzaHff0wiee9WXMlmwJqWnOyEl8M+4Fk2Bio6qGAiUCvL7hgBMFn2NwrJCRePhkxqir5+MVQAJbF+/Skpb6D3rcyznyQSZ7ZHJ+RqczxmTAViLbYqoTnmdtXe3goBWp1R+JxGLrJ9Nu1pyQryPW0ppsDlbuY72xTpXUOSNat7opo1wCHGHDWw0nNnuEIF6ZLQ+hYz7aIubvwbJa7vUBbKOckV50vrbjEiHH610A==; 5:8zSNnW2np+Sd19dkpnitJ6xvi2yKbYhdv11mYj+3bE/7WtBfC96jbbnpnoP6muwNjbHLVOPRNAMUFvH2RFQQ4DIWVBD/WoME8I2aVYRWpNPWDFy+GCnmowg1th8Wle6SUzH9In5kfRHdpHK3YVx5xIxcHkr9IMTR55dfM0uXkMY=; 7:CMykT+AaqVYJSf9rJ8OrAx6IEUtwhu0DpoPebR5ab3KdsxhWu6EYitMNW8Jh+2/l1nso3OAS1ni34BjZoqEsG9LnSDs5Qs/9c/k2MX+wDbp6UNJ0K9I511h5TX8Z8RTdaFhqqyBB0oJrJcLKBeVapQ== x-ms-office365-filtering-correlation-id: ea0d6692-dcdb-47af-6a13-08d64eca3e10 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390098)(7020095)(4652040)(8989299)(5600074)(711020)(4618075)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7153060)(7193020); SRVR:AM6PR04MB4775; x-ms-traffictypediagnostic: AM6PR04MB4775: x-microsoft-antispam-prvs: x-ms-exchange-senderadcheck: 1 x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(8211001083)(6040522)(2401047)(8121501046)(5005006)(93006095)(93001095)(3231442)(944501410)(52105112)(3002001)(10201501046)(6055026)(148016)(149066)(150057)(6041310)(20161123562045)(20161123564045)(20161123560045)(20161123558120)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(201708071742011)(7699051)(76991095); SRVR:AM6PR04MB4775; BCL:0; PCL:0; RULEID:; SRVR:AM6PR04MB4775; x-forefront-prvs: 08626BE3A5 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(366004)(39860400002)(136003)(376002)(396003)(346002)(189003)(199004)(66066001)(1076002)(2900100001)(68736007)(8676002)(6486002)(5660300001)(8936002)(6116002)(3846002)(2501003)(97736004)(81166006)(26005)(186003)(81156014)(105586002)(7416002)(102836004)(2906002)(386003)(6506007)(7736002)(305945005)(106356001)(6512007)(76176011)(36756003)(4326008)(99286004)(52116002)(14444005)(25786009)(110136005)(54906003)(2616005)(86362001)(53936002)(446003)(11346002)(256004)(2201001)(6436002)(486006)(71190400001)(71200400001)(478600001)(316002)(476003)(14454004)(921003)(1121003); DIR:OUT; SFP:1101; SCL:1; SRVR:AM6PR04MB4775; H:AM6PR04MB5781.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: 6KJ1GjpFdDZfi37ewh0jXplm4xIbrKqtxjTbuW8uNM1Zq+A9jIJAz8ktQHjV+uVvJS/dnFXIXAgEBJD8dgS+WSYblfzDbtlb9YLQzo2vZupC4r4gPdmN9cxGu5B2evrU8S1HU9+qKuYcVaUgeMiO3g8zy6nHX/+OVy+q9orS+GyJleJriQOcmZcNTK3pyQw7YJrmnfegf+Neep4Zw1JYr/+nFcksn8dYcZLqAsZWOP0Rl2eCRNdQGanpxgK25sE8HwwXPfVkuHXLM96mdG+itKuO6FSqONdk03AkRk0K9KxagzmovxTYMihqhOoBDO6FedfPt/TyljQdoO3aGJobh5p+Q/aIb7desGLNMBzRvV8= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: ea0d6692-dcdb-47af-6a13-08d64eca3e10 X-MS-Exchange-CrossTenant-originalarrivaltime: 20 Nov 2018 09:26:25.6908 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR04MB4775 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Hou Zhiqiang The inbound windows have different register set with outbound windows. This patch change the MEM inbound window to the first one. Signed-off-by: Hou Zhiqiang reviewed-by: Minghuan Lian --- V2: - no change drivers/pci/controller/pcie-mobiveil.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c index df71c11b4810..e88afc792a5c 100644 --- a/drivers/pci/controller/pcie-mobiveil.c +++ b/drivers/pci/controller/pcie-mobiveil.c @@ -616,7 +616,7 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie) CFG_WINDOW_TYPE, resource_size(pcie->ob_io_res)); /* memory inbound translation window */ - program_ib_windows(pcie, WIN_NUM_1, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE); + program_ib_windows(pcie, WIN_NUM_0, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE); /* Get the I/O and memory ranges from DT */ resource_list_for_each_entry(win, &pcie->resources) { From patchwork Tue Nov 20 09:26:31 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Z.Q. Hou" X-Patchwork-Id: 1000355 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=nxp.com header.i=@nxp.com header.b="FTZ51UYF"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42zgPX6XVPz9s1x for ; Tue, 20 Nov 2018 20:28:48 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727581AbeKTTyq (ORCPT ); Tue, 20 Nov 2018 14:54:46 -0500 Received: from mail-eopbgr70059.outbound.protection.outlook.com ([40.107.7.59]:1760 "EHLO EUR04-HE1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726716AbeKTTyp (ORCPT ); Tue, 20 Nov 2018 14:54:45 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=uv7d7aRXjXXLBi9qVH1Wav4d3eWy/uugc2EqsvYzyEA=; b=FTZ51UYFEgObqFMWFXxhlUEUD8GpPFqB5fEE91COPITjonqbeefl5cqBInaHbNE+w7NAHrz7BEr3aK4nSs1codoVYZE5GWEjdnVhzzuPkpxM/4XAViOEd2rqi1P+yLtiIScWGTTvDiulK+NB0od7yfdufhegD0UNECQ2zMV3W6M= Received: from AM6PR04MB5781.eurprd04.prod.outlook.com (20.179.2.80) by AM6PR04MB5269.eurprd04.prod.outlook.com (20.177.35.214) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1339.21; Tue, 20 Nov 2018 09:26:31 +0000 Received: from AM6PR04MB5781.eurprd04.prod.outlook.com ([fe80::29b5:b3ed:3854:cf1c]) by AM6PR04MB5781.eurprd04.prod.outlook.com ([fe80::29b5:b3ed:3854:cf1c%4]) with mapi id 15.20.1339.026; Tue, 20 Nov 2018 09:26:31 +0000 From: "Z.q. Hou" To: "linux-pci@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "bhelgaas@google.com" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "l.subrahmanya@mobiveil.co.in" , "shawnguo@kernel.org" , Leo Li , "lorenzo.pieralisi@arm.com" , "catalin.marinas@arm.com" , "will.deacon@arm.com" CC: Mingkai Hu , "M.h. Lian" , Xiaowei Bao , "Z.q. Hou" Subject: [PATCHv2 09/25] PCI: mobiveil: correct inbound/outbound window setup routines Thread-Topic: [PATCHv2 09/25] PCI: mobiveil: correct inbound/outbound window setup routines Thread-Index: AQHUgLMfzg72EygTE02IZiCF1pLIHA== Date: Tue, 20 Nov 2018 09:26:31 +0000 Message-ID: <20181120092615.11680-10-Zhiqiang.Hou@nxp.com> References: <20181120092615.11680-1-Zhiqiang.Hou@nxp.com> In-Reply-To: <20181120092615.11680-1-Zhiqiang.Hou@nxp.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: HK2PR03CA0050.apcprd03.prod.outlook.com (2603:1096:202:17::20) To AM6PR04MB5781.eurprd04.prod.outlook.com (2603:10a6:20b:aa::16) authentication-results: spf=none (sender IP is ) smtp.mailfrom=zhiqiang.hou@nxp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [119.31.174.73] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; AM6PR04MB5269; 6:WdihQqDyxyYuH7aSwHQii/wp1jq+OZkim/hFXtCPUkKfij2ske73pXxJfgR60gDpxmYvm5XQe7fL9fHh+f6AsDnIFKWvoo2RXUfqKjqLoRQs7xN0eZ/BATsKJ5h+/5wVguYBX2h7UUiTvsU9dezt22FVQNSR9rqU+d6XbC6HMRG5jlifpQ6GFMBd+FKrEZq+DYM3HekYzS30fiau8V/kOlBllfHgRcUTQYEvqRkjjL16lkM7h0Pq1xhaWBI4QPpPfxQsjrAG6ifiAHbr1mGJw6KfWqyP3HhXmlfpPH6ikQeZ+ZV4ceyFkTE0LbhdVZdD5xlsN0fA0pSw36jClFe9EQ+lEbtRVpVDLGui5lB2q9PNvVp6/1GZzWLtqcgoJRR9srcgTCG2NSZm2hY3YqpeQ716QgvBeTUoCj/K5RRLakd9ZX4iNtfbPnSR+ulyFyR7CFljHy4fbT03dYarxvT8+A==; 5:SjRq9rCtQ1XGsKI0AJICR32/bNLto1KIvhcVrV5EOLMCR+HeHCdAU2f3xpHqs5lssuIpdZJDkIE3+J0H2Qh++gFz43DOAg9GLNnxm9FlkmFPw9JRdsUkoedS2MPmaIDB2GT1SMkEgnpVRq9dbWfptqpx0HNV8FhHgbIVc63U9Kw=; 7:HtrVDOLkg21ns8xCN68u/AxwAZtv4+iPJ89fqieSXdEA9NL9JBTU9Cgh35Zjyk0t6n/E6iMq55hZhhVtDGZAo5Fn+ejoITP96LvhvUtBvOX3PEd7NYpDuSsAW2nBueE5tMIPzA2H1dCtGhQJtIpYow== x-ms-office365-filtering-correlation-id: 5d824447-a65f-4cea-2c15-08d64eca41dd x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390098)(7020095)(4652040)(8989299)(5600074)(711020)(4618075)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7153060)(7193020); SRVR:AM6PR04MB5269; x-ms-traffictypediagnostic: AM6PR04MB5269: x-microsoft-antispam-prvs: x-ms-exchange-senderadcheck: 1 x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(8211001083)(6040522)(2401047)(5005006)(8121501046)(3231442)(944501410)(52105112)(3002001)(10201501046)(93006095)(93001095)(6055026)(148016)(149066)(150057)(6041310)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123558120)(20161123564045)(20161123560045)(20161123562045)(201708071742011)(7699051)(76991095); SRVR:AM6PR04MB5269; BCL:0; PCL:0; RULEID:; SRVR:AM6PR04MB5269; x-forefront-prvs: 08626BE3A5 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(979002)(346002)(376002)(136003)(396003)(366004)(39860400002)(189003)(199004)(305945005)(7736002)(36756003)(5660300001)(7416002)(68736007)(2906002)(4326008)(8936002)(14454004)(256004)(54906003)(53936002)(6436002)(71200400001)(110136005)(71190400001)(6512007)(316002)(2616005)(476003)(446003)(11346002)(486006)(25786009)(2501003)(2201001)(86362001)(575784001)(52116002)(76176011)(6506007)(102836004)(386003)(186003)(106356001)(26005)(2900100001)(81156014)(81166006)(105586002)(6486002)(8676002)(99286004)(66066001)(6116002)(3846002)(1076002)(478600001)(97736004)(921003)(1121003)(969003)(989001)(999001)(1009001)(1019001); DIR:OUT; SFP:1101; SCL:1; SRVR:AM6PR04MB5269; H:AM6PR04MB5781.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: daiOWTPkIPX/bIFZdU6bXfx5GdfC5WRlZmQ41Us9isdyxo+xZ0Bsf287+j4hC7Oe+Hn+R99+9u1k9xxCLDAQtVxlS03u0mdAzdWknaEEFgdlsZaqS0A2wvg0id33HybBJ7lwYzKtSb2YmJImQQoVTw2U4KWj5KY11Wr6UFmo3lvmnEIzWIgQWQX/M9HFwqazTyNrovdFUjtkBqRLp8D17Dlxck5fTtmFty3URbANDHSh5xV3u8K39YJDy6NcYmuVsNH+WOytYBmdsdV+yAlP5roONrkjGWOIW87fm1+GqpT0WH/FIMJ13Cnqvw/2K82HQf4BcDPc9pDq5tLI735JDBkgFJLw1Ckjh1RldrPp7og= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5d824447-a65f-4cea-2c15-08d64eca41dd X-MS-Exchange-CrossTenant-originalarrivaltime: 20 Nov 2018 09:26:31.8002 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR04MB5269 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Hou Zhiqiang Outbound window routine: - Removed unused var definition and register read operations. - Added the upper 32-bit cpu address setup of the window. - Instead of blindly write, only change the fields specified. - Masked the lower bits of window size in case override the control bits. - Check if the passing window number is available, instead of the total number of the initialized windows. Inbound window routine: - Added parameter 'u64 cpu_addr' to specify the cpu address of the window instead of using 'pci_addr'. - Changed 'int pci_addr' to 'u64 pci_addr', and added setup of the upper 32-bit pci address of the window. - Moved the PCIe PIO master enablement to mobiveil_host_init(). - Instead of blindly write, only change the fields specified. - Masked the lower bits of window size in case override the control bits. - Check if the passing window number is available, instead of the total number of the initialized windows. - And added the statistic of initialized inbound windows. Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP driver") Signed-off-by: Hou Zhiqiang reviewed-by: Minghuan Lian reviewed-by: Minghuan Lian --- V2: - Inbound window setup rountine: clear the size field before set it. drivers/pci/controller/pcie-mobiveil.c | 70 +++++++++++++++----------- 1 file changed, 42 insertions(+), 28 deletions(-) diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c index e88afc792a5c..4ba458474e42 100644 --- a/drivers/pci/controller/pcie-mobiveil.c +++ b/drivers/pci/controller/pcie-mobiveil.c @@ -65,9 +65,13 @@ #define PAB_AXI_AMAP_CTRL(win) PAB_REG_ADDR(0x0ba0, win) #define WIN_ENABLE_SHIFT 0 #define WIN_TYPE_SHIFT 1 +#define WIN_TYPE_MASK 0x3 +#define WIN_SIZE_SHIFT 10 +#define WIN_SIZE_MASK 0x3fffff #define PAB_EXT_AXI_AMAP_SIZE(win) PAB_EXT_REG_ADDR(0xbaf0, win) +#define PAB_EXT_AXI_AMAP_AXI_WIN(win) PAB_EXT_REG_ADDR(0x80a0, win) #define PAB_AXI_AMAP_AXI_WIN(win) PAB_REG_ADDR(0x0ba4, win) #define AXI_WINDOW_ALIGN_MASK 3 @@ -82,8 +86,10 @@ #define PAB_PEX_AMAP_CTRL(win) PAB_REG_ADDR(0x4ba0, win) #define AMAP_CTRL_EN_SHIFT 0 #define AMAP_CTRL_TYPE_SHIFT 1 +#define AMAP_CTRL_TYPE_MASK 3 #define PAB_EXT_PEX_AMAP_SIZEN(win) PAB_EXT_REG_ADDR(0xbef0, win) +#define PAB_EXT_PEX_AMAP_AXI_WIN(win) PAB_EXT_REG_ADDR(0xb4a0, win) #define PAB_PEX_AMAP_AXI_WIN(win) PAB_REG_ADDR(0x4ba4, win) #define PAB_PEX_AMAP_PEX_WIN_L(win) PAB_REG_ADDR(0x4ba8, win) #define PAB_PEX_AMAP_PEX_WIN_H(win) PAB_REG_ADDR(0x4bac, win) @@ -455,49 +461,51 @@ static int mobiveil_pcie_parse_dt(struct mobiveil_pcie *pcie) } static void program_ib_windows(struct mobiveil_pcie *pcie, int win_num, - int pci_addr, u32 type, u64 size) + u64 cpu_addr, u64 pci_addr, u32 type, u64 size) { - int pio_ctrl_val; - int amap_ctrl_dw; + u32 value; u64 size64 = ~(size - 1); - if ((pcie->ib_wins_configured + 1) > pcie->ppio_wins) { + if (win_num >= pcie->ppio_wins) { dev_err(&pcie->pdev->dev, "ERROR: max inbound windows reached !\n"); return; } - pio_ctrl_val = csr_readl(pcie, PAB_PEX_PIO_CTRL); - pio_ctrl_val |= 1 << PIO_ENABLE_SHIFT; - csr_writel(pcie, pio_ctrl_val, PAB_PEX_PIO_CTRL); - - amap_ctrl_dw = csr_readl(pcie, PAB_PEX_AMAP_CTRL(win_num)); - amap_ctrl_dw |= (type << AMAP_CTRL_TYPE_SHIFT) | - (1 << AMAP_CTRL_EN_SHIFT) | - lower_32_bits(size64); - csr_writel(pcie, amap_ctrl_dw, PAB_PEX_AMAP_CTRL(win_num)); + value = csr_readl(pcie, PAB_PEX_AMAP_CTRL(win_num)); + value &= ~(AMAP_CTRL_TYPE_MASK << AMAP_CTRL_TYPE_SHIFT | + WIN_SIZE_MASK << WIN_SIZE_SHIFT); + value |= (type << AMAP_CTRL_TYPE_SHIFT) | (1 << AMAP_CTRL_EN_SHIFT) | + (lower_32_bits(size64) & WIN_SIZE_MASK << WIN_SIZE_SHIFT); + csr_writel(pcie, value, PAB_PEX_AMAP_CTRL(win_num)); csr_writel(pcie, upper_32_bits(size64), PAB_EXT_PEX_AMAP_SIZEN(win_num)); - csr_writel(pcie, pci_addr, PAB_PEX_AMAP_AXI_WIN(win_num)); + csr_writel(pcie, lower_32_bits(cpu_addr), + PAB_PEX_AMAP_AXI_WIN(win_num)); + csr_writel(pcie, upper_32_bits(cpu_addr), + PAB_EXT_PEX_AMAP_AXI_WIN(win_num)); + + csr_writel(pcie, lower_32_bits(pci_addr), + PAB_PEX_AMAP_PEX_WIN_L(win_num)); + csr_writel(pcie, upper_32_bits(pci_addr), + PAB_PEX_AMAP_PEX_WIN_H(win_num)); - csr_writel(pcie, pci_addr, PAB_PEX_AMAP_PEX_WIN_L(win_num)); - csr_writel(pcie, 0, PAB_PEX_AMAP_PEX_WIN_H(win_num)); + pcie->ib_wins_configured++; } /* * routine to program the outbound windows */ static void program_ob_windows(struct mobiveil_pcie *pcie, int win_num, - u64 cpu_addr, u64 pci_addr, - u32 config_io_bit, u64 size) + u64 cpu_addr, u64 pci_addr, u32 type, u64 size) { - u32 value, type; + u32 value; u64 size64 = ~(size - 1); - if ((pcie->ob_wins_configured + 1) > pcie->apio_wins) { + if (win_num >= pcie->apio_wins) { dev_err(&pcie->pdev->dev, "ERROR: max outbound windows reached !\n"); return; @@ -507,10 +515,12 @@ static void program_ob_windows(struct mobiveil_pcie *pcie, int win_num, * program Enable Bit to 1, Type Bit to (00) base 2, AXI Window Size Bit * to 4 KB in PAB_AXI_AMAP_CTRL register */ - type = config_io_bit; value = csr_readl(pcie, PAB_AXI_AMAP_CTRL(win_num)); - csr_writel(pcie, 1 << WIN_ENABLE_SHIFT | type << WIN_TYPE_SHIFT | - lower_32_bits(size64), PAB_AXI_AMAP_CTRL(win_num)); + value &= ~(WIN_TYPE_MASK << WIN_TYPE_SHIFT | + WIN_SIZE_MASK << WIN_SIZE_SHIFT); + value |= 1 << WIN_ENABLE_SHIFT | type << WIN_TYPE_SHIFT | + (lower_32_bits(size64) & WIN_SIZE_MASK << WIN_SIZE_SHIFT); + csr_writel(pcie, value, PAB_AXI_AMAP_CTRL(win_num)); csr_writel(pcie, upper_32_bits(size64), PAB_EXT_AXI_AMAP_SIZE(win_num)); @@ -518,11 +528,10 @@ static void program_ob_windows(struct mobiveil_pcie *pcie, int win_num, * program AXI window base with appropriate value in * PAB_AXI_AMAP_AXI_WIN0 register */ - value = csr_readl(pcie, PAB_AXI_AMAP_AXI_WIN(win_num)); - csr_writel(pcie, cpu_addr & (~AXI_WINDOW_ALIGN_MASK), + csr_writel(pcie, lower_32_bits(cpu_addr) & (~AXI_WINDOW_ALIGN_MASK), PAB_AXI_AMAP_AXI_WIN(win_num)); - - value = csr_readl(pcie, PAB_AXI_AMAP_PEX_WIN_H(win_num)); + csr_writel(pcie, upper_32_bits(cpu_addr), + PAB_EXT_AXI_AMAP_AXI_WIN(win_num)); csr_writel(pcie, lower_32_bits(pci_addr), PAB_AXI_AMAP_PEX_WIN_L(win_num)); @@ -604,6 +613,11 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie) value |= APIO_EN_MASK; csr_writel(pcie, value, PAB_AXI_PIO_CTRL); + /* Enable PCIe PIO master */ + value = csr_readl(pcie, PAB_PEX_PIO_CTRL); + value |= 1 << PIO_ENABLE_SHIFT; + csr_writel(pcie, value, PAB_PEX_PIO_CTRL); + /* * we'll program one outbound window for config reads and * another default inbound window for all the upstream traffic @@ -616,7 +630,7 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie) CFG_WINDOW_TYPE, resource_size(pcie->ob_io_res)); /* memory inbound translation window */ - program_ib_windows(pcie, WIN_NUM_0, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE); + program_ib_windows(pcie, WIN_NUM_0, 0, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE); /* Get the I/O and memory ranges from DT */ resource_list_for_each_entry(win, &pcie->resources) { From patchwork Tue Nov 20 09:26:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Z.Q. Hou" X-Patchwork-Id: 1000336 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=nxp.com header.i=@nxp.com header.b="VCo/ZHKH"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42zgM830yTz9s1x for ; Tue, 20 Nov 2018 20:26:44 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727583AbeKTTyv (ORCPT ); Tue, 20 Nov 2018 14:54:51 -0500 Received: from mail-eopbgr70045.outbound.protection.outlook.com ([40.107.7.45]:62088 "EHLO EUR04-HE1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726716AbeKTTyu (ORCPT ); Tue, 20 Nov 2018 14:54:50 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=VkrwOlIe0p0nc1Q29ASMybBvLH+bLhdoWNV6ai411VA=; b=VCo/ZHKHfhPAQDTtMNdlDVPqbqu73t1LvjtuYsqbvpTKWdW68KbxFILotET6w+QGuxK5diOSzZ3z45wlUAXD7cH1yebrEitR/gxDU7pA3av5vOwvoP7SUncdeXPOXZ6VNkly/pzZK62rMI9XLkDeyQvKQwnTJ6QDHiMyNkE9uVA= Received: from AM6PR04MB5781.eurprd04.prod.outlook.com (20.179.2.80) by AM6PR04MB5269.eurprd04.prod.outlook.com (20.177.35.214) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1339.21; Tue, 20 Nov 2018 09:26:37 +0000 Received: from AM6PR04MB5781.eurprd04.prod.outlook.com ([fe80::29b5:b3ed:3854:cf1c]) by AM6PR04MB5781.eurprd04.prod.outlook.com ([fe80::29b5:b3ed:3854:cf1c%4]) with mapi id 15.20.1339.026; Tue, 20 Nov 2018 09:26:37 +0000 From: "Z.q. Hou" To: "linux-pci@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "bhelgaas@google.com" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "l.subrahmanya@mobiveil.co.in" , "shawnguo@kernel.org" , Leo Li , "lorenzo.pieralisi@arm.com" , "catalin.marinas@arm.com" , "will.deacon@arm.com" CC: Mingkai Hu , "M.h. Lian" , Xiaowei Bao , "Z.q. Hou" Subject: [PATCHv2 10/25] PCI: mobiveil: fix the INTx process error Thread-Topic: [PATCHv2 10/25] PCI: mobiveil: fix the INTx process error Thread-Index: AQHUgLMjn4TF2XEFDkS2g0YPrTFmig== Date: Tue, 20 Nov 2018 09:26:37 +0000 Message-ID: <20181120092615.11680-11-Zhiqiang.Hou@nxp.com> References: <20181120092615.11680-1-Zhiqiang.Hou@nxp.com> In-Reply-To: <20181120092615.11680-1-Zhiqiang.Hou@nxp.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: HK2PR03CA0050.apcprd03.prod.outlook.com (2603:1096:202:17::20) To AM6PR04MB5781.eurprd04.prod.outlook.com (2603:10a6:20b:aa::16) authentication-results: spf=none (sender IP is ) smtp.mailfrom=zhiqiang.hou@nxp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [119.31.174.73] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; AM6PR04MB5269; 6:WHslZZm6LZmy4Wso0xh4MoJrcgs/sQr3OVNBxXTQ9RwtzdTcFHUsdyuRPIA0I3rAVzA7Hsp7DOTn2eWMucARDy2s94U+cbyiiHsDBhdc/yvf84BQ74T6xxqIsboqd/GdZv4jnyzE4Yxxr2JNJwIoH8IqJmTqRdNtz4Rs3byTUdcyOp3wTT8qqtqKzKYTVlDQ3mkyUrWK77Y6/2lF0Py9KkQhY6/RvBAkLXeCYusFS5PEN3z8tccmd0Khl1awdih5PSffi1GG+4xlr8bgc6wZ+7ocEFM+RrLiKRnaneayM6A5xkcS8R/nTM2FIPE49WpJlkNhxut5AkPoJIXllpr9QipbFho0LGK/7w5N46P8bUWPHH8p4dxgN51nfBIANcfESHsktyAavp9DSF+tt/F8bM4q4LfvsfQnv7NdN37VmcWEk54LzUKYFwTHmE2FHQHCEZyaik9c1zOTxP7/xcgMPQ==; 5:+dRr01V7TBlIlWvDiPhZq/jbJgqFE154U+LUyXv8Dzfj06x+2WFPtaR/l37mkcoaeTpMi2C44hAdWKEDbgheEIWM+51nZS9Ixac8Ye87IoaP26ddfonu35oHQV3ZRVTugq9Zh34Z5flGG+9IypRLd7q17LU2I8wNwopqZSb3t5U=; 7:7d5gDRjYBcun5G2eq6DnRHj1UmOQplMQB9cHVLzVzAHcAyXdGDMZI9T0otQ8BSNUpZ4O1ooQOAYuX55gq4SKFU481rPXuvd7c+RyaRbkcCXp7Km1vx7ch9nw0H8aO5BOb4ZZIktZZAR2q5R6IWHuIw== x-ms-office365-filtering-correlation-id: 9d8238e7-3aa1-40d4-6618-08d64eca4581 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390098)(7020095)(4652040)(8989299)(5600074)(711020)(4618075)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7153060)(7193020); SRVR:AM6PR04MB5269; x-ms-traffictypediagnostic: AM6PR04MB5269: x-microsoft-antispam-prvs: x-ms-exchange-senderadcheck: 1 x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(8211001083)(6040522)(2401047)(5005006)(8121501046)(3231442)(944501410)(52105112)(3002001)(10201501046)(93006095)(93001095)(6055026)(148016)(149066)(150057)(6041310)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123558120)(20161123564045)(20161123560045)(20161123562045)(201708071742011)(7699051)(76991095); SRVR:AM6PR04MB5269; BCL:0; PCL:0; RULEID:; SRVR:AM6PR04MB5269; x-forefront-prvs: 08626BE3A5 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(346002)(376002)(136003)(396003)(366004)(39860400002)(189003)(199004)(305945005)(7736002)(36756003)(5660300001)(7416002)(68736007)(2906002)(4326008)(8936002)(14454004)(256004)(54906003)(53936002)(6436002)(71200400001)(110136005)(71190400001)(6512007)(316002)(2616005)(476003)(446003)(11346002)(486006)(25786009)(2501003)(2201001)(86362001)(52116002)(76176011)(6506007)(102836004)(386003)(186003)(106356001)(26005)(2900100001)(81156014)(81166006)(105586002)(6486002)(8676002)(99286004)(66066001)(6116002)(3846002)(1076002)(478600001)(97736004)(921003)(1121003); DIR:OUT; SFP:1101; SCL:1; SRVR:AM6PR04MB5269; H:AM6PR04MB5781.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: W9kncstN0BEKoexRNbyTetZD5MBYZUljUjhqurZxgWkxZ6K6vwVvc5NMZw4zYIQl2VvwfJPWAY7wf/10rcBesCe2OXbEES5MVfu7Y0xKE5VmjbDvbsaQV5HA5FSU0Ov1XaJfdxAd+4y/YVG0FIOR7/7/j4tl87QaQgIw3MJxuV52ycx1rLJFgF2vWNqtYJab+A8JvCbuysTctb9t99gb+ICMoc8swXRtJkiLssg2Rk+zVy0O4BV0NGgj23SDCHGbv5ihIDBmCItYQz1F9Dpkg1hxG0BX/cgPPhFqlmc6sD2xCWCGJjlyoBMhfYp31GKtp+1xy9/wH474dLQs7DxhAm95ywtkZ/jI2/y1EaKn4p8= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 9d8238e7-3aa1-40d4-6618-08d64eca4581 X-MS-Exchange-CrossTenant-originalarrivaltime: 20 Nov 2018 09:26:37.8472 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR04MB5269 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Hou Zhiqiang In the loop block, there is not code change the loop key, this patch updated the loop key by re-read the INTx status register. This patch also change to clear the handled INTx status. Note: Need MV to test this fix. Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP driver") Signed-off-by: Hou Zhiqiang reviewed-by: Minghuan Lian --- V2: - Added fixes entry. drivers/pci/controller/pcie-mobiveil.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c index 4ba458474e42..78e575e71f4d 100644 --- a/drivers/pci/controller/pcie-mobiveil.c +++ b/drivers/pci/controller/pcie-mobiveil.c @@ -361,6 +361,7 @@ static void mobiveil_pcie_isr(struct irq_desc *desc) /* Handle INTx */ if (intr_status & PAB_INTP_INTX_MASK) { shifted_status = csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT); + shifted_status &= PAB_INTP_INTX_MASK; shifted_status >>= PAB_INTX_START; do { for_each_set_bit(bit, &shifted_status, PCI_NUM_INTX) { @@ -372,12 +373,16 @@ static void mobiveil_pcie_isr(struct irq_desc *desc) dev_err_ratelimited(dev, "unexpected IRQ, INT%d\n", bit); - /* clear interrupt */ - csr_writel(pcie, - shifted_status << PAB_INTX_START, + /* clear interrupt handled */ + csr_writel(pcie, 1 << (PAB_INTX_START + bit), PAB_INTP_AMBA_MISC_STAT); } - } while ((shifted_status >> PAB_INTX_START) != 0); + + shifted_status = csr_readl(pcie, + PAB_INTP_AMBA_MISC_STAT); + shifted_status &= PAB_INTP_INTX_MASK; + shifted_status >>= PAB_INTX_START; + } while (shifted_status != 0); } /* read extra MSI status register */ From patchwork Tue Nov 20 09:26:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Z.Q. Hou" X-Patchwork-Id: 1000342 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=nxp.com header.i=@nxp.com header.b="UI4Js3nf"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42zgMt1yllz9s8F for ; Tue, 20 Nov 2018 20:27:22 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727881AbeKTTy5 (ORCPT ); Tue, 20 Nov 2018 14:54:57 -0500 Received: from mail-eopbgr70045.outbound.protection.outlook.com ([40.107.7.45]:16489 "EHLO EUR04-HE1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727477AbeKTTy5 (ORCPT ); Tue, 20 Nov 2018 14:54:57 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=pCGh70nXCKmtSPXoh9FE7myom0psJbNczh4S1/7vMso=; b=UI4Js3nf1LJO0LLTMa6Jg9E+9X1oKzDzfrswSHVyW4cFJKGEGJb3/v8lJz7srP5yuv3qvqkmFnjsQVez87+uJyqi8e9w+L7Tr97icY6rLlfNpYHQpD7LD7CjBKbdD64TjgCtxplCP/2/cYy4WdPnjkrgHFP28M3nYhwq/GFPPkg= Received: from AM6PR04MB5781.eurprd04.prod.outlook.com (20.179.2.80) by AM6PR04MB5269.eurprd04.prod.outlook.com (20.177.35.214) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1339.21; Tue, 20 Nov 2018 09:26:44 +0000 Received: from AM6PR04MB5781.eurprd04.prod.outlook.com ([fe80::29b5:b3ed:3854:cf1c]) by AM6PR04MB5781.eurprd04.prod.outlook.com ([fe80::29b5:b3ed:3854:cf1c%4]) with mapi id 15.20.1339.026; Tue, 20 Nov 2018 09:26:44 +0000 From: "Z.q. Hou" To: "linux-pci@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "bhelgaas@google.com" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "l.subrahmanya@mobiveil.co.in" , "shawnguo@kernel.org" , Leo Li , "lorenzo.pieralisi@arm.com" , "catalin.marinas@arm.com" , "will.deacon@arm.com" CC: Mingkai Hu , "M.h. Lian" , Xiaowei Bao , "Z.q. Hou" Subject: [PATCHv2 11/25] PCI: mobiveil: only fix up the Class Code field Thread-Topic: [PATCHv2 11/25] PCI: mobiveil: only fix up the Class Code field Thread-Index: AQHUgLMmM+e4UAw2tUizP6EGfGXfLA== Date: Tue, 20 Nov 2018 09:26:44 +0000 Message-ID: <20181120092615.11680-12-Zhiqiang.Hou@nxp.com> References: <20181120092615.11680-1-Zhiqiang.Hou@nxp.com> In-Reply-To: <20181120092615.11680-1-Zhiqiang.Hou@nxp.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: HK2PR03CA0050.apcprd03.prod.outlook.com (2603:1096:202:17::20) To AM6PR04MB5781.eurprd04.prod.outlook.com (2603:10a6:20b:aa::16) authentication-results: spf=none (sender IP is ) smtp.mailfrom=zhiqiang.hou@nxp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [119.31.174.73] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; AM6PR04MB5269; 6:S7ZveHlWPmiJODZfx/EGQBWrx5L7lkAo9O3Y15n9si916rfis/N1xiWEymasiP0oE1RweLbpbhrSDm/RrlZ8qPuLBw1ZFVD3FwhtucjUSMrRmfQM2CHl+QTP0Mr+u+LWXo7l42ap/4ZZ+wRpCk2Gs8Z6O9xGI+ZdPhazoKHRcZNY5jpW1PytQi9Nfvb5eUcmmC3H7jd5F8OwbmkyMqvt/5xbn7nBo+ZWkKVEIY3geBLZDMv/kAiOto1N0j34k0Y8ML1HzCP/Ezt7v3BIVgN2IiHOJE4pOLY5I2v7gD2l3Q3D7ZEaMNqv31WxQbCNYjo07SmBiYCIaL0AyA2KB0c0LV8tODU1Ai49fCx4nQ+PbnANja/nkikTsjGELMvDd4qPELVs5bcsMTA7OnftQiSqmLq0tZhTU7xXNYrjI++XxmfUmOoiCBs9wbUKf5tq3E8Pv26atiIbvYzEZO2hQ6bBCw==; 5:GgwQ5mcn4R7pWey8OTGg0xGlWsWtBaLEckdXJTf4G+s6xawZxBqK6S1XqHM1olZpkExeWMvR6S59czr73q2ymfljFWMQ/4RtdEObLIX7O4cZGpZ6H3IQc5b39vGZr8RyaQtd1z62CidrbSaNAZYNFDVoogymksdVlscaop1knHc=; 7:aUMxZ6fE6eLN1D3hyy5J2jLoAY7GbfCnrtxX9+7Fb0KCeX/jIYOTypY4FkmqIutbJ6YASVt+DgiJ2TjEnupIbtAcr9tgmHPm/D33TaQgtZM1UNWGrUy/YRRg70WHgYv4p16ERrNZNs/IDoGchyO3LA== x-ms-office365-filtering-correlation-id: f905b938-8619-4e43-db5c-08d64eca4920 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390098)(7020095)(4652040)(8989299)(5600074)(711020)(4618075)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7153060)(7193020); SRVR:AM6PR04MB5269; x-ms-traffictypediagnostic: AM6PR04MB5269: x-microsoft-antispam-prvs: x-ms-exchange-senderadcheck: 1 x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(8211001083)(6040522)(2401047)(5005006)(8121501046)(3231442)(944501410)(52105112)(3002001)(10201501046)(93006095)(93001095)(6055026)(148016)(149066)(150057)(6041310)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123558120)(20161123564045)(20161123560045)(20161123562045)(201708071742011)(7699051)(76991095); SRVR:AM6PR04MB5269; BCL:0; PCL:0; RULEID:; SRVR:AM6PR04MB5269; x-forefront-prvs: 08626BE3A5 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(346002)(376002)(136003)(396003)(366004)(39860400002)(189003)(199004)(305945005)(7736002)(36756003)(5660300001)(7416002)(68736007)(2906002)(4326008)(8936002)(14454004)(256004)(54906003)(53936002)(6436002)(71200400001)(110136005)(71190400001)(6512007)(316002)(2616005)(476003)(446003)(11346002)(486006)(25786009)(2501003)(2201001)(86362001)(52116002)(76176011)(6506007)(102836004)(386003)(186003)(106356001)(26005)(2900100001)(81156014)(81166006)(105586002)(6486002)(8676002)(99286004)(66066001)(6116002)(3846002)(1076002)(478600001)(97736004)(921003)(1121003); DIR:OUT; SFP:1101; SCL:1; SRVR:AM6PR04MB5269; H:AM6PR04MB5781.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: Vnir+2ZcgJ4B/4bq0bXcwJGRHW6L27VQ3MEOCYZXiaO2gYBN5bVnH1QxVu+OgFy7a846zn4RYkkModRheUeV5pdA8jTjKpNgyDhxvar82qW0H/vbMM4lM9pnEtg/hHiiKqexThQbesjWWdQjw7FjPWeaMDUizobq+AtfKrVnQv5Yg76/U7r2smSTGa4/BtuM6SS2SXN70exeH++0Xb+6OWicNBoPPPF8pj6JJW1PSHritFdPVvBHwTtDFbIdKJHFqdT/kMRLE4J3PdLeQ2Q91aCqd1ONrBGrBfdPfXaBWyMrEYwF4tX/AwsGOKPlcb8PHhdo89GlupduxuZ2KiIJEDhDHG+qUvkTdNUt0MwkyPY= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: f905b938-8619-4e43-db5c-08d64eca4920 X-MS-Exchange-CrossTenant-originalarrivaltime: 20 Nov 2018 09:26:44.1754 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR04MB5269 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Hou Zhiqiang Fix up the Class Code to PCI bridge, do not change the Revision ID. And move the fixup to mobiveil_host_init function. Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP driver") Signed-off-by: Hou Zhiqiang reviewed-by: Minghuan Lian --- V2: - Added fixes entry. drivers/pci/controller/pcie-mobiveil.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c index 78e575e71f4d..8eee1ab7ee24 100644 --- a/drivers/pci/controller/pcie-mobiveil.c +++ b/drivers/pci/controller/pcie-mobiveil.c @@ -653,6 +653,12 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie) type, resource_size(win->res)); } + /* fixup for PCIe class register */ + value = csr_readl(pcie, PAB_INTP_AXI_PIO_CLASS); + value &= 0xff; + value |= (PCI_CLASS_BRIDGE_PCI << 16); + csr_writel(pcie, value, PAB_INTP_AXI_PIO_CLASS); + /* setup MSI hardware registers */ mobiveil_pcie_enable_msi(pcie); @@ -896,9 +902,6 @@ static int mobiveil_pcie_probe(struct platform_device *pdev) goto error; } - /* fixup for PCIe class register */ - csr_writel(pcie, 0x060402ab, PAB_INTP_AXI_PIO_CLASS); - /* initialize the IRQ domains */ ret = mobiveil_pcie_init_irq_domain(pcie); if (ret) { From patchwork Tue Nov 20 09:26:50 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Z.Q. Hou" X-Patchwork-Id: 1000337 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=nxp.com header.i=@nxp.com header.b="ExBx9BV1"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42zgMP0tCxz9s1x for ; Tue, 20 Nov 2018 20:26:57 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727974AbeKTTzD (ORCPT ); Tue, 20 Nov 2018 14:55:03 -0500 Received: from mail-eopbgr80073.outbound.protection.outlook.com ([40.107.8.73]:11604 "EHLO EUR04-VI1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727477AbeKTTzC (ORCPT ); Tue, 20 Nov 2018 14:55:02 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=IjcSXw7tHNyA93XfqGn65Uz6dkglRFYQIp/PtgEylDk=; b=ExBx9BV1Bkf8QGnMxXpaEkmrEejZdb6h0LSI6gdJDP53aL+22L6BexzY+rkCwi2Tzt8GIiP7s7Bc+6yvwcTn2JlqJjrkkitM3SxVBibUZp4p8RksuIOab89BwHJOiPHT1cJpElmRsw0eZs+G/5IsOLLKLUW6Z5xLN1qZDoKzVXE= Received: from AM6PR04MB5781.eurprd04.prod.outlook.com (20.179.2.80) by AM6PR04MB5269.eurprd04.prod.outlook.com (20.177.35.214) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1339.21; Tue, 20 Nov 2018 09:26:50 +0000 Received: from AM6PR04MB5781.eurprd04.prod.outlook.com ([fe80::29b5:b3ed:3854:cf1c]) by AM6PR04MB5781.eurprd04.prod.outlook.com ([fe80::29b5:b3ed:3854:cf1c%4]) with mapi id 15.20.1339.026; Tue, 20 Nov 2018 09:26:50 +0000 From: "Z.q. Hou" To: "linux-pci@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "bhelgaas@google.com" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "l.subrahmanya@mobiveil.co.in" , "shawnguo@kernel.org" , Leo Li , "lorenzo.pieralisi@arm.com" , "catalin.marinas@arm.com" , "will.deacon@arm.com" CC: Mingkai Hu , "M.h. Lian" , Xiaowei Bao , "Z.q. Hou" Subject: [PATCHv2 12/25] PCI: mobiveil: move out the link up waiting from mobiveil_host_init Thread-Topic: [PATCHv2 12/25] PCI: mobiveil: move out the link up waiting from mobiveil_host_init Thread-Index: AQHUgLMquEOAt+rjOkCT2d13q//Fpw== Date: Tue, 20 Nov 2018 09:26:50 +0000 Message-ID: <20181120092615.11680-13-Zhiqiang.Hou@nxp.com> References: <20181120092615.11680-1-Zhiqiang.Hou@nxp.com> In-Reply-To: <20181120092615.11680-1-Zhiqiang.Hou@nxp.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: HK2PR03CA0050.apcprd03.prod.outlook.com (2603:1096:202:17::20) To AM6PR04MB5781.eurprd04.prod.outlook.com (2603:10a6:20b:aa::16) authentication-results: spf=none (sender IP is ) smtp.mailfrom=zhiqiang.hou@nxp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [119.31.174.73] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; AM6PR04MB5269; 6:AWQ1sYEk2nm5xqfqW30Ocpj2Fbkl4++aKn1ilMFY44NCdj5BUYCe+a8eAD8e6HmqPLB3OWG5R66/e4NngdOrisLt+uIzVyFwg94XVH9i9AzE8VCb2ndFQBsD9QL6h0GvzuZJqDPDNyJAI1PCzWlmQ+toFKDMZUABDKFxnTqALrNTxk7OWgOL8todNxow4ZT9iCr3zFCHMcAxe0aT0+37hZtxOje1HVPjrfKXblocA95SgyazkmZrZyyYi+dp+xD1Nbw4S2lHRfXYytbW9Za4eE0U/0twyygSgyL7ZUUYMxoJR1ma4GzMnK64fCE2f1o4X+yVL691JahddKCr6KrCILwkT0InnJT39817Fu4OHFMVDOCAmz5gC5yCQUsTVXWfNDHyoSynnlZ8QQmOXkpnB1EF0NNgpmcCmGTNTmdy83JxMnm+6vyv4T+VtEfcGllRZKXVphI4VZyQ/H0u8FtuCw==; 5:0zYA2CLN12GAnIWzPzs2Imo6umMMsYt9wuknQCMJtdc6PxJ16q5yQ8ru7tAA/Y+YiWf7zIzNCtaPDOugGhJd6NXA5GRlDm+4qSZ3ogGXV59lvCqpjMc8TcrWqnuEl+uKhwOMlcniYN1NQyxcUMAlR0fpySz4EaHps3eT87AmKog=; 7:GGDFdKhoVqw1r5mwx1d35Keo0qeeYWMw1zwiwgTsP2JNYdbmlZWipFycRX/kZWF3V3446+HHYOFga6F1Wog3VYsJIRz5v7CKGt+9EKPkNeUn1Fe0zkGG+C/J1rlq/lu/wQHNTYD3fJOfd791e4pBOQ== x-ms-office365-filtering-correlation-id: 9ddd7237-d838-483c-13fe-08d64eca4ce4 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390098)(7020095)(4652040)(8989299)(5600074)(711020)(4618075)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7153060)(7193020); SRVR:AM6PR04MB5269; x-ms-traffictypediagnostic: AM6PR04MB5269: x-microsoft-antispam-prvs: x-ms-exchange-senderadcheck: 1 x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(8211001083)(6040522)(2401047)(5005006)(8121501046)(3231442)(944501410)(52105112)(3002001)(10201501046)(93006095)(93001095)(6055026)(148016)(149066)(150057)(6041310)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123558120)(20161123564045)(20161123560045)(20161123562045)(201708071742011)(7699051)(76991095); SRVR:AM6PR04MB5269; BCL:0; PCL:0; RULEID:; SRVR:AM6PR04MB5269; x-forefront-prvs: 08626BE3A5 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(346002)(376002)(136003)(396003)(366004)(39860400002)(189003)(199004)(305945005)(7736002)(36756003)(5660300001)(7416002)(68736007)(2906002)(4326008)(8936002)(14454004)(256004)(54906003)(53936002)(6436002)(71200400001)(110136005)(71190400001)(6512007)(316002)(2616005)(476003)(446003)(11346002)(486006)(25786009)(2501003)(2201001)(86362001)(52116002)(76176011)(6506007)(102836004)(386003)(186003)(106356001)(26005)(2900100001)(81156014)(81166006)(105586002)(6486002)(8676002)(99286004)(66066001)(6116002)(3846002)(1076002)(478600001)(97736004)(921003)(1121003); DIR:OUT; SFP:1101; SCL:1; SRVR:AM6PR04MB5269; H:AM6PR04MB5781.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: 5Sg+Aqf1ka9dH012De7b6HhvhDgBxwHr5Yun5/6RW6zftUjFYOQbODpPKmt+cLdwOqsF5DWXa2XzdWyuYf9nTe+ZquTVgPIcaB9HxHIpS90mq55Zc5zfOduFF8B5tjwciJvpJOj3PGSYIZNqILamkLU7w+c44K+Q3nqBYoBA2S0uy98wb62hFSnCRb8jCXAWlGL3h7JK3ghfYWf6sBKQJ2lR/DryFjMTgNQDIG07PWtFZjo0kEO01512SsomLalsgcL6QE2MLXtGMC/rZzsUP69oUXnXie66DNaUgSyK4nDPbaNsc53RO1XBZktz+no940LZPXeI+krApvJShCt6iDRT4b7Dtu/Pcysd/ein5gQ= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 9ddd7237-d838-483c-13fe-08d64eca4ce4 X-MS-Exchange-CrossTenant-originalarrivaltime: 20 Nov 2018 09:26:50.2379 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR04MB5269 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Hou Zhiqiang Host initial sequence does not depend on PCIe link up, so move it to the place just before the enumeration. Signed-off-by: Hou Zhiqiang reviewed-by: Minghuan Lian --- V2: - no change drivers/pci/controller/pcie-mobiveil.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c index 8eee1ab7ee24..c2848c22b466 100644 --- a/drivers/pci/controller/pcie-mobiveil.c +++ b/drivers/pci/controller/pcie-mobiveil.c @@ -582,15 +582,8 @@ static void mobiveil_pcie_enable_msi(struct mobiveil_pcie *pcie) static int mobiveil_host_init(struct mobiveil_pcie *pcie) { u32 value, pab_ctrl, type; - int err; struct resource_entry *win; - err = mobiveil_bringup_link(pcie); - if (err) { - dev_info(&pcie->pdev->dev, "link bring-up failed\n"); - return err; - } - /* * program Bus Master Enable Bit in Command Register in PAB Config * Space @@ -662,7 +655,7 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie) /* setup MSI hardware registers */ mobiveil_pcie_enable_msi(pcie); - return err; + return 0; } static void mobiveil_mask_intx_irq(struct irq_data *data) @@ -922,6 +915,12 @@ static int mobiveil_pcie_probe(struct platform_device *pdev) bridge->map_irq = of_irq_parse_and_map_pci; bridge->swizzle_irq = pci_common_swizzle; + ret = mobiveil_bringup_link(pcie); + if (ret) { + dev_info(dev, "link bring-up failed\n"); + goto error; + } + /* setup the kernel resources for the newly added PCIe root bus */ ret = pci_scan_root_bus_bridge(bridge); if (ret) From patchwork Tue Nov 20 09:26:56 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Z.Q. Hou" X-Patchwork-Id: 1000338 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=nxp.com header.i=@nxp.com header.b="ThtbnWEx"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42zgMT4h4Cz9s8F for ; Tue, 20 Nov 2018 20:27:01 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727435AbeKTTzJ (ORCPT ); Tue, 20 Nov 2018 14:55:09 -0500 Received: from mail-eopbgr00077.outbound.protection.outlook.com ([40.107.0.77]:37792 "EHLO EUR02-AM5-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727166AbeKTTzI (ORCPT ); Tue, 20 Nov 2018 14:55:08 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=yHrphN+K8xYQ7GQ8b/pdf5d/iDyYtsAdae/rfUzCQOM=; b=ThtbnWExzj8Ug4PLoG38BUgXRLWcNt8StcroEmTr/AEpP0zD/fikK1Acmqk0bc7wemFKXabADlw6UdjbZEwQgYyLn7vqhlKEUDxRmwmSBbXkahQrec9Zdf7PqutJ8WRa+BA8A+V0kUvt9BlhsH1El+dww4PnYwpSsMYJQf+biro= Received: from AM6PR04MB5781.eurprd04.prod.outlook.com (20.179.2.80) by AM6PR04MB5269.eurprd04.prod.outlook.com (20.177.35.214) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1339.21; Tue, 20 Nov 2018 09:26:56 +0000 Received: from AM6PR04MB5781.eurprd04.prod.outlook.com ([fe80::29b5:b3ed:3854:cf1c]) by AM6PR04MB5781.eurprd04.prod.outlook.com ([fe80::29b5:b3ed:3854:cf1c%4]) with mapi id 15.20.1339.026; Tue, 20 Nov 2018 09:26:56 +0000 From: "Z.q. Hou" To: "linux-pci@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "bhelgaas@google.com" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "l.subrahmanya@mobiveil.co.in" , "shawnguo@kernel.org" , Leo Li , "lorenzo.pieralisi@arm.com" , "catalin.marinas@arm.com" , "will.deacon@arm.com" CC: Mingkai Hu , "M.h. Lian" , Xiaowei Bao , "Z.q. Hou" Subject: [PATCHv2 13/25] PCI: mobiveil: move irq chained handler setup out of DT parse Thread-Topic: [PATCHv2 13/25] PCI: mobiveil: move irq chained handler setup out of DT parse Thread-Index: AQHUgLMux9U/dwM62kiiFtDOow1Ukg== Date: Tue, 20 Nov 2018 09:26:56 +0000 Message-ID: <20181120092615.11680-14-Zhiqiang.Hou@nxp.com> References: <20181120092615.11680-1-Zhiqiang.Hou@nxp.com> In-Reply-To: <20181120092615.11680-1-Zhiqiang.Hou@nxp.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: HK2PR03CA0050.apcprd03.prod.outlook.com (2603:1096:202:17::20) To AM6PR04MB5781.eurprd04.prod.outlook.com (2603:10a6:20b:aa::16) authentication-results: spf=none (sender IP is ) smtp.mailfrom=zhiqiang.hou@nxp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [119.31.174.73] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; AM6PR04MB5269; 6:wDcIPEI+BvrfCnRubcXXDFqzYxJqHPw+g4yNFYaDUcSnGV1SKXQlgSY1pkBIVPrWVs1BxKJVSSWtI7jpZeI3vt5iSsALNRjnln/VLLwvCDWF2mllOFBUx4jmVRl3P4BpdscmXDBi0ExMXgkX+6PLDuuEs0KgkbhLynfmRgU3iCunQTUFTcMaahRt32+EZzufds3q4BJ6UPm82e3ymn6E0N5nnJyhBkG33agYnSyyZMMQ+HnisfvKaopZmapYOB+5PqOGNlBpqXLKVLHtwa+NNXVJfIOlKuGa5o4+ERzXmL0J5U8z5DdMcdi/soaGlDMKtvoxS6c6n76Id08aN4yDThYQNln0RS504kQiVKFjsCa7ovOkaXYvOq97a+8Fw5mRC3lanoLa4mkTtULMjbmwWW/kTViAniXYqhU1fqmaTdan0FrqY2q/ya76i1GQRpX6oKPD/Hs2qF7n16xpM9ZYng==; 5:NrJRMOdBRH66cD9H5syOgA5WN1/xr9A0qCf3+1xpfkrRE5zCZr/ScearuNp9LduWSllIToa0/28tqIVjCmsZnDjhX3f+37GqBN+lPjiPpe/9Sb5i7+WZTv6Jq9x4MJKnvIH5cP4voso4vUMq7JiOlRk+xnWkMsKfo0x7fm7U5f8=; 7:m/RsDQjdddVWocmUFZ0VW/DvoxFtXmG7TvZnEmwdl6VGFHyoz3OEAob1b679NoyyMco0jRklJqk7roJkxBMOuY31O9xrzmvXhyl2DPY+LpebXLAUBYJuUULodnug4whaxAKMCN5hEcXnD2tm/J2+vg== x-ms-office365-filtering-correlation-id: 7659cf1c-7627-4218-26ba-08d64eca5081 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390098)(7020095)(4652040)(8989299)(5600074)(711020)(4618075)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7153060)(7193020); SRVR:AM6PR04MB5269; x-ms-traffictypediagnostic: AM6PR04MB5269: x-microsoft-antispam-prvs: x-ms-exchange-senderadcheck: 1 x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(8211001083)(6040522)(2401047)(5005006)(8121501046)(3231442)(944501410)(52105112)(3002001)(10201501046)(93006095)(93001095)(6055026)(148016)(149066)(150057)(6041310)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123558120)(20161123564045)(20161123560045)(20161123562045)(201708071742011)(7699051)(76991095); SRVR:AM6PR04MB5269; BCL:0; PCL:0; RULEID:; SRVR:AM6PR04MB5269; x-forefront-prvs: 08626BE3A5 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(346002)(376002)(136003)(396003)(366004)(39860400002)(189003)(199004)(305945005)(7736002)(36756003)(5660300001)(7416002)(68736007)(2906002)(4326008)(8936002)(14454004)(256004)(54906003)(14444005)(53936002)(6436002)(71200400001)(110136005)(71190400001)(6512007)(316002)(2616005)(476003)(446003)(11346002)(486006)(25786009)(2501003)(2201001)(86362001)(52116002)(76176011)(6506007)(102836004)(386003)(186003)(106356001)(26005)(2900100001)(81156014)(81166006)(105586002)(6486002)(8676002)(99286004)(66066001)(6116002)(3846002)(1076002)(478600001)(97736004)(921003)(1121003); DIR:OUT; SFP:1101; SCL:1; SRVR:AM6PR04MB5269; H:AM6PR04MB5781.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: RpgzmGALt1n/vkzOwwCZLig75k4L2+bnmif/Mi2Fsa0I2sR86qVjqhugZtPlAb40fiU3M1uaDZcQBgSx6OwieLT4uGv6czliVAZwpQe4tzaIsupqsvnoZSPmvHhui6zQW/VjaQKXH9kcvcNPcw+r0I6Ey2z4+5+L6Nu+9+6tARuTxP5tzZhukp//SUigirrEG7TNgjDNNAm24L0pwmKzp26rl6YfZlEYYGOep9ye2s7CupOWoO7NJML5uaGkb7o+NjAIlB9ahGFPLkX1caYKS5MmNDj/6LQ89Y3KU0LhzVW1AQSg7sWVixhKcG35KfSCFUSuW5rRrNB/0YiKK3DXIFdCwZQxFMhx+5wAjEyS8Ks= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 7659cf1c-7627-4218-26ba-08d64eca5081 X-MS-Exchange-CrossTenant-originalarrivaltime: 20 Nov 2018 09:26:56.4880 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR04MB5269 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Hou Zhiqiang Move irq_set_chained_handler_and_data() out of DT parse function. Signed-off-by: Hou Zhiqiang reviewed-by: Minghuan Lian --- V2: - no change drivers/pci/controller/pcie-mobiveil.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c index c2848c22b466..db7ecb021c63 100644 --- a/drivers/pci/controller/pcie-mobiveil.c +++ b/drivers/pci/controller/pcie-mobiveil.c @@ -460,8 +460,6 @@ static int mobiveil_pcie_parse_dt(struct mobiveil_pcie *pcie) return -ENODEV; } - irq_set_chained_handler_and_data(pcie->irq, mobiveil_pcie_isr, pcie); - return 0; } @@ -902,6 +900,8 @@ static int mobiveil_pcie_probe(struct platform_device *pdev) goto error; } + irq_set_chained_handler_and_data(pcie->irq, mobiveil_pcie_isr, pcie); + ret = devm_request_pci_bus_resources(dev, &pcie->resources); if (ret) goto error; From patchwork Tue Nov 20 09:27:02 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Z.Q. Hou" X-Patchwork-Id: 1000339 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=nxp.com header.i=@nxp.com header.b="GzubTKzn"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42zgMl0g9Zz9s3l for ; Tue, 20 Nov 2018 20:27:15 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727500AbeKTTzO (ORCPT ); Tue, 20 Nov 2018 14:55:14 -0500 Received: from mail-eopbgr00074.outbound.protection.outlook.com ([40.107.0.74]:17696 "EHLO EUR02-AM5-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727166AbeKTTzO (ORCPT ); Tue, 20 Nov 2018 14:55:14 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Z1T5BV36agyfCDR1ehoCpE1ivcDfB/dlzT8GWZ0qN8c=; b=GzubTKznkLxED5rys5q34lkoCZAOPyuNae6bRSAZxQ7+XkpUCw3GXZEUF4m+DIpb2ceIeVaaawhzS4L158Y0RicfMB+8CXjERFiPgPFV3RG3rS8gBqEqfaKbGt1mb7kHAsfTsZtX5zEXsQ3OqbVui7Q2uQ4rTvdK8SRmjEkKmn4= Received: from AM6PR04MB5781.eurprd04.prod.outlook.com (20.179.2.80) by AM6PR04MB5269.eurprd04.prod.outlook.com (20.177.35.214) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1339.21; Tue, 20 Nov 2018 09:27:02 +0000 Received: from AM6PR04MB5781.eurprd04.prod.outlook.com ([fe80::29b5:b3ed:3854:cf1c]) by AM6PR04MB5781.eurprd04.prod.outlook.com ([fe80::29b5:b3ed:3854:cf1c%4]) with mapi id 15.20.1339.026; Tue, 20 Nov 2018 09:27:02 +0000 From: "Z.q. Hou" To: "linux-pci@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "bhelgaas@google.com" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "l.subrahmanya@mobiveil.co.in" , "shawnguo@kernel.org" , Leo Li , "lorenzo.pieralisi@arm.com" , "catalin.marinas@arm.com" , "will.deacon@arm.com" CC: Mingkai Hu , "M.h. Lian" , Xiaowei Bao , "Z.q. Hou" Subject: [PATCHv2 14/25] PCI: mobiveil: initialize Primary/Secondary/Subordinate bus number Thread-Topic: [PATCHv2 14/25] PCI: mobiveil: initialize Primary/Secondary/Subordinate bus number Thread-Index: AQHUgLMx5aBe4vIHuE218OKNVbDjcA== Date: Tue, 20 Nov 2018 09:27:02 +0000 Message-ID: <20181120092615.11680-15-Zhiqiang.Hou@nxp.com> References: <20181120092615.11680-1-Zhiqiang.Hou@nxp.com> In-Reply-To: <20181120092615.11680-1-Zhiqiang.Hou@nxp.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: HK2PR03CA0050.apcprd03.prod.outlook.com (2603:1096:202:17::20) To AM6PR04MB5781.eurprd04.prod.outlook.com (2603:10a6:20b:aa::16) authentication-results: spf=none (sender IP is ) smtp.mailfrom=zhiqiang.hou@nxp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [119.31.174.73] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; AM6PR04MB5269; 6:c3uK7t9w3TqvO0zsskYV0oQPF1Ecw0nfX2+d10VrfQMASQM8OPAmxj4fTTAZ2CEAf9QqNi7TQu4aeHoSHUAFGt8qIMFBl2kHnXOB6gM9bv5q20yltbp7IWWsatAiAXH0QREuH0M7usMjmzFiq9/HOEliO772KHxbhKHGTGNPJCaWGML9NCwcjFA9Odjw2Sd2L0xVRNoSNr2OwH5mQm9KQnTV49a9iawg3+8fPI3RMYjiPyPiNDkLVvXQv/4P2cEcx1JSbaFTuoqTamyMru9Il3Z8hgz8ZPZPIEiIJxQKn2gem4hQ28eXe7Dyz9jl+++Uofsod1uEq30GJXSO/4duTlwV6luAgkj7pMKOKZDslpEj10sVRD954tEQBVxZW5UpdUPUYZl2JRkhv4jKfoDAH9KgKiL7jXdbqeWUsd3FRPQ4cT4qAylS6XJBkzjeHo9z7ZMHNT/r9elXaVUzbHnXpg==; 5:95pdw1nEMrkHMggTIubzcrzZzhmtrirJQzBFc1bGD7nc3TEUmufrh8JjWWlHezVC0EM+II++pGzMNKiwf6plUPUb3Z70Mzmc4gbGTNCZqVfr2F1ExsHxDL+OybJG5lPpjRxFCRzO83otCD3Wbzfpy+3OtLj9MFXotp8ksjP+qKE=; 7:p6oJn3UI2DFD3+ZnOCfC9H0PjoxGNFhK3Yge54ab1ehF1YeyVOES1cmfx1E5VCV9/qobMazFqtXMiYXJYTBaWHbBQtYNgwL5NcNpza0U0/qE4tzUb/Ewoih+fM6lG3x5bu+TvN2E8oaxzABGLGo58A== x-ms-office365-filtering-correlation-id: 012d7905-628b-4b01-d5f6-08d64eca543a x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390098)(7020095)(4652040)(8989299)(5600074)(711020)(4618075)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7153060)(7193020); SRVR:AM6PR04MB5269; x-ms-traffictypediagnostic: AM6PR04MB5269: x-microsoft-antispam-prvs: x-ms-exchange-senderadcheck: 1 x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(8211001083)(6040522)(2401047)(5005006)(8121501046)(3231442)(944501410)(52105112)(3002001)(10201501046)(93006095)(93001095)(6055026)(148016)(149066)(150057)(6041310)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123558120)(20161123564045)(20161123560045)(20161123562045)(201708071742011)(7699051)(76991095); SRVR:AM6PR04MB5269; BCL:0; PCL:0; RULEID:; SRVR:AM6PR04MB5269; x-forefront-prvs: 08626BE3A5 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(346002)(376002)(136003)(396003)(366004)(39860400002)(189003)(199004)(305945005)(7736002)(36756003)(5660300001)(7416002)(68736007)(2906002)(4326008)(8936002)(14454004)(256004)(54906003)(53936002)(6436002)(71200400001)(110136005)(71190400001)(6512007)(316002)(2616005)(476003)(446003)(11346002)(486006)(25786009)(2501003)(2201001)(86362001)(52116002)(76176011)(6506007)(102836004)(386003)(186003)(106356001)(26005)(2900100001)(81156014)(81166006)(105586002)(6486002)(8676002)(99286004)(66066001)(6116002)(3846002)(1076002)(478600001)(97736004)(921003)(1121003); DIR:OUT; SFP:1101; SCL:1; SRVR:AM6PR04MB5269; H:AM6PR04MB5781.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: 8m6dpeExL1rjbYbxZ+ibatZBdkhFmhp8qsU8j4/FqojzI2DOwBHBlgrCXnwALaSe3ypLeOpX/ubaJWX+eRoLTmV5vjtUEtv7CktRPDgqgq3mOSiKUznjXkjkxzHXnQGtYFM5Cw6+pNBXN458TywTZ72v6KTzbBHndkD9Np+1GGMao4Xu1+I7CORk5E2VvoobGlWmskEO1+4+PHcClave0IItaJ9Sn5WPvDLMYz0jWEkHAkhs5G0dsGmaLxP/QLWNEKotOyzgu+lFFpfWmcqAoeJDXmIybGqafvqC7unKPZEB5V2s9Go+WCZ75KMJ14DdGwBtuiDE+e0qrMg6T/4p/mvYfejmcds/LqF3oNb0EYk= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 012d7905-628b-4b01-d5f6-08d64eca543a X-MS-Exchange-CrossTenant-originalarrivaltime: 20 Nov 2018 09:27:02.7225 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR04MB5269 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Hou Zhiqiang The reset value is all zero, so set a workable value for Primary, Secondary and Subordinate bus numbers. Signed-off-by: Hou Zhiqiang reviewed-by: Minghuan Lian reviewed-by: Minghuan Lian --- V2: - no change drivers/pci/controller/pcie-mobiveil.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c index db7ecb021c63..9210165fe8c0 100644 --- a/drivers/pci/controller/pcie-mobiveil.c +++ b/drivers/pci/controller/pcie-mobiveil.c @@ -582,6 +582,12 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie) u32 value, pab_ctrl, type; struct resource_entry *win; + /* setup bus numbers */ + value = csr_readl(pcie, PCI_PRIMARY_BUS); + value &= 0xff000000; + value |= 0x00ff0100; + csr_writel(pcie, value, PCI_PRIMARY_BUS); + /* * program Bus Master Enable Bit in Command Register in PAB Config * Space From patchwork Tue Nov 20 09:27:08 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Z.Q. Hou" X-Patchwork-Id: 1000340 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=nxp.com header.i=@nxp.com header.b="XPaaKFI2"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42zgMq62BHz9s8F for ; Tue, 20 Nov 2018 20:27:19 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727496AbeKTTzW (ORCPT ); Tue, 20 Nov 2018 14:55:22 -0500 Received: from mail-eopbgr70083.outbound.protection.outlook.com ([40.107.7.83]:29568 "EHLO EUR04-HE1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727166AbeKTTzV (ORCPT ); Tue, 20 Nov 2018 14:55:21 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ePwAFGVsVHvPO6KTDI1NHxc+DeJJ2cOiUT6B8wuQgBY=; b=XPaaKFI2ksHfY6yFcavIBQDjxdZzZhxMWeXUxHTVa4Pbm6iit7MLa/W1duaKLlu3g9Rhjyf5K0plEA2r4pxEhpL25rzmcnp9stLuBiumYccxGXaBgrqJQRSUwvPMeC05lyHLrI/yWQISTCdQxy2eNNt3Xc3kMHpKXfeXF1SLDHI= Received: from AM6PR04MB5781.eurprd04.prod.outlook.com (20.179.2.80) by AM6PR04MB5269.eurprd04.prod.outlook.com (20.177.35.214) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1339.21; Tue, 20 Nov 2018 09:27:09 +0000 Received: from AM6PR04MB5781.eurprd04.prod.outlook.com ([fe80::29b5:b3ed:3854:cf1c]) by AM6PR04MB5781.eurprd04.prod.outlook.com ([fe80::29b5:b3ed:3854:cf1c%4]) with mapi id 15.20.1339.026; Tue, 20 Nov 2018 09:27:09 +0000 From: "Z.q. Hou" To: "linux-pci@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "bhelgaas@google.com" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "l.subrahmanya@mobiveil.co.in" , "shawnguo@kernel.org" , Leo Li , "lorenzo.pieralisi@arm.com" , "catalin.marinas@arm.com" , "will.deacon@arm.com" CC: Mingkai Hu , "M.h. Lian" , Xiaowei Bao , "Z.q. Hou" Subject: [PATCHv2 15/25] dt-bindings: pci: mobiveil: change gpio_slave and apb_csr to optional Thread-Topic: [PATCHv2 15/25] dt-bindings: pci: mobiveil: change gpio_slave and apb_csr to optional Thread-Index: AQHUgLM1AcYaMXR/GE2OPnFnxNzh5w== Date: Tue, 20 Nov 2018 09:27:08 +0000 Message-ID: <20181120092615.11680-16-Zhiqiang.Hou@nxp.com> References: <20181120092615.11680-1-Zhiqiang.Hou@nxp.com> In-Reply-To: <20181120092615.11680-1-Zhiqiang.Hou@nxp.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: HK2PR03CA0050.apcprd03.prod.outlook.com (2603:1096:202:17::20) To AM6PR04MB5781.eurprd04.prod.outlook.com (2603:10a6:20b:aa::16) authentication-results: spf=none (sender IP is ) smtp.mailfrom=zhiqiang.hou@nxp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [119.31.174.73] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; AM6PR04MB5269; 6:JtaAMmW4X8RqcCxWDVZcz2ycan15HvhL4nYca6iVqUHk92KFN/ZCVJ/sa5UEzpCCckHLlUsnVxigOB20KNN3zFBWNjVNRYGQt8wcpt2YA7zhF9E75AJBXhRUzvOcc+pgl12cICvTTNzdbuIEdK9gnof0CcMjvPWQ0H9Sr2DL+inq8CfhrBcUJJq4NjCyQQm13dBI83kmW+ufuBThUkWzwqJl9oh0UUb1T0cKFQKAg7uxp18xxDHiehU4ScupVruC26ndBkHUomDyyOOwYfgXoxc7eJXVqff2siaM4jY1PsALhcE4yDulaxVLvzyF+tSY5F6uUA8d0AIneNGzpglRCrP9i2dgOqWBN1jC6k51kjoQw2wNSnT9TGIlT7yhBdNw7qKl4BJgphzk4FcR5+WVVS0Vg+wZw/U0SWCC+hO8PSuqvQITr8WJ6lPaBtjhGtKTLD7lf3kI8JaQ9Mt+MUf2aQ==; 5:tAYpgP2L7p3O5/pLgDGQTYMxRSxBT9yI4tXcOVASiyIult/TjAm+Ej5LNEwqCMoMHpSCopls6chyZtCX8U0uFLGaUcrqYrCRGyCq5vmVcRhKCXDFMjg8gMIRDdslqcET6Rn9TnRv4LhqvuxKe/yfsZNj7YmZxRxa0hr5zFAfxyI=; 7:bNQIvnLmRs4Lxhc4ESuaNQ3f2ueIDBJXOFez9iXiMTspZpvuml6BTJTkI0aOgxSHz7d6L3f/pONnlaEhPSAo79i1bdAl3vHr2zXxK2+3sTXOO2WTaRBCdWXR/m3+jlsWGLyXbE5AYNuoO5t7WrbjNQ== x-ms-office365-filtering-correlation-id: f7e9de60-7c56-48bc-8525-08d64eca57f4 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390098)(7020095)(4652040)(8989299)(5600074)(711020)(4618075)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7153060)(7193020); SRVR:AM6PR04MB5269; x-ms-traffictypediagnostic: AM6PR04MB5269: x-microsoft-antispam-prvs: x-ms-exchange-senderadcheck: 1 x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(8211001083)(6040522)(2401047)(5005006)(8121501046)(3231442)(944501410)(52105112)(3002001)(10201501046)(93006095)(93001095)(6055026)(148016)(149066)(150057)(6041310)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123558120)(20161123564045)(20161123560045)(20161123562045)(201708071742011)(7699051)(76991095); SRVR:AM6PR04MB5269; BCL:0; PCL:0; RULEID:; SRVR:AM6PR04MB5269; x-forefront-prvs: 08626BE3A5 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(346002)(376002)(136003)(396003)(366004)(39860400002)(189003)(199004)(305945005)(7736002)(36756003)(5660300001)(7416002)(68736007)(2906002)(4326008)(8936002)(14454004)(256004)(54906003)(53936002)(6436002)(71200400001)(110136005)(71190400001)(6512007)(316002)(2616005)(476003)(446003)(11346002)(486006)(25786009)(2501003)(2201001)(86362001)(52116002)(76176011)(6506007)(102836004)(386003)(186003)(106356001)(26005)(2900100001)(81156014)(81166006)(105586002)(6486002)(8676002)(99286004)(66066001)(6116002)(3846002)(1076002)(478600001)(97736004)(921003)(1121003); DIR:OUT; SFP:1101; SCL:1; SRVR:AM6PR04MB5269; H:AM6PR04MB5781.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: vgUOUSkBwDtLQkUuLSzpQW5nHtUst7YdTPvIL5siIz1kx2H8qbI1Lbjlc5EYWzXC8aokz6QfiyJ3Mo87osUV3wTPc/fDWeC5R2w+zKEKevQcfhOtZ/XxJnh16J7fuCSAqXt1U/nX5JSzj8z6axsfyb7QNN89Uu8QmoinC67Sj6vMBeXixsvmr2bruQbuY/g/Pkv7tgdYHtm4S00HJYNx4j8OUSookV8pnDSP3b9pkWZkQxsafxzgTbGXKxkIVSyRqEHzZ7atk3+zBR3fFBvR24xaPn2bH+MDjb/zu5x52U5jX4Z2VAI/lFyBcXToomRHtYrqcgoSNm1MX4q7Q54gLf/99BnzcRibJsNul3fA11Y= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: f7e9de60-7c56-48bc-8525-08d64eca57f4 X-MS-Exchange-CrossTenant-originalarrivaltime: 20 Nov 2018 09:27:09.0350 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR04MB5269 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Hou Zhiqiang Change the "gpio_slave" and "apb_csr" to optional, the "gpio_slave" is not used in current code, and "apb_csr" is not used by some platforms. Signed-off-by: Hou Zhiqiang Acked-by: Subrahmanya Lingappa Acked-by: Rob Herring reviewed-by: Minghuan Lian --- V2: - no change Documentation/devicetree/bindings/pci/mobiveil-pcie.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/mobiveil-pcie.txt b/Documentation/devicetree/bindings/pci/mobiveil-pcie.txt index a618d4787dd7..64156993e052 100644 --- a/Documentation/devicetree/bindings/pci/mobiveil-pcie.txt +++ b/Documentation/devicetree/bindings/pci/mobiveil-pcie.txt @@ -10,8 +10,10 @@ Required properties: interrupt source. The value must be 1. - compatible: Should contain "mbvl,gpex40-pcie" - reg: Should contain PCIe registers location and length + Mandatory: "config_axi_slave": PCIe controller registers "csr_axi_slave" : Bridge config registers + Optional: "gpio_slave" : GPIO registers to control slot power "apb_csr" : MSI registers From patchwork Tue Nov 20 09:27:15 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Z.Q. Hou" X-Patchwork-Id: 1000354 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=nxp.com header.i=@nxp.com header.b="Cgsgfm5G"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42zgPV1N45z9s1x for ; Tue, 20 Nov 2018 20:28:46 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727629AbeKTTzc (ORCPT ); Tue, 20 Nov 2018 14:55:32 -0500 Received: from mail-eopbgr70054.outbound.protection.outlook.com ([40.107.7.54]:64008 "EHLO EUR04-HE1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727166AbeKTTzb (ORCPT ); Tue, 20 Nov 2018 14:55:31 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=HofEKq9ZrIWmKq9VfbLtsg2FR6p6rHXjiuTp/sHTmeI=; b=Cgsgfm5GjiRhmZhSUgCOfdeRRQ+tLZuXKQUuaISn0YQJsctOy7s1Sga2S3PsMUbSUodQi74h/UduM3A9buTfj3mrPuMQR1DK2CcTw7swikZO3FX1b0O4OuWDtlIJlD4L5xl2BtQQ4CzlpsNYYZLep8j5yI0sUf/CBUEiL/D6k4M= Received: from AM6PR04MB5781.eurprd04.prod.outlook.com (20.179.2.80) by AM6PR04MB5269.eurprd04.prod.outlook.com (20.177.35.214) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1339.21; Tue, 20 Nov 2018 09:27:15 +0000 Received: from AM6PR04MB5781.eurprd04.prod.outlook.com ([fe80::29b5:b3ed:3854:cf1c]) by AM6PR04MB5781.eurprd04.prod.outlook.com ([fe80::29b5:b3ed:3854:cf1c%4]) with mapi id 15.20.1339.026; Tue, 20 Nov 2018 09:27:15 +0000 From: "Z.q. Hou" To: "linux-pci@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "bhelgaas@google.com" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "l.subrahmanya@mobiveil.co.in" , "shawnguo@kernel.org" , Leo Li , "lorenzo.pieralisi@arm.com" , "catalin.marinas@arm.com" , "will.deacon@arm.com" CC: Mingkai Hu , "M.h. Lian" , Xiaowei Bao , "Z.q. Hou" Subject: [PATCHv2 16/25] PCI: mobiveil: refactor Mobiveil PCIe Host Bridge IP driver Thread-Topic: [PATCHv2 16/25] PCI: mobiveil: refactor Mobiveil PCIe Host Bridge IP driver Thread-Index: AQHUgLM5VxJKmLTanke1a+Ns2blnaA== Date: Tue, 20 Nov 2018 09:27:15 +0000 Message-ID: <20181120092615.11680-17-Zhiqiang.Hou@nxp.com> References: <20181120092615.11680-1-Zhiqiang.Hou@nxp.com> In-Reply-To: <20181120092615.11680-1-Zhiqiang.Hou@nxp.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: HK2PR03CA0050.apcprd03.prod.outlook.com (2603:1096:202:17::20) To AM6PR04MB5781.eurprd04.prod.outlook.com (2603:10a6:20b:aa::16) authentication-results: spf=none (sender IP is ) smtp.mailfrom=zhiqiang.hou@nxp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [119.31.174.73] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; AM6PR04MB5269; 6:yag3sFlVxxtdc0J+PMjAPKTSzMYkLnXI0m09WqihRxskXZYe2HvgMa6BKBCDxm+t4uhVyhMq/5ALbmcrddfipNhS/R5Vo6knKcxI7ezqoe/1NVkj7Kef1lS2uzlac5BMtkEuFWYbtm493fBkFzfgO4UcGanoGIvCWyDAdcr9i1V8u/Wr4J9DDnZwz0vY1LQ2FxOVAHmPGHJJXVvRALjkIlqQwfmKNBuxI2SSFnAR1fQH+9094KkHEb6s7kiz4ylMJIjHWEJTafoOV0rnq2jf/Cq5eNKtqPJp+9qFQoL/8IpcbNf5ohNeNZhctcnK0H9EheWpKugqJ+JAKN9OyVqNEKEiG2Tm9y++/TRNEpdg4SJ6MHe7FgwXGiDWoFbIFhzipiK4M0E1DNk2ZlEGSvnmT+2fUtsZuC8OSMi14JTL5rBSlJVd3G6DyQPzuRvHpCtTXMFhd5xASbhIGlnpxeM+wg==; 5:nKQ7yotUAEh8FKVi/zHw+L5ho5QhTvd2AxabFBrXYeVU1fridslKxzwWChKrb9h/akVAH+4D6Fa0lt2AJKXic49CX+g+e83ss5ec60NOxHyttu6m4eGCfbcrx850QmL639V06nEWvCBkbWIleM2FguRIQZwDjVGSjBDKaAqY5g8=; 7:+ppcE/5XsuLvkcnvgVydbVAzqsy9hY2gQhVUFVlgz5s7stH5fsRZPAQSxOHzII8ZYZ96XVru6TUQtG/t9hgCBfzKkF99nSS49a2vjfvTv906PkhLXTNBW1vDWdQeHQtDdinj39aP7J9xZa8I0KAgyw== x-ms-office365-filtering-correlation-id: 130a748c-9d2d-42e6-f910-08d64eca5bb2 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390098)(7020095)(4652040)(8989299)(5600074)(711020)(4618075)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7153060)(7193020); SRVR:AM6PR04MB5269; x-ms-traffictypediagnostic: AM6PR04MB5269: x-microsoft-antispam-prvs: x-ms-exchange-senderadcheck: 1 x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(8211001083)(6040522)(2401047)(5005006)(8121501046)(3231442)(944501410)(52105112)(3002001)(10201501046)(93006095)(93001095)(6055026)(148016)(149066)(150057)(6041310)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123558120)(20161123564045)(20161123560045)(20161123562045)(201708071742011)(7699051)(76991095); SRVR:AM6PR04MB5269; BCL:0; PCL:0; RULEID:; SRVR:AM6PR04MB5269; x-forefront-prvs: 08626BE3A5 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(346002)(376002)(136003)(396003)(366004)(39860400002)(189003)(199004)(305945005)(7736002)(36756003)(5660300001)(7416002)(68736007)(2906002)(4326008)(8936002)(14454004)(5024004)(256004)(54906003)(14444005)(4744004)(53936002)(6436002)(71200400001)(110136005)(71190400001)(6512007)(53946003)(316002)(2616005)(476003)(446003)(11346002)(486006)(25786009)(2501003)(2201001)(86362001)(575784001)(52116002)(76176011)(6506007)(102836004)(386003)(186003)(106356001)(26005)(2900100001)(81156014)(81166006)(105586002)(6486002)(8676002)(99286004)(66066001)(6116002)(3846002)(1076002)(478600001)(97736004)(921003)(1121003)(579004)(569006); DIR:OUT; SFP:1101; SCL:1; SRVR:AM6PR04MB5269; H:AM6PR04MB5781.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: 6wjkim7BqN9zC6b/yHVcKce4BCf+Zyj1LK1OHbreAwjjul+z4MRyavj21meQWQW/ni+Iy5oUuPW3nyf3QdKHFHVlL5OyK5cIhwuXK+fn4AzGtuiPx6xLWwVFGHEw3JEAHvZUEhPDXLfYSDnY7sE5l/NqWCgiw3j6T05fd7WNxWk8tR8p5I1ufcG78OShPWQ15/o2olrFAU5O8t/xb49KlvvPUKrzO8cqnb/Zm2xokqk2HKP86ikRcppnTzabAiL7fUutBRMODmTXqlL/JM9qw0rlWMXKwA2fFayNA8vPM8KQrlj+3SG7IkVUIjjSn3xDExVR650Xv1CtD5cQgjcWitRWa+aT8pSpT36kWHIYrq0= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 130a748c-9d2d-42e6-f910-08d64eca5bb2 X-MS-Exchange-CrossTenant-originalarrivaltime: 20 Nov 2018 09:27:15.3007 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR04MB5269 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Hou Zhiqiang As the Mobiveil PCIe controller support RC&EP DAUL mode, and to make platforms which integrated the Mobiveil PCIe IP more easy to add their drivers, this patch moved the Mobiveil driver to a new directory 'drivers/pci/controller/mobiveil' and refactored it according to the abstraction of RC&EP (EP driver will be added later). Signed-off-by: Hou Zhiqiang reviewed-by: Minghuan Lian --- V2: - Move interrupts enabling to interrupt init function and revert to just enable INTX and MSI. MAINTAINERS | 2 +- drivers/pci/controller/Kconfig | 11 +- drivers/pci/controller/Makefile | 2 +- drivers/pci/controller/mobiveil/Kconfig | 24 + drivers/pci/controller/mobiveil/Makefile | 4 + .../pcie-mobiveil-host.c} | 528 +++--------------- .../controller/mobiveil/pcie-mobiveil-plat.c | 54 ++ .../pci/controller/mobiveil/pcie-mobiveil.c | 228 ++++++++ .../pci/controller/mobiveil/pcie-mobiveil.h | 187 +++++++ 9 files changed, 587 insertions(+), 453 deletions(-) create mode 100644 drivers/pci/controller/mobiveil/Kconfig create mode 100644 drivers/pci/controller/mobiveil/Makefile rename drivers/pci/controller/{pcie-mobiveil.c => mobiveil/pcie-mobiveil-host.c} (55%) create mode 100644 drivers/pci/controller/mobiveil/pcie-mobiveil-plat.c create mode 100644 drivers/pci/controller/mobiveil/pcie-mobiveil.c create mode 100644 drivers/pci/controller/mobiveil/pcie-mobiveil.h diff --git a/MAINTAINERS b/MAINTAINERS index 2d916afea75d..084d225583e0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11447,7 +11447,7 @@ M: Subrahmanya Lingappa L: linux-pci@vger.kernel.org S: Supported F: Documentation/devicetree/bindings/pci/mobiveil-pcie.txt -F: drivers/pci/controller/pcie-mobiveil.c +F: drivers/pci/controller/mobiveil/pcie-mobiveil* PCI DRIVER FOR MVEBU (Marvell Armada 370 and Armada XP SOC support) M: Thomas Petazzoni diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig index 6671946dbf66..0e981ed00a75 100644 --- a/drivers/pci/controller/Kconfig +++ b/drivers/pci/controller/Kconfig @@ -241,16 +241,6 @@ config PCIE_MEDIATEK Say Y here if you want to enable PCIe controller support on MediaTek SoCs. -config PCIE_MOBIVEIL - bool "Mobiveil AXI PCIe controller" - depends on ARCH_ZYNQMP || COMPILE_TEST - depends on OF - depends on PCI_MSI_IRQ_DOMAIN - help - Say Y here if you want to enable support for the Mobiveil AXI PCIe - Soft IP. It has up to 8 outbound and inbound windows - for address translation and it is a PCIe Gen4 IP. - config PCIE_TANGO_SMP8759 bool "Tango SMP8759 PCIe controller (DANGEROUS)" depends on ARCH_TANGO && PCI_MSI && OF @@ -281,4 +271,5 @@ config VMD module will be called vmd. source "drivers/pci/controller/dwc/Kconfig" +source "drivers/pci/controller/mobiveil/Kconfig" endmenu diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile index d56a507495c5..b79a615041a0 100644 --- a/drivers/pci/controller/Makefile +++ b/drivers/pci/controller/Makefile @@ -26,11 +26,11 @@ obj-$(CONFIG_PCIE_ROCKCHIP) += pcie-rockchip.o obj-$(CONFIG_PCIE_ROCKCHIP_EP) += pcie-rockchip-ep.o obj-$(CONFIG_PCIE_ROCKCHIP_HOST) += pcie-rockchip-host.o obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o -obj-$(CONFIG_PCIE_MOBIVEIL) += pcie-mobiveil.o obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o obj-$(CONFIG_VMD) += vmd.o # pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW obj-y += dwc/ +obj-y += mobiveil/ # The following drivers are for devices that use the generic ACPI diff --git a/drivers/pci/controller/mobiveil/Kconfig b/drivers/pci/controller/mobiveil/Kconfig new file mode 100644 index 000000000000..64343c07bfed --- /dev/null +++ b/drivers/pci/controller/mobiveil/Kconfig @@ -0,0 +1,24 @@ +# SPDX-License-Identifier: GPL-2.0 + +menu "Mobiveil PCIe Core Support" + depends on PCI + +config PCIE_MOBIVEIL + bool + +config PCIE_MOBIVEIL_HOST + bool + depends on PCI_MSI_IRQ_DOMAIN + select PCIE_MOBIVEIL + +config PCIE_MOBIVEIL_PLAT + bool "Mobiveil AXI PCIe controller" + depends on ARCH_ZYNQMP || COMPILE_TEST + depends on OF + select PCIE_MOBIVEIL_HOST + help + Say Y here if you want to enable support for the Mobiveil AXI PCIe + Soft IP. It has up to 8 outbound and inbound windows + for address translation and it is a PCIe Gen4 IP. + +endmenu diff --git a/drivers/pci/controller/mobiveil/Makefile b/drivers/pci/controller/mobiveil/Makefile new file mode 100644 index 000000000000..9fb6d1c6504d --- /dev/null +++ b/drivers/pci/controller/mobiveil/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_PCIE_MOBIVEIL) += pcie-mobiveil.o +obj-$(CONFIG_PCIE_MOBIVEIL_HOST) += pcie-mobiveil-host.o +obj-$(CONFIG_PCIE_MOBIVEIL_PLAT) += pcie-mobiveil-plat.o diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c similarity index 55% rename from drivers/pci/controller/pcie-mobiveil.c rename to drivers/pci/controller/mobiveil/pcie-mobiveil-host.c index 9210165fe8c0..dc5324d94466 100644 --- a/drivers/pci/controller/pcie-mobiveil.c +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c @@ -4,9 +4,9 @@ * * Copyright (c) 2018 Mobiveil Inc. * Author: Subrahmanya Lingappa + * Refactor: Zhiqiang Hou */ -#include #include #include #include @@ -23,275 +23,21 @@ #include #include -#include "../pci.h" - -/* register offsets and bit positions */ - -/* - * translation tables are grouped into windows, each window registers are - * grouped into blocks of 4 or 16 registers each - */ -#define PAB_REG_BLOCK_SIZE 16 -#define PAB_EXT_REG_BLOCK_SIZE 4 - -#define PAB_REG_ADDR(offset, win) \ - (offset + (win * PAB_REG_BLOCK_SIZE)) -#define PAB_EXT_REG_ADDR(offset, win) \ - (offset + (win * PAB_EXT_REG_BLOCK_SIZE)) - -#define LTSSM_STATUS 0x0404 -#define LTSSM_STATUS_L0_MASK 0x3f -#define LTSSM_STATUS_L0 0x2d - -#define PAB_CTRL 0x0808 -#define AMBA_PIO_ENABLE_SHIFT 0 -#define PEX_PIO_ENABLE_SHIFT 1 -#define PAGE_SEL_SHIFT 13 -#define PAGE_SEL_MASK 0x3f -#define PAGE_LO_MASK 0x3ff -#define PAGE_SEL_OFFSET_SHIFT 10 - -#define PAB_AXI_PIO_CTRL 0x0840 -#define APIO_EN_MASK 0xf - -#define PAB_PEX_PIO_CTRL 0x08c0 -#define PIO_ENABLE_SHIFT 0 - -#define PAB_INTP_AMBA_MISC_ENB 0x0b0c -#define PAB_INTP_AMBA_MISC_STAT 0x0b1c -#define PAB_INTP_INTX_MASK 0x01e0 -#define PAB_INTP_MSI_MASK 0x8 - -#define PAB_AXI_AMAP_CTRL(win) PAB_REG_ADDR(0x0ba0, win) -#define WIN_ENABLE_SHIFT 0 -#define WIN_TYPE_SHIFT 1 -#define WIN_TYPE_MASK 0x3 -#define WIN_SIZE_SHIFT 10 -#define WIN_SIZE_MASK 0x3fffff - -#define PAB_EXT_AXI_AMAP_SIZE(win) PAB_EXT_REG_ADDR(0xbaf0, win) - -#define PAB_EXT_AXI_AMAP_AXI_WIN(win) PAB_EXT_REG_ADDR(0x80a0, win) -#define PAB_AXI_AMAP_AXI_WIN(win) PAB_REG_ADDR(0x0ba4, win) -#define AXI_WINDOW_ALIGN_MASK 3 - -#define PAB_AXI_AMAP_PEX_WIN_L(win) PAB_REG_ADDR(0x0ba8, win) -#define PAB_BUS_SHIFT 24 -#define PAB_DEVICE_SHIFT 19 -#define PAB_FUNCTION_SHIFT 16 - -#define PAB_AXI_AMAP_PEX_WIN_H(win) PAB_REG_ADDR(0x0bac, win) -#define PAB_INTP_AXI_PIO_CLASS 0x474 - -#define PAB_PEX_AMAP_CTRL(win) PAB_REG_ADDR(0x4ba0, win) -#define AMAP_CTRL_EN_SHIFT 0 -#define AMAP_CTRL_TYPE_SHIFT 1 -#define AMAP_CTRL_TYPE_MASK 3 - -#define PAB_EXT_PEX_AMAP_SIZEN(win) PAB_EXT_REG_ADDR(0xbef0, win) -#define PAB_EXT_PEX_AMAP_AXI_WIN(win) PAB_EXT_REG_ADDR(0xb4a0, win) -#define PAB_PEX_AMAP_AXI_WIN(win) PAB_REG_ADDR(0x4ba4, win) -#define PAB_PEX_AMAP_PEX_WIN_L(win) PAB_REG_ADDR(0x4ba8, win) -#define PAB_PEX_AMAP_PEX_WIN_H(win) PAB_REG_ADDR(0x4bac, win) - -/* starting offset of INTX bits in status register */ -#define PAB_INTX_START 5 - -/* supported number of MSI interrupts */ -#define PCI_NUM_MSI 16 - -/* MSI registers */ -#define MSI_BASE_LO_OFFSET 0x04 -#define MSI_BASE_HI_OFFSET 0x08 -#define MSI_SIZE_OFFSET 0x0c -#define MSI_ENABLE_OFFSET 0x14 -#define MSI_STATUS_OFFSET 0x18 -#define MSI_DATA_OFFSET 0x20 -#define MSI_ADDR_L_OFFSET 0x24 -#define MSI_ADDR_H_OFFSET 0x28 - -/* outbound and inbound window definitions */ -#define WIN_NUM_0 0 -#define WIN_NUM_1 1 -#define CFG_WINDOW_TYPE 0 -#define IO_WINDOW_TYPE 1 -#define MEM_WINDOW_TYPE 2 -#define IB_WIN_SIZE ((u64)256 * 1024 * 1024 * 1024) -#define MAX_PIO_WINDOWS 8 - -/* Parameters for the waiting for link up routine */ -#define LINK_WAIT_MAX_RETRIES 10 -#define LINK_WAIT_MIN 90000 -#define LINK_WAIT_MAX 100000 - -#define PAGED_ADDR_BNDRY 0xc00 -#define OFFSET_TO_PAGE_ADDR(off) \ - ((off & PAGE_LO_MASK) | PAGED_ADDR_BNDRY) -#define OFFSET_TO_PAGE_IDX(off) \ - ((off >> PAGE_SEL_OFFSET_SHIFT) & PAGE_SEL_MASK) - -struct mobiveil_msi { /* MSI information */ - struct mutex lock; /* protect bitmap variable */ - struct irq_domain *msi_domain; - struct irq_domain *dev_domain; - phys_addr_t msi_pages_phys; - int num_of_vectors; - DECLARE_BITMAP(msi_irq_in_use, PCI_NUM_MSI); -}; - -struct mobiveil_pcie { - struct platform_device *pdev; - struct list_head resources; - void __iomem *config_axi_slave_base; /* endpoint config base */ - void __iomem *csr_axi_slave_base; /* root port config base */ - void __iomem *apb_csr_base; /* MSI register base */ - phys_addr_t pcie_reg_base; /* Physical PCIe Controller Base */ - struct irq_domain *intx_domain; - raw_spinlock_t intx_mask_lock; - int irq; - int apio_wins; - int ppio_wins; - int ob_wins_configured; /* configured outbound windows */ - int ib_wins_configured; /* configured inbound windows */ - struct resource *ob_io_res; - char root_bus_nr; - struct mobiveil_msi msi; -}; - -/* - * mobiveil_pcie_sel_page - routine to access paged register - * - * Registers whose address greater than PAGED_ADDR_BNDRY (0xc00) are paged, - * for this scheme to work extracted higher 6 bits of the offset will be - * written to pg_sel field of PAB_CTRL register and rest of the lower 10 - * bits enabled with PAGED_ADDR_BNDRY are used as offset of the register. - */ -static void mobiveil_pcie_sel_page(struct mobiveil_pcie *pcie, u8 pg_idx) -{ - u32 val; - - val = readl(pcie->csr_axi_slave_base + PAB_CTRL); - val &= ~(PAGE_SEL_MASK << PAGE_SEL_SHIFT); - val |= (pg_idx & PAGE_SEL_MASK) << PAGE_SEL_SHIFT; - - writel(val, pcie->csr_axi_slave_base + PAB_CTRL); -} - -static void *mobiveil_pcie_comp_addr(struct mobiveil_pcie *pcie, u32 off) -{ - if (off < PAGED_ADDR_BNDRY) { - /* For directly accessed registers, clear the pg_sel field */ - mobiveil_pcie_sel_page(pcie, 0); - return pcie->csr_axi_slave_base + off; - } - - mobiveil_pcie_sel_page(pcie, OFFSET_TO_PAGE_IDX(off)); - return pcie->csr_axi_slave_base + OFFSET_TO_PAGE_ADDR(off); -} - -static int mobiveil_pcie_read(void __iomem *addr, int size, u32 *val) -{ - if ((uintptr_t)addr & (size - 1)) { - *val = 0; - return PCIBIOS_BAD_REGISTER_NUMBER; - } - - switch (size) { - case 4: - *val = readl(addr); - break; - case 2: - *val = readw(addr); - break; - case 1: - *val = readb(addr); - break; - default: - *val = 0; - return PCIBIOS_BAD_REGISTER_NUMBER; - } - - return PCIBIOS_SUCCESSFUL; -} - -static int mobiveil_pcie_write(void __iomem *addr, int size, u32 val) -{ - if ((uintptr_t)addr & (size - 1)) - return PCIBIOS_BAD_REGISTER_NUMBER; - - switch (size) { - case 4: - writel(val, addr); - break; - case 2: - writew(val, addr); - break; - case 1: - writeb(val, addr); - break; - default: - return PCIBIOS_BAD_REGISTER_NUMBER; - } - - return PCIBIOS_SUCCESSFUL; -} - -static u32 csr_read(struct mobiveil_pcie *pcie, u32 off, size_t size) -{ - void *addr; - u32 val; - int ret; - - addr = mobiveil_pcie_comp_addr(pcie, off); - - ret = mobiveil_pcie_read(addr, size, &val); - if (ret) - dev_err(&pcie->pdev->dev, "read CSR address failed\n"); - - return val; -} - -static void csr_write(struct mobiveil_pcie *pcie, u32 val, u32 off, size_t size) -{ - void *addr; - int ret; - - addr = mobiveil_pcie_comp_addr(pcie, off); - - ret = mobiveil_pcie_write(addr, size, val); - if (ret) - dev_err(&pcie->pdev->dev, "write CSR address failed\n"); -} - -static u32 csr_readl(struct mobiveil_pcie *pcie, u32 off) -{ - return csr_read(pcie, off, 0x4); -} - -static void csr_writel(struct mobiveil_pcie *pcie, u32 val, u32 off) -{ - csr_write(pcie, val, off, 0x4); -} - -static bool mobiveil_pcie_link_up(struct mobiveil_pcie *pcie) -{ - return (csr_readl(pcie, LTSSM_STATUS) & - LTSSM_STATUS_L0_MASK) == LTSSM_STATUS_L0; -} +#include "pcie-mobiveil.h" static bool mobiveil_pcie_valid_device(struct pci_bus *bus, unsigned int devfn) { struct mobiveil_pcie *pcie = bus->sysdata; /* Only one device down on each root port */ - if ((bus->number == pcie->root_bus_nr) && (devfn > 0)) + if ((bus->number == pcie->rp.root_bus_nr) && (devfn > 0)) return false; /* * Do not read more than one device on the bus directly * attached to RC */ - if ((bus->primary == pcie->root_bus_nr) && (devfn > 0)) + if ((bus->primary == pcie->rp.root_bus_nr) && (devfn > 0)) return false; return true; @@ -311,7 +57,7 @@ static void __iomem *mobiveil_pcie_map_bus(struct pci_bus *bus, return NULL; /* RC config access */ - if (bus->number == pcie->root_bus_nr) + if (bus->number == pcie->rp.root_bus_nr) return pcie->csr_axi_slave_base + where; /* @@ -326,7 +72,7 @@ static void __iomem *mobiveil_pcie_map_bus(struct pci_bus *bus, csr_writel(pcie, value, PAB_AXI_AMAP_PEX_WIN_L(WIN_NUM_0)); - return pcie->config_axi_slave_base + where; + return pcie->rp.config_axi_slave_base + where; } static struct pci_ops mobiveil_pcie_ops = { @@ -340,7 +86,7 @@ static void mobiveil_pcie_isr(struct irq_desc *desc) struct irq_chip *chip = irq_desc_get_chip(desc); struct mobiveil_pcie *pcie = irq_desc_get_handler_data(desc); struct device *dev = &pcie->pdev->dev; - struct mobiveil_msi *msi = &pcie->msi; + struct mobiveil_msi *msi = &pcie->rp.msi; u32 msi_data, msi_addr_lo, msi_addr_hi; u32 intr_status, msi_status; unsigned long shifted_status; @@ -365,7 +111,7 @@ static void mobiveil_pcie_isr(struct irq_desc *desc) shifted_status >>= PAB_INTX_START; do { for_each_set_bit(bit, &shifted_status, PCI_NUM_INTX) { - virq = irq_find_mapping(pcie->intx_domain, + virq = irq_find_mapping(pcie->rp.intx_domain, bit + 1); if (virq) generic_handle_irq(virq); @@ -428,10 +174,10 @@ static int mobiveil_pcie_parse_dt(struct mobiveil_pcie *pcie) /* map config resource */ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config_axi_slave"); - pcie->config_axi_slave_base = devm_pci_remap_cfg_resource(dev, res); - if (IS_ERR(pcie->config_axi_slave_base)) - return PTR_ERR(pcie->config_axi_slave_base); - pcie->ob_io_res = res; + pcie->rp.config_axi_slave_base = devm_pci_remap_cfg_resource(dev, res); + if (IS_ERR(pcie->rp.config_axi_slave_base)) + return PTR_ERR(pcie->rp.config_axi_slave_base); + pcie->rp.ob_io_res = res; /* map csr resource */ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, @@ -441,12 +187,6 @@ static int mobiveil_pcie_parse_dt(struct mobiveil_pcie *pcie) return PTR_ERR(pcie->csr_axi_slave_base); pcie->pcie_reg_base = res->start; - /* map MSI config resource */ - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "apb_csr"); - pcie->apb_csr_base = devm_pci_remap_cfg_resource(dev, res); - if (IS_ERR(pcie->apb_csr_base)) - return PTR_ERR(pcie->apb_csr_base); - /* read the number of windows requested */ if (of_property_read_u32(node, "apio-wins", &pcie->apio_wins)) pcie->apio_wins = MAX_PIO_WINDOWS; @@ -454,119 +194,15 @@ static int mobiveil_pcie_parse_dt(struct mobiveil_pcie *pcie) if (of_property_read_u32(node, "ppio-wins", &pcie->ppio_wins)) pcie->ppio_wins = MAX_PIO_WINDOWS; - pcie->irq = platform_get_irq(pdev, 0); - if (pcie->irq <= 0) { - dev_err(dev, "failed to map IRQ: %d\n", pcie->irq); - return -ENODEV; - } - return 0; } -static void program_ib_windows(struct mobiveil_pcie *pcie, int win_num, - u64 cpu_addr, u64 pci_addr, u32 type, u64 size) -{ - u32 value; - u64 size64 = ~(size - 1); - - if (win_num >= pcie->ppio_wins) { - dev_err(&pcie->pdev->dev, - "ERROR: max inbound windows reached !\n"); - return; - } - - value = csr_readl(pcie, PAB_PEX_AMAP_CTRL(win_num)); - value &= ~(AMAP_CTRL_TYPE_MASK << AMAP_CTRL_TYPE_SHIFT | - WIN_SIZE_MASK << WIN_SIZE_SHIFT); - value |= (type << AMAP_CTRL_TYPE_SHIFT) | (1 << AMAP_CTRL_EN_SHIFT) | - (lower_32_bits(size64) & WIN_SIZE_MASK << WIN_SIZE_SHIFT); - csr_writel(pcie, value, PAB_PEX_AMAP_CTRL(win_num)); - - csr_writel(pcie, upper_32_bits(size64), - PAB_EXT_PEX_AMAP_SIZEN(win_num)); - - csr_writel(pcie, lower_32_bits(cpu_addr), - PAB_PEX_AMAP_AXI_WIN(win_num)); - csr_writel(pcie, upper_32_bits(cpu_addr), - PAB_EXT_PEX_AMAP_AXI_WIN(win_num)); - - csr_writel(pcie, lower_32_bits(pci_addr), - PAB_PEX_AMAP_PEX_WIN_L(win_num)); - csr_writel(pcie, upper_32_bits(pci_addr), - PAB_PEX_AMAP_PEX_WIN_H(win_num)); - - pcie->ib_wins_configured++; -} - -/* - * routine to program the outbound windows - */ -static void program_ob_windows(struct mobiveil_pcie *pcie, int win_num, - u64 cpu_addr, u64 pci_addr, u32 type, u64 size) -{ - - u32 value; - u64 size64 = ~(size - 1); - - if (win_num >= pcie->apio_wins) { - dev_err(&pcie->pdev->dev, - "ERROR: max outbound windows reached !\n"); - return; - } - - /* - * program Enable Bit to 1, Type Bit to (00) base 2, AXI Window Size Bit - * to 4 KB in PAB_AXI_AMAP_CTRL register - */ - value = csr_readl(pcie, PAB_AXI_AMAP_CTRL(win_num)); - value &= ~(WIN_TYPE_MASK << WIN_TYPE_SHIFT | - WIN_SIZE_MASK << WIN_SIZE_SHIFT); - value |= 1 << WIN_ENABLE_SHIFT | type << WIN_TYPE_SHIFT | - (lower_32_bits(size64) & WIN_SIZE_MASK << WIN_SIZE_SHIFT); - csr_writel(pcie, value, PAB_AXI_AMAP_CTRL(win_num)); - - csr_writel(pcie, upper_32_bits(size64), PAB_EXT_AXI_AMAP_SIZE(win_num)); - - /* - * program AXI window base with appropriate value in - * PAB_AXI_AMAP_AXI_WIN0 register - */ - csr_writel(pcie, lower_32_bits(cpu_addr) & (~AXI_WINDOW_ALIGN_MASK), - PAB_AXI_AMAP_AXI_WIN(win_num)); - csr_writel(pcie, upper_32_bits(cpu_addr), - PAB_EXT_AXI_AMAP_AXI_WIN(win_num)); - - csr_writel(pcie, lower_32_bits(pci_addr), - PAB_AXI_AMAP_PEX_WIN_L(win_num)); - csr_writel(pcie, upper_32_bits(pci_addr), - PAB_AXI_AMAP_PEX_WIN_H(win_num)); - - pcie->ob_wins_configured++; -} - -static int mobiveil_bringup_link(struct mobiveil_pcie *pcie) -{ - int retries; - - /* check if the link is up or not */ - for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { - if (mobiveil_pcie_link_up(pcie)) - return 0; - - usleep_range(LINK_WAIT_MIN, LINK_WAIT_MAX); - } - - dev_err(&pcie->pdev->dev, "link never came up\n"); - - return -ETIMEDOUT; -} - static void mobiveil_pcie_enable_msi(struct mobiveil_pcie *pcie) { phys_addr_t msg_addr = pcie->pcie_reg_base; - struct mobiveil_msi *msi = &pcie->msi; + struct mobiveil_msi *msi = &pcie->rp.msi; - pcie->msi.num_of_vectors = PCI_NUM_MSI; + msi->num_of_vectors = PCI_NUM_MSI; msi->msi_pages_phys = (phys_addr_t)msg_addr; writel_relaxed(lower_32_bits(msg_addr), @@ -604,9 +240,6 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie) pab_ctrl |= (1 << AMBA_PIO_ENABLE_SHIFT) | (1 << PEX_PIO_ENABLE_SHIFT); csr_writel(pcie, pab_ctrl, PAB_CTRL); - csr_writel(pcie, (PAB_INTP_INTX_MASK | PAB_INTP_MSI_MASK), - PAB_INTP_AMBA_MISC_ENB); - /* * program PIO Enable Bit to 1 and Config Window Enable Bit to 1 in * PAB_AXI_PIO_CTRL Register @@ -628,20 +261,24 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie) */ /* config outbound translation window */ - program_ob_windows(pcie, WIN_NUM_0, pcie->ob_io_res->start, 0, - CFG_WINDOW_TYPE, resource_size(pcie->ob_io_res)); + program_ob_windows(pcie, WIN_NUM_0, pcie->rp.ob_io_res->start, 0, + CFG_WINDOW_TYPE, resource_size(pcie->rp.ob_io_res)); /* memory inbound translation window */ program_ib_windows(pcie, WIN_NUM_0, 0, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE); /* Get the I/O and memory ranges from DT */ resource_list_for_each_entry(win, &pcie->resources) { - if (resource_type(win->res) == IORESOURCE_MEM) + if (resource_type(win->res) == IORESOURCE_MEM) { type = MEM_WINDOW_TYPE; - else if (resource_type(win->res) == IORESOURCE_IO) + } else if (resource_type(win->res) == IORESOURCE_IO) { type = IO_WINDOW_TYPE; - else + } else if (resource_type(win->res) == IORESOURCE_BUS) { + pcie->rp.root_bus_nr = win->res->start; + continue; + } else { continue; + } /* configure outbound translation window */ program_ob_windows(pcie, pcie->ob_wins_configured, @@ -656,9 +293,6 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie) value |= (PCI_CLASS_BRIDGE_PCI << 16); csr_writel(pcie, value, PAB_INTP_AXI_PIO_CLASS); - /* setup MSI hardware registers */ - mobiveil_pcie_enable_msi(pcie); - return 0; } @@ -671,11 +305,11 @@ static void mobiveil_mask_intx_irq(struct irq_data *data) pcie = irq_desc_get_chip_data(desc); mask = 1 << ((data->hwirq + PAB_INTX_START) - 1); - raw_spin_lock_irqsave(&pcie->intx_mask_lock, flags); + raw_spin_lock_irqsave(&pcie->rp.intx_mask_lock, flags); shifted_val = csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB); shifted_val &= ~mask; csr_writel(pcie, shifted_val, PAB_INTP_AMBA_MISC_ENB); - raw_spin_unlock_irqrestore(&pcie->intx_mask_lock, flags); + raw_spin_unlock_irqrestore(&pcie->rp.intx_mask_lock, flags); } static void mobiveil_unmask_intx_irq(struct irq_data *data) @@ -687,11 +321,11 @@ static void mobiveil_unmask_intx_irq(struct irq_data *data) pcie = irq_desc_get_chip_data(desc); mask = 1 << ((data->hwirq + PAB_INTX_START) - 1); - raw_spin_lock_irqsave(&pcie->intx_mask_lock, flags); + raw_spin_lock_irqsave(&pcie->rp.intx_mask_lock, flags); shifted_val = csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB); shifted_val |= mask; csr_writel(pcie, shifted_val, PAB_INTP_AMBA_MISC_ENB); - raw_spin_unlock_irqrestore(&pcie->intx_mask_lock, flags); + raw_spin_unlock_irqrestore(&pcie->rp.intx_mask_lock, flags); } static struct irq_chip intx_irq_chip = { @@ -759,7 +393,7 @@ static int mobiveil_irq_msi_domain_alloc(struct irq_domain *domain, unsigned int nr_irqs, void *args) { struct mobiveil_pcie *pcie = domain->host_data; - struct mobiveil_msi *msi = &pcie->msi; + struct mobiveil_msi *msi = &pcie->rp.msi; unsigned long bit; WARN_ON(nr_irqs != 1); @@ -786,7 +420,7 @@ static void mobiveil_irq_msi_domain_free(struct irq_domain *domain, { struct irq_data *d = irq_domain_get_irq_data(domain, virq); struct mobiveil_pcie *pcie = irq_data_get_irq_chip_data(d); - struct mobiveil_msi *msi = &pcie->msi; + struct mobiveil_msi *msi = &pcie->rp.msi; mutex_lock(&msi->lock); @@ -807,9 +441,9 @@ static int mobiveil_allocate_msi_domains(struct mobiveil_pcie *pcie) { struct device *dev = &pcie->pdev->dev; struct fwnode_handle *fwnode = of_node_to_fwnode(dev->of_node); - struct mobiveil_msi *msi = &pcie->msi; + struct mobiveil_msi *msi = &pcie->rp.msi; - mutex_init(&pcie->msi.lock); + mutex_init(&msi->lock); msi->dev_domain = irq_domain_add_linear(NULL, msi->num_of_vectors, &msi_domain_ops, pcie); if (!msi->dev_domain) { @@ -836,15 +470,15 @@ static int mobiveil_pcie_init_irq_domain(struct mobiveil_pcie *pcie) int ret; /* setup INTx */ - pcie->intx_domain = irq_domain_add_linear(node, PCI_NUM_INTX, - &intx_domain_ops, pcie); + pcie->rp.intx_domain = irq_domain_add_linear(node, PCI_NUM_INTX, + &intx_domain_ops, pcie); - if (!pcie->intx_domain) { + if (!pcie->rp.intx_domain) { dev_err(dev, "Failed to get a INTx IRQ domain\n"); return -ENOMEM; } - raw_spin_lock_init(&pcie->intx_mask_lock); + raw_spin_lock_init(&pcie->rp.intx_mask_lock); /* setup MSI */ ret = mobiveil_allocate_msi_domains(pcie); @@ -854,24 +488,58 @@ static int mobiveil_pcie_init_irq_domain(struct mobiveil_pcie *pcie) return 0; } -static int mobiveil_pcie_probe(struct platform_device *pdev) +static int mobiveil_pcie_interrupt_init(struct mobiveil_pcie *pcie) +{ + struct device *dev = &pcie->pdev->dev; + struct resource *res; + int ret; + + if (pcie->rp.ops->interrupt_init) + return pcie->rp.ops->interrupt_init(pcie); + + /* map MSI config resource */ + res = platform_get_resource_byname(pcie->pdev, IORESOURCE_MEM, + "apb_csr"); + pcie->apb_csr_base = devm_pci_remap_cfg_resource(dev, res); + if (IS_ERR(pcie->apb_csr_base)) + return PTR_ERR(pcie->apb_csr_base); + + /* setup MSI hardware registers */ + mobiveil_pcie_enable_msi(pcie); + + pcie->rp.irq = platform_get_irq(pcie->pdev, 0); + if (pcie->rp.irq <= 0) { + dev_err(dev, "failed to map IRQ: %d\n", pcie->rp.irq); + return -ENODEV; + } + + /* initialize the IRQ domains */ + ret = mobiveil_pcie_init_irq_domain(pcie); + if (ret) { + dev_err(dev, "Failed creating IRQ Domain\n"); + return ret; + } + + irq_set_chained_handler_and_data(pcie->rp.irq, + mobiveil_pcie_isr, pcie); + + /* Enable interrupts */ + csr_writel(pcie, (PAB_INTP_INTX_MASK | PAB_INTP_MSI_MASK), + PAB_INTP_AMBA_MISC_ENB); + + return 0; +} + +int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie) { - struct mobiveil_pcie *pcie; struct pci_bus *bus; struct pci_bus *child; struct pci_host_bridge *bridge; - struct device *dev = &pdev->dev; + struct device *dev = &pcie->pdev->dev; resource_size_t iobase; int ret; - /* allocate the PCIe port */ - bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie)); - if (!bridge) - return -ENOMEM; - - pcie = pci_host_bridge_priv(bridge); - - pcie->pdev = pdev; + INIT_LIST_HEAD(&pcie->resources); ret = mobiveil_pcie_parse_dt(pcie); if (ret) { @@ -879,7 +547,10 @@ static int mobiveil_pcie_probe(struct platform_device *pdev) return ret; } - INIT_LIST_HEAD(&pcie->resources); + /* allocate the PCIe port */ + bridge = devm_pci_alloc_host_bridge(dev, 0); + if (!bridge) + return -ENOMEM; /* parse the host bridge base addresses from the device tree file */ ret = devm_of_pci_get_host_bridge_resources(dev, 0, 0xff, @@ -899,15 +570,12 @@ static int mobiveil_pcie_probe(struct platform_device *pdev) goto error; } - /* initialize the IRQ domains */ - ret = mobiveil_pcie_init_irq_domain(pcie); + ret = mobiveil_pcie_interrupt_init(pcie); if (ret) { - dev_err(dev, "Failed creating IRQ Domain\n"); + dev_err(dev, "Interrupt init failed\n"); goto error; } - irq_set_chained_handler_and_data(pcie->irq, mobiveil_pcie_isr, pcie); - ret = devm_request_pci_bus_resources(dev, &pcie->resources); if (ret) goto error; @@ -916,7 +584,7 @@ static int mobiveil_pcie_probe(struct platform_device *pdev) list_splice_init(&pcie->resources, &bridge->windows); bridge->dev.parent = dev; bridge->sysdata = pcie; - bridge->busnr = pcie->root_bus_nr; + bridge->busnr = pcie->rp.root_bus_nr; bridge->ops = &mobiveil_pcie_ops; bridge->map_irq = of_irq_parse_and_map_pci; bridge->swizzle_irq = pci_common_swizzle; @@ -944,25 +612,3 @@ static int mobiveil_pcie_probe(struct platform_device *pdev) pci_free_resource_list(&pcie->resources); return ret; } - -static const struct of_device_id mobiveil_pcie_of_match[] = { - {.compatible = "mbvl,gpex40-pcie",}, - {}, -}; - -MODULE_DEVICE_TABLE(of, mobiveil_pcie_of_match); - -static struct platform_driver mobiveil_pcie_driver = { - .probe = mobiveil_pcie_probe, - .driver = { - .name = "mobiveil-pcie", - .of_match_table = mobiveil_pcie_of_match, - .suppress_bind_attrs = true, - }, -}; - -builtin_platform_driver(mobiveil_pcie_driver); - -MODULE_LICENSE("GPL v2"); -MODULE_DESCRIPTION("Mobiveil PCIe host controller driver"); -MODULE_AUTHOR("Subrahmanya Lingappa "); diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil-plat.c b/drivers/pci/controller/mobiveil/pcie-mobiveil-plat.c new file mode 100644 index 000000000000..216c62f35568 --- /dev/null +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil-plat.c @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * PCIe host controller driver for Mobiveil PCIe Host controller + * + * Copyright (c) 2018 Mobiveil Inc. + * Author: Subrahmanya Lingappa + * Refactor: Zhiqiang Hou + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "pcie-mobiveil.h" + +static int mobiveil_pcie_probe(struct platform_device *pdev) +{ + struct mobiveil_pcie *pcie; + struct device *dev = &pdev->dev; + + pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); + if (!pcie) + return -ENOMEM; + + pcie->pdev = pdev; + + return mobiveil_pcie_host_probe(pcie); +} + +static const struct of_device_id mobiveil_pcie_of_match[] = { + {.compatible = "mbvl,gpex40-pcie",}, + {}, +}; + +MODULE_DEVICE_TABLE(of, mobiveil_pcie_of_match); + +static struct platform_driver mobiveil_pcie_driver = { + .probe = mobiveil_pcie_probe, + .driver = { + .name = "mobiveil-pcie", + .of_match_table = mobiveil_pcie_of_match, + .suppress_bind_attrs = true, + }, +}; + +builtin_platform_driver(mobiveil_pcie_driver); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("Mobiveil PCIe host controller driver"); +MODULE_AUTHOR("Subrahmanya Lingappa "); diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.c b/drivers/pci/controller/mobiveil/pcie-mobiveil.c new file mode 100644 index 000000000000..ee678a60825d --- /dev/null +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.c @@ -0,0 +1,228 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * PCIe host controller driver for Mobiveil PCIe Host controller + * + * Copyright (c) 2018 Mobiveil Inc. + * Author: Subrahmanya Lingappa + * Refactor: Zhiqiang Hou + */ + +#include +#include +#include +#include +#include + +#include "pcie-mobiveil.h" + +/* + * mobiveil_pcie_sel_page - routine to access paged register + * + * Registers whose address greater than PAGED_ADDR_BNDRY (0xc00) are paged, + * for this scheme to work extracted higher 6 bits of the offset will be + * written to pg_sel field of PAB_CTRL register and rest of the lower 10 + * bits enabled with PAGED_ADDR_BNDRY are used as offset of the register. + */ +static void mobiveil_pcie_sel_page(struct mobiveil_pcie *pcie, u8 pg_idx) +{ + u32 val; + + val = readl(pcie->csr_axi_slave_base + PAB_CTRL); + val &= ~(PAGE_SEL_MASK << PAGE_SEL_SHIFT); + val |= (pg_idx & PAGE_SEL_MASK) << PAGE_SEL_SHIFT; + + writel(val, pcie->csr_axi_slave_base + PAB_CTRL); +} + +static void *mobiveil_pcie_comp_addr(struct mobiveil_pcie *pcie, u32 off) +{ + if (off < PAGED_ADDR_BNDRY) { + /* For directly accessed registers, clear the pg_sel field */ + mobiveil_pcie_sel_page(pcie, 0); + return pcie->csr_axi_slave_base + off; + } + + mobiveil_pcie_sel_page(pcie, OFFSET_TO_PAGE_IDX(off)); + return pcie->csr_axi_slave_base + OFFSET_TO_PAGE_ADDR(off); +} + +static int mobiveil_pcie_read(void __iomem *addr, int size, u32 *val) +{ + if ((uintptr_t)addr & (size - 1)) { + *val = 0; + return PCIBIOS_BAD_REGISTER_NUMBER; + } + + switch (size) { + case 4: + *val = readl(addr); + break; + case 2: + *val = readw(addr); + break; + case 1: + *val = readb(addr); + break; + default: + *val = 0; + return PCIBIOS_BAD_REGISTER_NUMBER; + } + + return PCIBIOS_SUCCESSFUL; +} + +static int mobiveil_pcie_write(void __iomem *addr, int size, u32 val) +{ + if ((uintptr_t)addr & (size - 1)) + return PCIBIOS_BAD_REGISTER_NUMBER; + + switch (size) { + case 4: + writel(val, addr); + break; + case 2: + writew(val, addr); + break; + case 1: + writeb(val, addr); + break; + default: + return PCIBIOS_BAD_REGISTER_NUMBER; + } + + return PCIBIOS_SUCCESSFUL; +} + +u32 csr_read(struct mobiveil_pcie *pcie, u32 off, size_t size) +{ + void *addr; + u32 val; + int ret; + + addr = mobiveil_pcie_comp_addr(pcie, off); + + ret = mobiveil_pcie_read(addr, size, &val); + if (ret) + dev_err(&pcie->pdev->dev, "read CSR address failed\n"); + + return val; +} + +void csr_write(struct mobiveil_pcie *pcie, u32 val, u32 off, size_t size) +{ + void *addr; + int ret; + + addr = mobiveil_pcie_comp_addr(pcie, off); + + ret = mobiveil_pcie_write(addr, size, val); + if (ret) + dev_err(&pcie->pdev->dev, "write CSR address failed\n"); +} + +bool mobiveil_pcie_link_up(struct mobiveil_pcie *pcie) +{ + if (pcie->ops->link_up) + return pcie->ops->link_up(pcie); + + return (csr_readl(pcie, LTSSM_STATUS) & + LTSSM_STATUS_L0_MASK) == LTSSM_STATUS_L0; +} + +void program_ib_windows(struct mobiveil_pcie *pcie, int win_num, u64 cpu_addr, + u64 pci_addr, u32 type, u64 size) +{ + u32 value; + u64 size64 = ~(size - 1); + + if (win_num >= pcie->ppio_wins) { + dev_err(&pcie->pdev->dev, + "ERROR: max inbound windows reached !\n"); + return; + } + + value = csr_readl(pcie, PAB_PEX_AMAP_CTRL(win_num)); + value &= ~(AMAP_CTRL_TYPE_MASK << AMAP_CTRL_TYPE_SHIFT | + WIN_SIZE_MASK << WIN_SIZE_SHIFT); + value |= (type << AMAP_CTRL_TYPE_SHIFT) | (1 << AMAP_CTRL_EN_SHIFT) | + (lower_32_bits(size64) & WIN_SIZE_MASK << WIN_SIZE_SHIFT); + csr_writel(pcie, value, PAB_PEX_AMAP_CTRL(win_num)); + + csr_writel(pcie, upper_32_bits(size64), + PAB_EXT_PEX_AMAP_SIZEN(win_num)); + + csr_writel(pcie, lower_32_bits(cpu_addr), + PAB_PEX_AMAP_AXI_WIN(win_num)); + csr_writel(pcie, upper_32_bits(cpu_addr), + PAB_EXT_PEX_AMAP_AXI_WIN(win_num)); + + csr_writel(pcie, lower_32_bits(pci_addr), + PAB_PEX_AMAP_PEX_WIN_L(win_num)); + csr_writel(pcie, upper_32_bits(pci_addr), + PAB_PEX_AMAP_PEX_WIN_H(win_num)); + + pcie->ib_wins_configured++; +} + +/* + * routine to program the outbound windows + */ +void program_ob_windows(struct mobiveil_pcie *pcie, int win_num, u64 cpu_addr, + u64 pci_addr, u32 type, u64 size) +{ + + u32 value; + u64 size64 = ~(size - 1); + + if (win_num >= pcie->apio_wins) { + dev_err(&pcie->pdev->dev, + "ERROR: max outbound windows reached !\n"); + return; + } + + /* + * program Enable Bit to 1, Type Bit to (00) base 2, AXI Window Size Bit + * to 4 KB in PAB_AXI_AMAP_CTRL register + */ + value = csr_readl(pcie, PAB_AXI_AMAP_CTRL(win_num)); + value &= ~(WIN_TYPE_MASK << WIN_TYPE_SHIFT | + WIN_SIZE_MASK << WIN_SIZE_SHIFT); + value |= 1 << WIN_ENABLE_SHIFT | type << WIN_TYPE_SHIFT | + (lower_32_bits(size64) & WIN_SIZE_MASK << WIN_SIZE_SHIFT); + csr_writel(pcie, value, PAB_AXI_AMAP_CTRL(win_num)); + + csr_writel(pcie, upper_32_bits(size64), PAB_EXT_AXI_AMAP_SIZE(win_num)); + + /* + * program AXI window base with appropriate value in + * PAB_AXI_AMAP_AXI_WIN0 register + */ + csr_writel(pcie, lower_32_bits(cpu_addr) & (~AXI_WINDOW_ALIGN_MASK), + PAB_AXI_AMAP_AXI_WIN(win_num)); + csr_writel(pcie, upper_32_bits(cpu_addr), + PAB_EXT_AXI_AMAP_AXI_WIN(win_num)); + + csr_writel(pcie, lower_32_bits(pci_addr), + PAB_AXI_AMAP_PEX_WIN_L(win_num)); + csr_writel(pcie, upper_32_bits(pci_addr), + PAB_AXI_AMAP_PEX_WIN_H(win_num)); + + pcie->ob_wins_configured++; +} + +int mobiveil_bringup_link(struct mobiveil_pcie *pcie) +{ + int retries; + + /* check if the link is up or not */ + for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { + if (mobiveil_pcie_link_up(pcie)) + return 0; + + usleep_range(LINK_WAIT_MIN, LINK_WAIT_MAX); + } + + dev_err(&pcie->pdev->dev, "link never came up\n"); + + return -ETIMEDOUT; +} diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.h b/drivers/pci/controller/mobiveil/pcie-mobiveil.h new file mode 100644 index 000000000000..eb4cb61291a8 --- /dev/null +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.h @@ -0,0 +1,187 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * PCIe host controller driver for Mobiveil PCIe Host controller + * + * Copyright (c) 2018 Mobiveil Inc. + * Author: Subrahmanya Lingappa + * Refactor: Zhiqiang Hou + */ + +#ifndef _PCIE_MOBIVEIL_H +#define _PCIE_MOBIVEIL_H + +#include +#include +#include +#include "../../pci.h" + +/* register offsets and bit positions */ + +/* + * translation tables are grouped into windows, each window registers are + * grouped into blocks of 4 or 16 registers each + */ +#define PAB_REG_BLOCK_SIZE 16 +#define PAB_EXT_REG_BLOCK_SIZE 4 + +#define PAB_REG_ADDR(offset, win) \ + (offset + (win * PAB_REG_BLOCK_SIZE)) +#define PAB_EXT_REG_ADDR(offset, win) \ + (offset + (win * PAB_EXT_REG_BLOCK_SIZE)) + +#define LTSSM_STATUS 0x0404 +#define LTSSM_STATUS_L0_MASK 0x3f +#define LTSSM_STATUS_L0 0x2d + +#define PAB_CTRL 0x0808 +#define AMBA_PIO_ENABLE_SHIFT 0 +#define PEX_PIO_ENABLE_SHIFT 1 +#define PAGE_SEL_SHIFT 13 +#define PAGE_SEL_MASK 0x3f +#define PAGE_LO_MASK 0x3ff +#define PAGE_SEL_OFFSET_SHIFT 10 + +#define PAB_AXI_PIO_CTRL 0x0840 +#define APIO_EN_MASK 0xf + +#define PAB_PEX_PIO_CTRL 0x08c0 +#define PIO_ENABLE_SHIFT 0 + +#define PAB_INTP_AMBA_MISC_ENB 0x0b0c +#define PAB_INTP_AMBA_MISC_STAT 0x0b1c +#define PAB_INTP_INTX_MASK 0x01e0 +#define PAB_INTP_MSI_MASK 0x8 + +#define PAB_AXI_AMAP_CTRL(win) PAB_REG_ADDR(0x0ba0, win) +#define WIN_ENABLE_SHIFT 0 +#define WIN_TYPE_SHIFT 1 +#define WIN_TYPE_MASK 0x3 +#define WIN_SIZE_SHIFT 10 +#define WIN_SIZE_MASK 0x3fffff + +#define PAB_EXT_AXI_AMAP_SIZE(win) PAB_EXT_REG_ADDR(0xbaf0, win) + +#define PAB_EXT_AXI_AMAP_AXI_WIN(win) PAB_EXT_REG_ADDR(0x80a0, win) +#define PAB_AXI_AMAP_AXI_WIN(win) PAB_REG_ADDR(0x0ba4, win) +#define AXI_WINDOW_ALIGN_MASK 3 + +#define PAB_AXI_AMAP_PEX_WIN_L(win) PAB_REG_ADDR(0x0ba8, win) +#define PAB_BUS_SHIFT 24 +#define PAB_DEVICE_SHIFT 19 +#define PAB_FUNCTION_SHIFT 16 + +#define PAB_AXI_AMAP_PEX_WIN_H(win) PAB_REG_ADDR(0x0bac, win) +#define PAB_INTP_AXI_PIO_CLASS 0x474 + +#define PAB_PEX_AMAP_CTRL(win) PAB_REG_ADDR(0x4ba0, win) +#define AMAP_CTRL_EN_SHIFT 0 +#define AMAP_CTRL_TYPE_SHIFT 1 +#define AMAP_CTRL_TYPE_MASK 3 + +#define PAB_EXT_PEX_AMAP_SIZEN(win) PAB_EXT_REG_ADDR(0xbef0, win) +#define PAB_EXT_PEX_AMAP_AXI_WIN(win) PAB_EXT_REG_ADDR(0xb4a0, win) +#define PAB_PEX_AMAP_AXI_WIN(win) PAB_REG_ADDR(0x4ba4, win) +#define PAB_PEX_AMAP_PEX_WIN_L(win) PAB_REG_ADDR(0x4ba8, win) +#define PAB_PEX_AMAP_PEX_WIN_H(win) PAB_REG_ADDR(0x4bac, win) + +/* starting offset of INTX bits in status register */ +#define PAB_INTX_START 5 + +/* supported number of MSI interrupts */ +#define PCI_NUM_MSI 16 + +/* MSI registers */ +#define MSI_BASE_LO_OFFSET 0x04 +#define MSI_BASE_HI_OFFSET 0x08 +#define MSI_SIZE_OFFSET 0x0c +#define MSI_ENABLE_OFFSET 0x14 +#define MSI_STATUS_OFFSET 0x18 +#define MSI_DATA_OFFSET 0x20 +#define MSI_ADDR_L_OFFSET 0x24 +#define MSI_ADDR_H_OFFSET 0x28 + +/* outbound and inbound window definitions */ +#define WIN_NUM_0 0 +#define WIN_NUM_1 1 +#define CFG_WINDOW_TYPE 0 +#define IO_WINDOW_TYPE 1 +#define MEM_WINDOW_TYPE 2 +#define IB_WIN_SIZE ((u64)256 * 1024 * 1024 * 1024) +#define MAX_PIO_WINDOWS 8 + +/* Parameters for the waiting for link up routine */ +#define LINK_WAIT_MAX_RETRIES 10 +#define LINK_WAIT_MIN 90000 +#define LINK_WAIT_MAX 100000 + +#define PAGED_ADDR_BNDRY 0xc00 +#define OFFSET_TO_PAGE_ADDR(off) \ + ((off & PAGE_LO_MASK) | PAGED_ADDR_BNDRY) +#define OFFSET_TO_PAGE_IDX(off) \ + ((off >> PAGE_SEL_OFFSET_SHIFT) & PAGE_SEL_MASK) + +struct mobiveil_pcie; + +struct mobiveil_msi { /* MSI information */ + struct mutex lock; /* protect bitmap variable */ + struct irq_domain *msi_domain; + struct irq_domain *dev_domain; + phys_addr_t msi_pages_phys; + int num_of_vectors; + DECLARE_BITMAP(msi_irq_in_use, PCI_NUM_MSI); +}; + +struct mobiveil_rp_ops { + int (*interrupt_init)(struct mobiveil_pcie *pcie); +}; + +struct root_port { + u8 root_bus_nr; + void __iomem *config_axi_slave_base; /* endpoint config base */ + struct resource *ob_io_res; + struct mobiveil_rp_ops *ops; + int irq; + raw_spinlock_t intx_mask_lock; + struct irq_domain *intx_domain; + struct mobiveil_msi msi; +}; + +struct mobiveil_pab_ops { + int (*link_up)(struct mobiveil_pcie *pcie); +}; + +struct mobiveil_pcie { + struct platform_device *pdev; + struct list_head resources; + void __iomem *csr_axi_slave_base; /* PAB registers base */ + phys_addr_t pcie_reg_base; /* Physical PCIe Controller Base */ + void __iomem *apb_csr_base; /* MSI register base */ + u32 apio_wins; + u32 ppio_wins; + u32 ob_wins_configured; /* configured outbound windows */ + u32 ib_wins_configured; /* configured inbound windows */ + const struct mobiveil_pab_ops *ops; + struct root_port rp; +}; + +int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie); +bool mobiveil_pcie_link_up(struct mobiveil_pcie *pcie); +int mobiveil_bringup_link(struct mobiveil_pcie *pcie); +void program_ob_windows(struct mobiveil_pcie *pcie, int win_num, u64 cpu_addr, + u64 pci_addr, u32 type, u64 size); +void program_ib_windows(struct mobiveil_pcie *pcie, int win_num, u64 cpu_addr, + u64 pci_addr, u32 type, u64 size); +u32 csr_read(struct mobiveil_pcie *pcie, u32 off, size_t size); +void csr_write(struct mobiveil_pcie *pcie, u32 val, u32 off, size_t size); + +static inline u32 csr_readl(struct mobiveil_pcie *pcie, u32 off) +{ + return csr_read(pcie, off, 0x4); +} + +static inline void csr_writel(struct mobiveil_pcie *pcie, u32 val, u32 off) +{ + csr_write(pcie, val, off, 0x4); +} + +#endif /* _PCIE_MOBIVEIL_H */ From patchwork Tue Nov 20 09:27:21 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Z.Q. Hou" X-Patchwork-Id: 1000344 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=nxp.com header.i=@nxp.com header.b="tkR+qVte"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42zgNF5NGnz9s8F for ; Tue, 20 Nov 2018 20:27:41 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727621AbeKTTzf (ORCPT ); Tue, 20 Nov 2018 14:55:35 -0500 Received: from mail-eopbgr70054.outbound.protection.outlook.com ([40.107.7.54]:64008 "EHLO EUR04-HE1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727601AbeKTTze (ORCPT ); Tue, 20 Nov 2018 14:55:34 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=/USPXyQcrsZGKosk4JU+LBbEUGh9CpRDV/DPjJVrauk=; b=tkR+qVte1Ht2aYFRtCSgtNP2zCIvdAWGFPKcVGfmFJaLr+WUPetrQiOUlRaLeXBhNM39xrujguRD9CDCDM1C9EklDlESolwZmbL6JS5yjvWuWykClSSXAqCcrU+9HAfkT4G1/xapUMGKy1JE+LFg/ZXYoMHJFkq/uTY0cYQhkYk= Received: from AM6PR04MB5781.eurprd04.prod.outlook.com (20.179.2.80) by AM6PR04MB5269.eurprd04.prod.outlook.com (20.177.35.214) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1339.21; Tue, 20 Nov 2018 09:27:21 +0000 Received: from AM6PR04MB5781.eurprd04.prod.outlook.com ([fe80::29b5:b3ed:3854:cf1c]) by AM6PR04MB5781.eurprd04.prod.outlook.com ([fe80::29b5:b3ed:3854:cf1c%4]) with mapi id 15.20.1339.026; Tue, 20 Nov 2018 09:27:21 +0000 From: "Z.q. Hou" To: "linux-pci@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "bhelgaas@google.com" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "l.subrahmanya@mobiveil.co.in" , "shawnguo@kernel.org" , Leo Li , "lorenzo.pieralisi@arm.com" , "catalin.marinas@arm.com" , "will.deacon@arm.com" CC: Mingkai Hu , "M.h. Lian" , Xiaowei Bao , "Z.q. Hou" Subject: [PATCHv2 17/25] PCI: mobiveil: fix the checking of valid device Thread-Topic: [PATCHv2 17/25] PCI: mobiveil: fix the checking of valid device Thread-Index: AQHUgLM9PQwv8Z1F2kGXCcsoQ8hriA== Date: Tue, 20 Nov 2018 09:27:21 +0000 Message-ID: <20181120092615.11680-18-Zhiqiang.Hou@nxp.com> References: <20181120092615.11680-1-Zhiqiang.Hou@nxp.com> In-Reply-To: <20181120092615.11680-1-Zhiqiang.Hou@nxp.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: HK2PR03CA0050.apcprd03.prod.outlook.com (2603:1096:202:17::20) To AM6PR04MB5781.eurprd04.prod.outlook.com (2603:10a6:20b:aa::16) authentication-results: spf=none (sender IP is ) smtp.mailfrom=zhiqiang.hou@nxp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [119.31.174.73] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; AM6PR04MB5269; 6:a5LCI9VhBmjD5Li+tOt4SLl7ROGn7ZFXJl6tNd0ywnB3PObMRqfqYCIqUv5m8jNF29DyO9HcKW8BwlfxtdjB2hwDpTtD1HqgDq+tYwuJt8BtH8tlzqYa1PH4/oSPdmoHn4Za16lADYVqlegUD10Ok4OjrrEUK2jk4kmMYRaNtlirVcpL0XcW9bsHVUI/cIkv2cLoKfeAKBItqqCtVVTZPET7Z/2/R79wb0P0R6GtGRtgDv2XMhdKQ+1Lmsbfm96Kef3da/LyG/DkX7Q1bk8buxbmqs8YoayVX7Awdf+JgnTzvKikDqYY3y0f4YfXLMIV9aXzEmvTQ1tDjQeXUq+D2rkT/qErLofhQ9xMys3N4KEs4EGui1gzXLeiTnm7NzBUtwRexkSFMqd9D3yewDSzAmSvzLZBNRimywrrnsmJxOpjkRJRhA399TIHPDf0YZu371v47GGYgkR+jluGIYL3Hw==; 5:8jXHTxQsmlof0O3KNYXZRTIIAGk0ZXFTczB0HEzhPgHEXXxKWfmSZtYHrgEjno6oRtPTyvOdcF34xFQzHyWcZl+yx8rahaW7ION4YxoNJXnXvkytCIwsm63FKlBG8vfebN+EDZ/WuwIbgDLhx2Nk9WycKBWiWbdXn8uOdoKHk/g=; 7:RRZSsZL9rxWFWUsCa+iR9e9g2WOyCp9i78DAkDCdHNqUemujZ+jgU8JLVPFMMRkBhyzZnH8yVzl4eOz8TCOusDjNgGPW4Nt29OB9EyQ6H5flrCLZ0yWwKG0UpjqfijLpzmawKNJ6VEnaLvfB3Xw4+Q== x-ms-office365-filtering-correlation-id: 45f2c008-aebc-456f-6cfa-08d64eca5f71 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390098)(7020095)(4652040)(8989299)(5600074)(711020)(4618075)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7153060)(7193020); SRVR:AM6PR04MB5269; x-ms-traffictypediagnostic: AM6PR04MB5269: x-microsoft-antispam-prvs: x-ms-exchange-senderadcheck: 1 x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(8211001083)(6040522)(2401047)(5005006)(8121501046)(3231442)(944501410)(52105112)(3002001)(10201501046)(93006095)(93001095)(6055026)(148016)(149066)(150057)(6041310)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123558120)(20161123564045)(20161123560045)(20161123562045)(201708071742011)(7699051)(76991095); SRVR:AM6PR04MB5269; BCL:0; PCL:0; RULEID:; SRVR:AM6PR04MB5269; x-forefront-prvs: 08626BE3A5 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(346002)(376002)(136003)(396003)(366004)(39860400002)(189003)(199004)(305945005)(7736002)(36756003)(5660300001)(7416002)(68736007)(2906002)(4326008)(8936002)(14454004)(5024004)(256004)(54906003)(14444005)(53936002)(6436002)(71200400001)(110136005)(71190400001)(6512007)(316002)(2616005)(476003)(446003)(11346002)(486006)(25786009)(2501003)(2201001)(86362001)(52116002)(76176011)(6506007)(102836004)(386003)(186003)(106356001)(26005)(2900100001)(81156014)(81166006)(105586002)(6486002)(8676002)(99286004)(66066001)(6116002)(3846002)(1076002)(478600001)(97736004)(921003)(1121003); DIR:OUT; SFP:1101; SCL:1; SRVR:AM6PR04MB5269; H:AM6PR04MB5781.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: ZUmOg5um4tPiaNj5sE7xYQXZ2VgEdrAm1SS1W+Cv6Akk51DJzZ+DNui/4THlnvXvUHGrgP4inYbW/vfPcduepgInActlNW6E2KolnjyrcJprOXkcBhpXdkmciw5eHoau+8i3FHNhj5QEDxZ4V7q7CN5haSi3r8lpB07Ndzd30/JciKEmpv5W3EWR0yFFBPacNhRzZcXH7ND+q1i3gC8S+Jco460Inp2Q6XGypWVbVtGuACkoVW1MuWZQqp0fuLVeeIroxdXqv46qhWEsV/Ecs9RRe1ycmTFTUU+QAy0RO0Shr5godZpz77J7A2Y+d1Kad+IElecpRPWvd7zd2szVoi2dEWziL/NKn7DNhUQyX18= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 45f2c008-aebc-456f-6cfa-08d64eca5f71 X-MS-Exchange-CrossTenant-originalarrivaltime: 20 Nov 2018 09:27:21.3633 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR04MB5269 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Hou Zhiqiang Avoid to issue CFG transactions to link partner when the PCIe link is not up. And allow CFG transactions to all functions of Endpoint implemented multiple functions. Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP driver") Signed-off-by: Hou Zhiqiang reviewed-by: Minghuan Lian --- V2: - New patch drivers/pci/controller/mobiveil/pcie-mobiveil-host.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c b/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c index dc5324d94466..1ae82e790562 100644 --- a/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c @@ -29,6 +29,10 @@ static bool mobiveil_pcie_valid_device(struct pci_bus *bus, unsigned int devfn) { struct mobiveil_pcie *pcie = bus->sysdata; + /* If there is no link, then there is no device */ + if (bus->number > pcie->rp.root_bus_nr && !mobiveil_pcie_link_up(pcie)) + return false; + /* Only one device down on each root port */ if ((bus->number == pcie->rp.root_bus_nr) && (devfn > 0)) return false; @@ -37,7 +41,7 @@ static bool mobiveil_pcie_valid_device(struct pci_bus *bus, unsigned int devfn) * Do not read more than one device on the bus directly * attached to RC */ - if ((bus->primary == pcie->rp.root_bus_nr) && (devfn > 0)) + if ((bus->primary == pcie->rp.root_bus_nr) && (PCI_SLOT(devfn) > 0)) return false; return true; From patchwork Tue Nov 20 09:27:27 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Z.Q. Hou" X-Patchwork-Id: 1000343 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=nxp.com header.i=@nxp.com header.b="bPkLHfoh"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42zgND0rQwz9s3l for ; Tue, 20 Nov 2018 20:27:40 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727650AbeKTTzk (ORCPT ); Tue, 20 Nov 2018 14:55:40 -0500 Received: from mail-eopbgr70054.outbound.protection.outlook.com ([40.107.7.54]:22608 "EHLO EUR04-HE1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727619AbeKTTzj (ORCPT ); Tue, 20 Nov 2018 14:55:39 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=YoA/AjZZM10D7utpJ22+WJNHEtNZ6Oqk3ZBm1m/xwIg=; b=bPkLHfohSOCeCO4r4RbLBlPxvuRNSeYnYlJqcbsxBOaUf5oq4seXUQgo9Rro+BsindyZI+kpGrOvAEKCmHky2/tD45gSUjHj22q8mKaSo/ekb+Ijwi/L8X+Hn5MM/l2GBHYpUS2/cEVw461x5LmP4DKBDwp3NiulVqroy21n+dQ= Received: from AM6PR04MB5781.eurprd04.prod.outlook.com (20.179.2.80) by AM6PR04MB5269.eurprd04.prod.outlook.com (20.177.35.214) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1339.21; Tue, 20 Nov 2018 09:27:27 +0000 Received: from AM6PR04MB5781.eurprd04.prod.outlook.com ([fe80::29b5:b3ed:3854:cf1c]) by AM6PR04MB5781.eurprd04.prod.outlook.com ([fe80::29b5:b3ed:3854:cf1c%4]) with mapi id 15.20.1339.026; Tue, 20 Nov 2018 09:27:27 +0000 From: "Z.q. Hou" To: "linux-pci@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "bhelgaas@google.com" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "l.subrahmanya@mobiveil.co.in" , "shawnguo@kernel.org" , Leo Li , "lorenzo.pieralisi@arm.com" , "catalin.marinas@arm.com" , "will.deacon@arm.com" CC: Mingkai Hu , "M.h. Lian" , Xiaowei Bao , "Z.q. Hou" Subject: [PATCHv2 18/25] PCI: mobiveil: continue to initialize the host upon no PCIe link Thread-Topic: [PATCHv2 18/25] PCI: mobiveil: continue to initialize the host upon no PCIe link Thread-Index: AQHUgLNAYjS1Cnpgq0ebuFei+bnlwA== Date: Tue, 20 Nov 2018 09:27:27 +0000 Message-ID: <20181120092615.11680-19-Zhiqiang.Hou@nxp.com> References: <20181120092615.11680-1-Zhiqiang.Hou@nxp.com> In-Reply-To: <20181120092615.11680-1-Zhiqiang.Hou@nxp.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: HK2PR03CA0050.apcprd03.prod.outlook.com (2603:1096:202:17::20) To AM6PR04MB5781.eurprd04.prod.outlook.com (2603:10a6:20b:aa::16) authentication-results: spf=none (sender IP is ) smtp.mailfrom=zhiqiang.hou@nxp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [119.31.174.73] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; AM6PR04MB5269; 6:S3birnnWbAGQzE2QICPiXbS1qAalb4WdNZofL7aVfXGJWnofSxgID0YxE31NIuAItRvtiLfAnLzc9YinxLtnZ2Mv2qHu1egiqbQ5g1foSCttvAyUCMSbnMoADeS3Fu4XvtYJqKivErdzgpuGGs+80BLLYjXXwTkMibgV/KkUDZl6Y9HioLTfG65uUek7UWUm7AmXIfDUo3XW9jERJBkWIFjc7hnw/jwH42+dKwc7EEdtuHxdrF/b1kw7kjIrNcFvy7HIxLTuC5EBPPRNRlSSxX50SrHvZ37LqHPOwFPeunn0/LNk/jcnHE44njbeC1mIrdjItSYRxkXR6liN1dhwvDwLMKUHTNFug3TSyFwBBke5WeQnM0YKuF3OysvgqzA9zUEIjUUwqWi/R20dvQjWb6mJ5J9cSg1ngS1yPd2otsZRPc5PQYXUOeSbv9bBF57JNszD9QUGP+/JvoxDepENFQ==; 5:UN2o2hCVFQ1sgbIj+1ZfB9f7QS+aUhL9fLfQdEF/rCU2DdFlOpMWQ2zEBmm3+y+GF1yb5cWUTOT/XPELwDKD+ts9jCqTnn6ibYj0Q3Bh4vi+I1dIMSS9LJSqVlz9RrrWki2ggIdKmnsSHHG0aNNzvXwCEP3yzUCaGqEDaXblVVs=; 7:q98zfKsnFuUQrr7s6ZWuZyf1QUJbL72M8ttE1PnUYiIpOvNt3B7dllgw6CbTbO+uDQAEMHU316gMfCT4uxl1U4HX8e3oWcbHtm4rF0/bs13DFvE5QEICTXp1DfOmYsZeTeR2qG8JrtM8javdla+huA== x-ms-office365-filtering-correlation-id: 70739860-93e6-4c80-bb33-08d64eca6309 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390098)(7020095)(4652040)(8989299)(5600074)(711020)(4618075)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7153060)(7193020); SRVR:AM6PR04MB5269; x-ms-traffictypediagnostic: AM6PR04MB5269: x-microsoft-antispam-prvs: x-ms-exchange-senderadcheck: 1 x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(8211001083)(6040522)(2401047)(5005006)(8121501046)(3231442)(944501410)(52105112)(3002001)(10201501046)(93006095)(93001095)(6055026)(148016)(149066)(150057)(6041310)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123558120)(20161123564045)(20161123560045)(20161123562045)(201708071742011)(7699051)(76991095); SRVR:AM6PR04MB5269; BCL:0; PCL:0; RULEID:; SRVR:AM6PR04MB5269; x-forefront-prvs: 08626BE3A5 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(346002)(376002)(136003)(396003)(366004)(39860400002)(189003)(199004)(305945005)(7736002)(36756003)(5660300001)(7416002)(68736007)(2906002)(4326008)(8936002)(14454004)(256004)(54906003)(53936002)(6436002)(71200400001)(110136005)(71190400001)(6512007)(316002)(2616005)(476003)(446003)(11346002)(486006)(25786009)(2501003)(2201001)(86362001)(52116002)(76176011)(6506007)(102836004)(386003)(186003)(106356001)(26005)(2900100001)(81156014)(81166006)(105586002)(6486002)(8676002)(99286004)(66066001)(6116002)(3846002)(1076002)(478600001)(97736004)(921003)(1121003); DIR:OUT; SFP:1101; SCL:1; SRVR:AM6PR04MB5269; H:AM6PR04MB5781.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: 9HTjv+z2bYw/wa6pqkV2O2iSJptTBF8dqQixbJX9YB/RJu6l3j3hkOjYtGRt7y6rw0XKrFJY8K1AFZYR+vHZ4V3/3NZ3MfBNA9KFn3Za+wToOVJtw8DfvqzDJ+JUsAXsQbiBkTATc4uFmwsuxDoh19KWUJ6RGlor/1p1EqylegbdyLaBbR0qvDYK3V5yy7BrpqU6BDnxhsx+0C2+M36wrRS2L4k4AVfkbl0R5u8wfdxqzM/W5m9ZQkBD1KWGvwJaW4AR4KIuLpS+CDwqkNLOPFVjltokq8vrdY5jgB0mWovVKtrj2mc2RQzgOAK2QPm/QeeD734Gwo0PIn3eUXWVCB/yN+M6tFnFCpGdQgq3LK0= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 70739860-93e6-4c80-bb33-08d64eca6309 X-MS-Exchange-CrossTenant-originalarrivaltime: 20 Nov 2018 09:27:27.4102 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR04MB5269 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Hou Zhiqiang Sometimes there is not a PCIe Endpoint in the PCIe slot, so do not exit when the PCIe link is not up. And degrade the print level of link up info. Signed-off-by: Hou Zhiqiang reviewed-by: Minghuan Lian --- V2: - no change drivers/pci/controller/mobiveil/pcie-mobiveil-host.c | 1 - drivers/pci/controller/mobiveil/pcie-mobiveil.c | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c b/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c index 1ae82e790562..d1765d572f44 100644 --- a/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c @@ -596,7 +596,6 @@ int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie) ret = mobiveil_bringup_link(pcie); if (ret) { dev_info(dev, "link bring-up failed\n"); - goto error; } /* setup the kernel resources for the newly added PCIe root bus */ diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.c b/drivers/pci/controller/mobiveil/pcie-mobiveil.c index ee678a60825d..370658d6546d 100644 --- a/drivers/pci/controller/mobiveil/pcie-mobiveil.c +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.c @@ -222,7 +222,7 @@ int mobiveil_bringup_link(struct mobiveil_pcie *pcie) usleep_range(LINK_WAIT_MIN, LINK_WAIT_MAX); } - dev_err(&pcie->pdev->dev, "link never came up\n"); + dev_info(&pcie->pdev->dev, "link never came up\n"); return -ETIMEDOUT; } From patchwork Tue Nov 20 09:27:33 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Z.Q. Hou" X-Patchwork-Id: 1000353 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=nxp.com header.i=@nxp.com header.b="NzqOilEh"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42zgPR3YtKz9s8F for ; Tue, 20 Nov 2018 20:28:43 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727589AbeKTTzt (ORCPT ); Tue, 20 Nov 2018 14:55:49 -0500 Received: from mail-eopbgr30040.outbound.protection.outlook.com ([40.107.3.40]:36159 "EHLO EUR03-AM5-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727619AbeKTTzt (ORCPT ); Tue, 20 Nov 2018 14:55:49 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=YDw3kEaa0DQsETyfo+oSPAgHHhgLI1NCNUESfmlPsyc=; b=NzqOilEhG4Hn9EPrNKF79c1QqWQPunTPOz94b6gwq7wnqmppwCWmxNWsWGYBDCiOfkqf/KUhmQrglL8da/AHkNIVuMLd9vdgG3/HijHf+dfCTnH2aRAdrLRKu+10o+0uzy9umtUkY1izOMFf6b7QLNDhn9vVVCdH80+YmMVaVg8= Received: from AM6PR04MB5781.eurprd04.prod.outlook.com (20.179.2.80) by AM6PR04MB4775.eurprd04.prod.outlook.com (20.177.32.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1339.21; Tue, 20 Nov 2018 09:27:33 +0000 Received: from AM6PR04MB5781.eurprd04.prod.outlook.com ([fe80::29b5:b3ed:3854:cf1c]) by AM6PR04MB5781.eurprd04.prod.outlook.com ([fe80::29b5:b3ed:3854:cf1c%4]) with mapi id 15.20.1339.026; Tue, 20 Nov 2018 09:27:33 +0000 From: "Z.q. Hou" To: "linux-pci@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "bhelgaas@google.com" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "l.subrahmanya@mobiveil.co.in" , "shawnguo@kernel.org" , Leo Li , "lorenzo.pieralisi@arm.com" , "catalin.marinas@arm.com" , "will.deacon@arm.com" CC: Mingkai Hu , "M.h. Lian" , Xiaowei Bao , "Z.q. Hou" Subject: [PATCHv2 19/25] PCI: mobiveil: disabled IB and OB windows set by bootloader Thread-Topic: [PATCHv2 19/25] PCI: mobiveil: disabled IB and OB windows set by bootloader Thread-Index: AQHUgLNEY3zDU/qMo0Oy4NY1Qyg81w== Date: Tue, 20 Nov 2018 09:27:33 +0000 Message-ID: <20181120092615.11680-20-Zhiqiang.Hou@nxp.com> References: <20181120092615.11680-1-Zhiqiang.Hou@nxp.com> In-Reply-To: <20181120092615.11680-1-Zhiqiang.Hou@nxp.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: HK2PR03CA0050.apcprd03.prod.outlook.com (2603:1096:202:17::20) To AM6PR04MB5781.eurprd04.prod.outlook.com (2603:10a6:20b:aa::16) authentication-results: spf=none (sender IP is ) smtp.mailfrom=zhiqiang.hou@nxp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [119.31.174.73] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; AM6PR04MB4775; 6:Q4KzPdFe3J+y1T/1qtn4Z/74yD5vZAjz9tx4QrCG7JFVXwo2YDowfNVt9xFrTGJ/jhXal5FKgm3kg0qarHJ3Ufd8wZuT7H8KXNRkMaP0pZgjXhIPVAeJHfUNj0hOWi0iPjAb3xs7Oi5b61/LcgbdJeVABbSVaOiYEYSLHhvQVKGhxcpzq2IK5CqOh7aVo9jSfseItDHkwOpa+0OL3wwNzPEzuKzp8+tC13O0jtebUlgjuyl4g+ftZxoWXUa+K93aRx6J0tQjZQ9D+gTrFfNIOZu94RJUMyuWJWTki7X8k8q+G+BvWbrU/mt6tBr3PfYX7HRUoFS4jNJb/tcOF5BrjyI2J/l8nkaZm9/CN6T4EdJ8ulc9fZl7p2wo1KRpjCbdeaoT7usdc5/Ig+I82M0wG2aFZwIeh0JAs7G2Z3M9nlYm+MKv/bVV8j+xUj3Q9UDaBdbjjbsIJlkmmPqCPqMYWw==; 5:UpPggIRmA5xf4owFMdK51G8XEBVGMmlxBneAb9Sh5d7JWGUo9cJs5x/r08VF8ufbvvpPjDynvLV2Kf0n0+ItirETc2Bpkau3La/1rs6DnJrvMCtUoxjLqgWsJRziDnZ1kPuoBf8YggIxnmCb1/vqcXuVlneRG/gfSNDxVr0m3HA=; 7:4oClPQx7FfkWhivydoCSd1z8m9+Cr36RylQ/z0pFzi3DaYDT9AQHNjde4Ds2+swKBplrR+nwbteKL43BSRRGHQWsEawzCsCXj2HSFuoHxjCQny7Q4uo4XqmQbwtIG/LvkPcivANmd8+i0XFgCs+/yw== x-ms-office365-filtering-correlation-id: beb93c8a-4d22-47b9-3044-08d64eca66a9 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390098)(7020095)(4652040)(8989299)(5600074)(711020)(4618075)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7153060)(7193020); SRVR:AM6PR04MB4775; x-ms-traffictypediagnostic: AM6PR04MB4775: x-microsoft-antispam-prvs: x-ms-exchange-senderadcheck: 1 x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(8211001083)(6040522)(2401047)(8121501046)(5005006)(93006095)(93001095)(3231442)(944501410)(52105112)(3002001)(10201501046)(6055026)(148016)(149066)(150057)(6041310)(20161123562045)(20161123564045)(20161123560045)(20161123558120)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(201708071742011)(7699051)(76991095); SRVR:AM6PR04MB4775; BCL:0; PCL:0; RULEID:; SRVR:AM6PR04MB4775; x-forefront-prvs: 08626BE3A5 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(366004)(39860400002)(136003)(376002)(396003)(346002)(189003)(199004)(66066001)(1076002)(2900100001)(68736007)(8676002)(6486002)(5660300001)(8936002)(6116002)(3846002)(2501003)(97736004)(81166006)(26005)(186003)(81156014)(105586002)(7416002)(102836004)(2906002)(386003)(6506007)(7736002)(305945005)(106356001)(6512007)(76176011)(36756003)(4326008)(99286004)(52116002)(14444005)(25786009)(575784001)(110136005)(54906003)(2616005)(86362001)(53936002)(446003)(11346002)(256004)(2201001)(6436002)(486006)(71190400001)(71200400001)(478600001)(316002)(476003)(14454004)(921003)(1121003); DIR:OUT; SFP:1101; SCL:1; SRVR:AM6PR04MB4775; H:AM6PR04MB5781.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: LhdnLkClXRsFFqPKipGSxXJwgpHMWOodwiY70PrYvrnUrw+/DHx/48uM87z46ww18Wq0IpJiT0f+WFBe3C4PT3O9v5x4DsZWQQktq6Wry1paXZG0Ay9IOo81Iz0NatsCHFZASKbrZOg3OQTPRmCNmVfCZEp8mpw17TUBjy/BgGjmLMT6CwbT/dIVRvCZRRveBN9GItHF5JGO7WQytcRQTK9QhC9poVa/Mdu1R1TvZocy7OV9FMbTTav+UcVQPtSLXAKJV0xdmPvjuraV7ulFm5XSPgUqG8VGYNzJenKZpctpKpF7DwMplpXcnEGwYKAzcpmWwRb3+qkaHkrZO7z3YvspHgDsDDp23SQZIFMbJgo= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: beb93c8a-4d22-47b9-3044-08d64eca66a9 X-MS-Exchange-CrossTenant-originalarrivaltime: 20 Nov 2018 09:27:33.4728 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR04MB4775 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Hou Zhiqiang Disabled all inbound and outbound windows before set up the windows in kernel, in case transactions match the window set by bootloader. Signed-off-by: Hou Zhiqiang reviewed-by: Minghuan Lian --- V2: - no change .../controller/mobiveil/pcie-mobiveil-host.c | 7 +++++++ .../pci/controller/mobiveil/pcie-mobiveil.c | 18 ++++++++++++++++++ .../pci/controller/mobiveil/pcie-mobiveil.h | 2 ++ 3 files changed, 27 insertions(+) diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c b/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c index d1765d572f44..d028cdf31d0e 100644 --- a/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c @@ -221,6 +221,13 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie) { u32 value, pab_ctrl, type; struct resource_entry *win; + int i; + + /* Disable all inbound/outbound windows */ + for (i = 0; i < pcie->apio_wins; i++) + mobiveil_pcie_disable_ob_win(pcie, i); + for (i = 0; i < pcie->ppio_wins; i++) + mobiveil_pcie_disable_ib_win(pcie, i); /* setup bus numbers */ value = csr_readl(pcie, PCI_PRIMARY_BUS); diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.c b/drivers/pci/controller/mobiveil/pcie-mobiveil.c index 370658d6546d..49d471b75925 100644 --- a/drivers/pci/controller/mobiveil/pcie-mobiveil.c +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.c @@ -226,3 +226,21 @@ int mobiveil_bringup_link(struct mobiveil_pcie *pcie) return -ETIMEDOUT; } + +void mobiveil_pcie_disable_ib_win(struct mobiveil_pcie *pci, int win_num) +{ + u32 val; + + val = csr_readl(pci, PAB_PEX_AMAP_CTRL(win_num)); + val &= ~(1 << AMAP_CTRL_EN_SHIFT); + csr_writel(pci, val, PAB_PEX_AMAP_CTRL(win_num)); +} + +void mobiveil_pcie_disable_ob_win(struct mobiveil_pcie *pci, int win_num) +{ + u32 val; + + val = csr_readl(pci, PAB_AXI_AMAP_CTRL(win_num)); + val &= ~(1 << WIN_ENABLE_SHIFT); + csr_writel(pci, val, PAB_AXI_AMAP_CTRL(win_num)); +} diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.h b/drivers/pci/controller/mobiveil/pcie-mobiveil.h index eb4cb61291a8..81685840b378 100644 --- a/drivers/pci/controller/mobiveil/pcie-mobiveil.h +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.h @@ -171,6 +171,8 @@ void program_ob_windows(struct mobiveil_pcie *pcie, int win_num, u64 cpu_addr, u64 pci_addr, u32 type, u64 size); void program_ib_windows(struct mobiveil_pcie *pcie, int win_num, u64 cpu_addr, u64 pci_addr, u32 type, u64 size); +void mobiveil_pcie_disable_ob_win(struct mobiveil_pcie *pci, int win_num); +void mobiveil_pcie_disable_ib_win(struct mobiveil_pcie *pci, int win_num); u32 csr_read(struct mobiveil_pcie *pcie, u32 off, size_t size); void csr_write(struct mobiveil_pcie *pcie, u32 val, u32 off, size_t size); From patchwork Tue Nov 20 09:27:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Z.Q. Hou" X-Patchwork-Id: 1000345 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=nxp.com header.i=@nxp.com header.b="jSJch3rV"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42zgNL4GVKz9s1x for ; Tue, 20 Nov 2018 20:27:46 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727680AbeKTTzx (ORCPT ); Tue, 20 Nov 2018 14:55:53 -0500 Received: from mail-eopbgr30040.outbound.protection.outlook.com ([40.107.3.40]:36159 "EHLO EUR03-AM5-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727453AbeKTTzu (ORCPT ); Tue, 20 Nov 2018 14:55:50 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=n7RFA8zuQdtBM4WyBZkYqo4kXC2Ymw2uQIGPx4o3Kkk=; b=jSJch3rVHHQX+CqnE1/qbyg6I9QEUn/MHZ0JPteprKFa6t3inYLfO+r0XECUJCnV8lDQfruTN/iyzBlfpgcYzNWRgKxJp8nU3UNltBxOHBYLWOruDyQUuUqf8IQIZ1VumRO+LAvVCkmlLUnGeg99Yuh1ApiWpNnyE/F00DfXg9c= Received: from AM6PR04MB5781.eurprd04.prod.outlook.com (20.179.2.80) by AM6PR04MB4775.eurprd04.prod.outlook.com (20.177.32.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1339.21; Tue, 20 Nov 2018 09:27:39 +0000 Received: from AM6PR04MB5781.eurprd04.prod.outlook.com ([fe80::29b5:b3ed:3854:cf1c]) by AM6PR04MB5781.eurprd04.prod.outlook.com ([fe80::29b5:b3ed:3854:cf1c%4]) with mapi id 15.20.1339.026; Tue, 20 Nov 2018 09:27:39 +0000 From: "Z.q. Hou" To: "linux-pci@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "bhelgaas@google.com" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "l.subrahmanya@mobiveil.co.in" , "shawnguo@kernel.org" , Leo Li , "lorenzo.pieralisi@arm.com" , "catalin.marinas@arm.com" , "will.deacon@arm.com" CC: Mingkai Hu , "M.h. Lian" , Xiaowei Bao , "Z.q. Hou" Subject: [PATCHv2 20/25] PCI: mobiveil: add Byte and Half-Word width register accessors Thread-Topic: [PATCHv2 20/25] PCI: mobiveil: add Byte and Half-Word width register accessors Thread-Index: AQHUgLNHzqe5uulTrkKuclVdC+mE8w== Date: Tue, 20 Nov 2018 09:27:39 +0000 Message-ID: <20181120092615.11680-21-Zhiqiang.Hou@nxp.com> References: <20181120092615.11680-1-Zhiqiang.Hou@nxp.com> In-Reply-To: <20181120092615.11680-1-Zhiqiang.Hou@nxp.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: HK2PR03CA0050.apcprd03.prod.outlook.com (2603:1096:202:17::20) To AM6PR04MB5781.eurprd04.prod.outlook.com (2603:10a6:20b:aa::16) authentication-results: spf=none (sender IP is ) smtp.mailfrom=zhiqiang.hou@nxp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [119.31.174.73] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; AM6PR04MB4775; 6:AmZySUidA3z2jtHLn5BeNNLETl+MQEXG+Um2mAPxAd2kBGwPxTwIKoome4oOSN2V1IV/TyFDKOH48Lxhzv079HuHvqXWWOjRayOglhaW8Zhi5LVGYqzrnO5m9TboAfOsR73xhCGCeFZGLARTBWqfdaRQLogB8Y5F/1b4jA00A7pX/cgsWiQ7K3JfQAAMNbDSRXesIztUo2bbmpzW2Y9BFbPZEvQxoT/gIAi9Nk7bxrtP8+JpwrdwPVlbupMztcG0MYeaKY93RLxe7pKs7xcMTPLVDryCxojfKP80XHC+ZNI8PJhCTzkoB1ZogPRpfG/AWMy5m4LrjoiNHfDnv1iNQIiNQfiAAnROhGUuVxJUNGPv475HMGp18LEZHIiuTJWPDt3XjVt7ESOsT/tVed2f/IeyiVNm6U3OTBrQY5BqDF9UUi5p1v51DhGONOoNqtp32B4VFBhq3dNgaebCC8y5YQ==; 5:yr27SlgQ8/ycbkp+UdyJQVDtdaID1YSCtRe8Sb7I8YR/bTAPEvU+9dIpyetxrNdbNxIaFtpPoL7bm2A7KJoCLxKvD1w3oBpfF4/oyY776zSgmern9FqSbrNZZX1+ecX1AI4hbB9m64LCpDgB1AxCPPHnGGIo1w7ucU7EhmuRhbk=; 7:RFMaA6yqrVGfW0MCT1J0GDJvAf92BrVT7cunQe/AfOpQePq7rIGlVmsCTTrL6SbPp8CoMop2ErV3fHx5ezezYuNu+eT4y85Z8a+65GvLON6FnlFzQVKYphr/Vr11gaYKHEJ8sARXJP4r7nXs1d/Fog== x-ms-office365-filtering-correlation-id: 61c683ec-23b3-41cf-e0dc-08d64eca6a43 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390098)(7020095)(4652040)(8989299)(5600074)(711020)(4618075)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7153060)(7193020); SRVR:AM6PR04MB4775; x-ms-traffictypediagnostic: AM6PR04MB4775: x-microsoft-antispam-prvs: x-ms-exchange-senderadcheck: 1 x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(8211001083)(6040522)(2401047)(8121501046)(5005006)(93006095)(93001095)(3231442)(944501410)(52105112)(3002001)(10201501046)(6055026)(148016)(149066)(150057)(6041310)(20161123562045)(20161123564045)(20161123560045)(20161123558120)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(201708071742011)(7699051)(76991095); SRVR:AM6PR04MB4775; BCL:0; PCL:0; RULEID:; SRVR:AM6PR04MB4775; x-forefront-prvs: 08626BE3A5 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(366004)(39860400002)(136003)(376002)(396003)(346002)(189003)(199004)(66066001)(1076002)(2900100001)(68736007)(8676002)(6486002)(5660300001)(8936002)(6116002)(3846002)(2501003)(97736004)(81166006)(26005)(186003)(81156014)(105586002)(7416002)(102836004)(2906002)(386003)(6506007)(7736002)(305945005)(106356001)(6512007)(76176011)(36756003)(4326008)(99286004)(52116002)(25786009)(110136005)(54906003)(2616005)(86362001)(53936002)(446003)(11346002)(256004)(2201001)(6436002)(486006)(71190400001)(71200400001)(478600001)(316002)(476003)(14454004)(921003)(1121003); DIR:OUT; SFP:1101; SCL:1; SRVR:AM6PR04MB4775; H:AM6PR04MB5781.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: KxAbea4+YS65QY0wrgWkYzJQmqhCNLbDfkZ6UNGfSc6jZJWu9agsmvgt/J9fghSZEfywum9VQ76v//z2NonWgMEL4qlq3H0tA7CB7SS1/YVJ+oxpU8SYNyreUBoGHKiU3EW6YLQGiQbff6tyA0X/vjXXAQJdNaOOv7eGXRArYRYHrjwmvhqymTHKtT8Iu7poGPI9oSYsak0UazC7+g0G20maaBkhvxqAS3mDvsgqpyGjmQ8WeP7HqJsCD1PrOPjBi3hbaZ9UvREtCvl0BCirfDF+Sy7ZtaWjAoRguhm3I5hfFMx9SZ5+i23Uc5fVo9YXkI/72sl8uGRZRalVhhm5OLzyioZFUBTBdZIVOUoTfZ4= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 61c683ec-23b3-41cf-e0dc-08d64eca6a43 X-MS-Exchange-CrossTenant-originalarrivaltime: 20 Nov 2018 09:27:39.5353 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR04MB4775 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Hou Zhiqiang As there are some Byte and Half-Work width registers in PCIe configuration space, add Byte and Half-Word width register accessors. Signed-off-by: Hou Zhiqiang reviewed-by: Minghuan Lian --- V2: - no change .../pci/controller/mobiveil/pcie-mobiveil.h | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.h b/drivers/pci/controller/mobiveil/pcie-mobiveil.h index 81685840b378..933c2f34bc52 100644 --- a/drivers/pci/controller/mobiveil/pcie-mobiveil.h +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.h @@ -181,9 +181,29 @@ static inline u32 csr_readl(struct mobiveil_pcie *pcie, u32 off) return csr_read(pcie, off, 0x4); } +static inline u32 csr_readw(struct mobiveil_pcie *pcie, u32 off) +{ + return csr_read(pcie, off, 0x2); +} + +static inline u32 csr_readb(struct mobiveil_pcie *pcie, u32 off) +{ + return csr_read(pcie, off, 0x1); +} + static inline void csr_writel(struct mobiveil_pcie *pcie, u32 val, u32 off) { csr_write(pcie, val, off, 0x4); } +static inline void csr_writew(struct mobiveil_pcie *pcie, u32 val, u32 off) +{ + csr_write(pcie, val, off, 0x2); +} + +static inline void csr_writeb(struct mobiveil_pcie *pcie, u32 val, u32 off) +{ + csr_write(pcie, val, off, 0x1); +} + #endif /* _PCIE_MOBIVEIL_H */ From patchwork Tue Nov 20 09:27:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Z.Q. Hou" X-Patchwork-Id: 1000352 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=nxp.com header.i=@nxp.com header.b="Z4eL2l+7"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42zgPH1GK7z9s1x for ; Tue, 20 Nov 2018 20:28:35 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728099AbeKTTz6 (ORCPT ); Tue, 20 Nov 2018 14:55:58 -0500 Received: from mail-eopbgr30082.outbound.protection.outlook.com ([40.107.3.82]:29684 "EHLO EUR03-AM5-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727453AbeKTTz5 (ORCPT ); Tue, 20 Nov 2018 14:55:57 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=6GGE+D1K97Uim7BzdeFvPAUZXAd8GUxbz3cRM28RI7M=; b=Z4eL2l+7wKihGp26NodvVE3TpeD0VOkVyKeAGX8fH+014Rqy4oG6H66OPyQAfh1E5zFuhEJqWMz7GFAkDi+ybfr+/eS0fU8u8HGB8kcx+vopkaCy0b0H2HTsY6nsFYJ0pVleWjzTke1f7ppK30i/aIX5/ss+RtCp1WEQTP/6cCQ= Received: from AM6PR04MB5781.eurprd04.prod.outlook.com (20.179.2.80) by AM6PR04MB4775.eurprd04.prod.outlook.com (20.177.32.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1339.21; Tue, 20 Nov 2018 09:27:45 +0000 Received: from AM6PR04MB5781.eurprd04.prod.outlook.com ([fe80::29b5:b3ed:3854:cf1c]) by AM6PR04MB5781.eurprd04.prod.outlook.com ([fe80::29b5:b3ed:3854:cf1c%4]) with mapi id 15.20.1339.026; Tue, 20 Nov 2018 09:27:45 +0000 From: "Z.q. Hou" To: "linux-pci@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "bhelgaas@google.com" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "l.subrahmanya@mobiveil.co.in" , "shawnguo@kernel.org" , Leo Li , "lorenzo.pieralisi@arm.com" , "catalin.marinas@arm.com" , "will.deacon@arm.com" CC: Mingkai Hu , "M.h. Lian" , Xiaowei Bao , "Z.q. Hou" Subject: [PATCHv2 21/25] PCI: mobiveil: make mobiveil_host_init can be used to re-init host Thread-Topic: [PATCHv2 21/25] PCI: mobiveil: make mobiveil_host_init can be used to re-init host Thread-Index: AQHUgLNL3BLuWxLGBEm5/AH+TXpIjA== Date: Tue, 20 Nov 2018 09:27:45 +0000 Message-ID: <20181120092615.11680-22-Zhiqiang.Hou@nxp.com> References: <20181120092615.11680-1-Zhiqiang.Hou@nxp.com> In-Reply-To: <20181120092615.11680-1-Zhiqiang.Hou@nxp.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: HK2PR03CA0050.apcprd03.prod.outlook.com (2603:1096:202:17::20) To AM6PR04MB5781.eurprd04.prod.outlook.com (2603:10a6:20b:aa::16) authentication-results: spf=none (sender IP is ) smtp.mailfrom=zhiqiang.hou@nxp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [119.31.174.73] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; AM6PR04MB4775; 6:KRj/yIcmp2taLLk1UAI1CyyPcziuZoBQ3bhnyRBIWwKx56dhoY6rbA2iU0Qje8tAz32QPBwpG26PUZqJtHXNUAkbVHw00A+mXC4fhEiGJCyM3YTJrTFrATUFjo6InrkegNanpcUEErVTRCq3KPxJAFRSakjo0OIUic4NcAxb0ymbiXTqlW4+7l7pJzPAvASuSX6bcfcuy8od5i5IsJHH6xzhaWsRXkn7aXgE7pRsVnnN05aN1/67WdMbgN4eRgM8bSyMZEYVesWVZpL5piwPu3zjoObpRoUbsqR5VOnlxfyll63Gxzg6fS27Bwjnrg/ykrpjsAalJ31OYUmANCDyVaJJZsNcR7rsyX5tCcBkp+578Yzz//6YYRNcegx1Ddixzblggwg5yUVKpjxNMbbfLDUUr/ELcdqwRBJtWFcLHSIN6gRCqdwEZ54gsDPwrrRtNItSAsy3nYm09DqxQgJXcQ==; 5:VsoKnTB/phS4OLtdGj+fqiA7eie6b+qChMYso7g21uC9Bop3YH30Nx50Lxhd24eEk/PEMZKgj6jasjbmBCQ8tLQT8BF0g+++Qf+Py+gcwN4xTb3VXT613QRrRj8e43sT76GBwrq0K1Xia3bMqNI8yTn1V7kSt4hy3KHpwUtOivg=; 7:v0Z+87SzIBCmHWu6uqN7vG5URm1d2Dx7UjgJc5TM2Zqfov0/FHG1W7fGRhRwXM6T3FoDIZZ3a9JovSaxl9aIYmDndS1jF86VPm//tT9RN7h1uT0M/zlFe/jUR+e3hHG4i644TGhV8GG9x/oxlBe6aQ== x-ms-office365-filtering-correlation-id: 7e2c51ec-4b23-4e51-f3c0-08d64eca6de0 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390098)(7020095)(4652040)(8989299)(5600074)(711020)(4618075)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7153060)(7193020); SRVR:AM6PR04MB4775; x-ms-traffictypediagnostic: AM6PR04MB4775: x-microsoft-antispam-prvs: x-ms-exchange-senderadcheck: 1 x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(8211001083)(6040522)(2401047)(8121501046)(5005006)(93006095)(93001095)(3231442)(944501410)(52105112)(3002001)(10201501046)(6055026)(148016)(149066)(150057)(6041310)(20161123562045)(20161123564045)(20161123560045)(20161123558120)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(201708071742011)(7699051)(76991095); SRVR:AM6PR04MB4775; BCL:0; PCL:0; RULEID:; SRVR:AM6PR04MB4775; x-forefront-prvs: 08626BE3A5 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(366004)(39860400002)(136003)(376002)(396003)(346002)(189003)(199004)(66066001)(1076002)(2900100001)(68736007)(8676002)(6486002)(5660300001)(8936002)(6116002)(3846002)(2501003)(97736004)(81166006)(26005)(186003)(81156014)(105586002)(7416002)(102836004)(2906002)(386003)(6506007)(7736002)(305945005)(106356001)(6512007)(76176011)(36756003)(4326008)(99286004)(52116002)(14444005)(25786009)(575784001)(110136005)(54906003)(2616005)(86362001)(53936002)(446003)(11346002)(256004)(2201001)(6436002)(486006)(71190400001)(71200400001)(478600001)(316002)(476003)(14454004)(921003)(1121003); DIR:OUT; SFP:1101; SCL:1; SRVR:AM6PR04MB4775; H:AM6PR04MB5781.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: o1p0SjrnmzMaStZfYMg58NrSXimv02zn6aIO5AnLOoRuE/4HVUM3a/tv2lmqwzw9Z3fRxTNGiaDhVN8Bn0/HofCd/o84ODcaLZ5Y1kEQl4PwaZfBThj3JUwlxU5O2n6GWUWkPxr6zcJwMulRNzHgN+OH0qiBFAgyG8p2vC0tZDapEA2B5P8IlUQuXNR39DuPFVThBbhw9pJ1W/OWJpXhw0agqkQJnfJmnfx+llAkJvc31HarNLyQ3qKSJWXkAW2xGQAp/qjfDAGIITcvu61QSTkkTi1prjEPRfO5qJAKdXk1gcBLLJfo3o23o8Itx9+26g8IXEmF1flIT0T3/D9al+g8SPkM5bq05tBB89hbTSA= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 7e2c51ec-4b23-4e51-f3c0-08d64eca6de0 X-MS-Exchange-CrossTenant-originalarrivaltime: 20 Nov 2018 09:27:45.6135 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR04MB4775 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Hou Zhiqiang Make the mobiveil_host_init function can be used to re-init host controller's PAB and GPEX CSR register block, as NXP integrated Mobiveil IP has to reset and then re-init the PAB and GPEX CSR registers upon Hot-reset. Signed-off-by: Hou Zhiqiang reviewed-by: Minghuan Lian --- V2: - Reset the statistic of IB/OB windows configured. - Change the type of member 'resources' to pointer to record the parsed resources for re-init the outbound windows. .../controller/mobiveil/pcie-mobiveil-host.c | 32 +++++++++++-------- .../pci/controller/mobiveil/pcie-mobiveil.h | 3 +- 2 files changed, 20 insertions(+), 15 deletions(-) diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c b/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c index d028cdf31d0e..c85f00d3cfcf 100644 --- a/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c @@ -217,7 +217,7 @@ static void mobiveil_pcie_enable_msi(struct mobiveil_pcie *pcie) writel_relaxed(1, pcie->apb_csr_base + MSI_ENABLE_OFFSET); } -static int mobiveil_host_init(struct mobiveil_pcie *pcie) +int mobiveil_host_init(struct mobiveil_pcie *pcie, bool reinit) { u32 value, pab_ctrl, type; struct resource_entry *win; @@ -229,11 +229,16 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie) for (i = 0; i < pcie->ppio_wins; i++) mobiveil_pcie_disable_ib_win(pcie, i); - /* setup bus numbers */ - value = csr_readl(pcie, PCI_PRIMARY_BUS); - value &= 0xff000000; - value |= 0x00ff0100; - csr_writel(pcie, value, PCI_PRIMARY_BUS); + pcie->ib_wins_configured = 0; + pcie->ob_wins_configured = 0; + + if (!reinit) { + /* setup bus numbers */ + value = csr_readl(pcie, PCI_PRIMARY_BUS); + value &= 0xff000000; + value |= 0x00ff0100; + csr_writel(pcie, value, PCI_PRIMARY_BUS); + } /* * program Bus Master Enable Bit in Command Register in PAB Config @@ -279,7 +284,7 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie) program_ib_windows(pcie, WIN_NUM_0, 0, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE); /* Get the I/O and memory ranges from DT */ - resource_list_for_each_entry(win, &pcie->resources) { + resource_list_for_each_entry(win, pcie->resources) { if (resource_type(win->res) == IORESOURCE_MEM) { type = MEM_WINDOW_TYPE; } else if (resource_type(win->res) == IORESOURCE_IO) { @@ -550,8 +555,6 @@ int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie) resource_size_t iobase; int ret; - INIT_LIST_HEAD(&pcie->resources); - ret = mobiveil_pcie_parse_dt(pcie); if (ret) { dev_err(dev, "Parsing DT failed, ret: %x\n", ret); @@ -565,17 +568,19 @@ int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie) /* parse the host bridge base addresses from the device tree file */ ret = devm_of_pci_get_host_bridge_resources(dev, 0, 0xff, - &pcie->resources, &iobase); + &bridge->windows, &iobase); if (ret) { dev_err(dev, "Getting bridge resources failed\n"); return ret; } + pcie->resources = &bridge->windows; + /* * configure all inbound and outbound windows and prepare the RC for * config access */ - ret = mobiveil_host_init(pcie); + ret = mobiveil_host_init(pcie, false); if (ret) { dev_err(dev, "Failed to initialize host\n"); goto error; @@ -587,12 +592,11 @@ int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie) goto error; } - ret = devm_request_pci_bus_resources(dev, &pcie->resources); + ret = devm_request_pci_bus_resources(dev, pcie->resources); if (ret) goto error; /* Initialize bridge */ - list_splice_init(&pcie->resources, &bridge->windows); bridge->dev.parent = dev; bridge->sysdata = pcie; bridge->busnr = pcie->rp.root_bus_nr; @@ -619,6 +623,6 @@ int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie) return 0; error: - pci_free_resource_list(&pcie->resources); + pci_free_resource_list(pcie->resources); return ret; } diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.h b/drivers/pci/controller/mobiveil/pcie-mobiveil.h index 933c2f34bc52..0f5303962e88 100644 --- a/drivers/pci/controller/mobiveil/pcie-mobiveil.h +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.h @@ -152,7 +152,7 @@ struct mobiveil_pab_ops { struct mobiveil_pcie { struct platform_device *pdev; - struct list_head resources; + struct list_head *resources; void __iomem *csr_axi_slave_base; /* PAB registers base */ phys_addr_t pcie_reg_base; /* Physical PCIe Controller Base */ void __iomem *apb_csr_base; /* MSI register base */ @@ -165,6 +165,7 @@ struct mobiveil_pcie { }; int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie); +int mobiveil_host_init(struct mobiveil_pcie *pcie, bool reinit); bool mobiveil_pcie_link_up(struct mobiveil_pcie *pcie); int mobiveil_bringup_link(struct mobiveil_pcie *pcie); void program_ob_windows(struct mobiveil_pcie *pcie, int win_num, u64 cpu_addr, From patchwork Tue Nov 20 09:27:51 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Z.Q. Hou" X-Patchwork-Id: 1000347 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=nxp.com header.i=@nxp.com header.b="J3SduIdN"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42zgNh1myTz9s1x for ; Tue, 20 Nov 2018 20:28:04 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727741AbeKTT4E (ORCPT ); Tue, 20 Nov 2018 14:56:04 -0500 Received: from mail-eopbgr70040.outbound.protection.outlook.com ([40.107.7.40]:14416 "EHLO EUR04-HE1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727453AbeKTT4E (ORCPT ); Tue, 20 Nov 2018 14:56:04 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=GWwdMdqomvJ7X3B+h406kA3moDPq5ytGZGF7TSk0nDM=; b=J3SduIdNyMWeDjDQG768UDP82RPetMIGk66sbOZvlh6cQ0+i5K2zeW24nUtPj94VxJ0Mw5nVJi/4a8ADdThoBkNsa7aHXf4oW8cLR/V0hU8W0pX/YusAOHXA+t3PeKqSveuNsiFa1Zj4Qh3KQlyct2yePXYDGrlIsgDTcMlS7hE= Received: from AM6PR04MB5781.eurprd04.prod.outlook.com (20.179.2.80) by AM6PR04MB4775.eurprd04.prod.outlook.com (20.177.32.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1339.21; Tue, 20 Nov 2018 09:27:51 +0000 Received: from AM6PR04MB5781.eurprd04.prod.outlook.com ([fe80::29b5:b3ed:3854:cf1c]) by AM6PR04MB5781.eurprd04.prod.outlook.com ([fe80::29b5:b3ed:3854:cf1c%4]) with mapi id 15.20.1339.026; Tue, 20 Nov 2018 09:27:51 +0000 From: "Z.q. Hou" To: "linux-pci@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "bhelgaas@google.com" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "l.subrahmanya@mobiveil.co.in" , "shawnguo@kernel.org" , Leo Li , "lorenzo.pieralisi@arm.com" , "catalin.marinas@arm.com" , "will.deacon@arm.com" CC: Mingkai Hu , "M.h. Lian" , Xiaowei Bao , "Z.q. Hou" Subject: [PATCHv2 22/25] dt-bindings: pci: Add NXP Layerscape SoCs PCIe Gen4 controller Thread-Topic: [PATCHv2 22/25] dt-bindings: pci: Add NXP Layerscape SoCs PCIe Gen4 controller Thread-Index: AQHUgLNPczhc2hMl6EuKyPkcknZC0A== Date: Tue, 20 Nov 2018 09:27:51 +0000 Message-ID: <20181120092615.11680-23-Zhiqiang.Hou@nxp.com> References: <20181120092615.11680-1-Zhiqiang.Hou@nxp.com> In-Reply-To: <20181120092615.11680-1-Zhiqiang.Hou@nxp.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: HK2PR03CA0050.apcprd03.prod.outlook.com (2603:1096:202:17::20) To AM6PR04MB5781.eurprd04.prod.outlook.com (2603:10a6:20b:aa::16) authentication-results: spf=none (sender IP is ) smtp.mailfrom=zhiqiang.hou@nxp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [119.31.174.73] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; AM6PR04MB4775; 6:4fR1Phc9/JNPoLtakd3OiUtHW8C/02MwltS0CbkbHN1f5WSTyPfIANa97MnwzS8yDo5i54/bRbJFB4zXXd+5dWZnzNP/Hm54u55lWATjeMRQZIlUxFiyNrq17ATr07g6WHPe2ghP1AEo5NqzhuugvaBdqV68ZYb1MdS1caOZieuEuZN8cjRuSpJcL9w7DRGAV0b+v2U7hURfvXEh2WIw4TBRmQwzK4EYfNCNEBXecCZpBYE3M8eUPHYu3KlkvMtzLlc/7X2fPhgF1qB2VL6rvBfTdE9IXOZLVEMUGlVWtgZdfzL8yIzq9TS5hq/uBu2W6s/FWqwyPrTxaDFgCk6jUi5qk6oi4dJqUlDvZ6LDgyabZT1FYUlFPJJicGe4KdEVHyyMQFukNEXwHbE7734ShETAMQ15tB0AK8h8XewgJFP+f2T4S75H8wQX04HBjfP4zDGHV1O4ncQqoJKND+m1WA==; 5:us0F8gc3ILlxMx5rKU7M/+Ydg0SP7n2sMssA6OeRIqxuN8kIaTkidO6IrP3e170f+4YV/YTv/ha2apkOc4XIGCj40FkPk65VK7yodfsYJKzekq7xiXBqVl/p7WLFf5yhHyv0KhOtzC/g9x/IfmXdKYzCWXvOs2wQ7uQtv15kJtA=; 7:RSidDyI37FtulDCoUm3ZyHoN+ABcEzq4kE1dlQ+aahr5lI9J4x+DA3p2QgbLTEvV9QsDXfx/LhJBmcoKi5lkDC+e/7IP4p1mWQLb0bFIm3dZ/Zjc8PC7ceh0I9xWXrds3VcXcp1tIA45cB6rnO5eyg== x-ms-office365-filtering-correlation-id: 08048503-fd52-4f92-690a-08d64eca7180 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390098)(7020095)(4652040)(8989299)(5600074)(711020)(4618075)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7153060)(7193020); SRVR:AM6PR04MB4775; x-ms-traffictypediagnostic: AM6PR04MB4775: x-microsoft-antispam-prvs: x-ms-exchange-senderadcheck: 1 x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(8211001083)(6040522)(2401047)(8121501046)(5005006)(93006095)(93001095)(3231442)(944501410)(52105112)(3002001)(10201501046)(6055026)(148016)(149066)(150057)(6041310)(20161123562045)(20161123564045)(20161123560045)(20161123558120)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(201708071742011)(7699051)(76991095); SRVR:AM6PR04MB4775; BCL:0; PCL:0; RULEID:; SRVR:AM6PR04MB4775; x-forefront-prvs: 08626BE3A5 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(6029001)(366004)(39860400002)(136003)(376002)(396003)(346002)(189003)(199004)(66066001)(1076002)(2900100001)(68736007)(8676002)(6486002)(5660300001)(8936002)(6116002)(3846002)(2501003)(97736004)(81166006)(26005)(186003)(81156014)(105586002)(7416002)(102836004)(2906002)(386003)(6506007)(7736002)(305945005)(106356001)(6512007)(76176011)(36756003)(4326008)(99286004)(52116002)(25786009)(575784001)(110136005)(54906003)(2616005)(86362001)(53936002)(446003)(11346002)(256004)(2201001)(6436002)(486006)(71190400001)(71200400001)(478600001)(316002)(476003)(14454004)(921003)(1121003); DIR:OUT; SFP:1101; SCL:1; SRVR:AM6PR04MB4775; H:AM6PR04MB5781.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: cjj/+wth+ycJM5PEbmwekiUmGl79nzeanlzytY/1yxNDuOnVElmBXJ7ybrW8cNxISoYS3lcU4FdmCaUOOjPDu1IawPjGrncJOgUyhnNg01+fwZTTBBsNFCw3fK6qdwEcc2dv6v4jD+R8hqBdjx2NdnoyONAbXKq9T1FAF7r7fAwzx9WD7aX/lDLl7afsWS/NntjAiyvKKpgeJ1WDudtRcL5bBFFwIfYia2ZahfzNuhs/Umkcxknu1KzUsD1EWgntooj5010R+H3BJk0vuBfZXsx4S1xETm3iaIfAX/2K9i8GDpPdBkYuDI1oz9k2qVeyrrcrooh5XfoMAimztdiVwuhVz9eEQDusniBbrytVrJI= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 08048503-fd52-4f92-690a-08d64eca7180 X-MS-Exchange-CrossTenant-originalarrivaltime: 20 Nov 2018 09:27:51.6605 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR04MB4775 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Hou Zhiqiang Add PCIe Gen4 controller DT bindings of NXP Layerscape SoCs. Signed-off-by: Hou Zhiqiang reviewed-by: Minghuan Lian --- V2: - Change to use the layerscape-pci.txt for PCIe Gen4 controller dt-bindings .../bindings/pci/layerscape-pci.txt | 57 +++++++++++++++++++ MAINTAINERS | 8 +++ 2 files changed, 65 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt index 66df1e81e0b8..3ef8836b6e97 100644 --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt @@ -1,4 +1,6 @@ +==================================== Freescale Layerscape PCIe controller +==================================== This PCIe host controller is based on the Synopsys DesignWare PCIe IP and thus inherits all the common properties defined in designware-pcie.txt. @@ -58,3 +60,58 @@ Example: <0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; }; + +=================================== +NXP Layerscape PCIe Gen4 controller +=================================== + +This PCIe controller is based on the Mobiveil PCIe IP and thus inherits all +the common properties defined in mobiveil-pcie.txt. + +Required properties: +- compatible: should contain the platform identifier such as: + "fsl,lx2160a-pcie" +- reg: base addresses and lengths of the PCIe controller register blocks. + "config_axi_slave": PCIe controller registers + "csr_axi_slave": Bridge config registers +- interrupts: A list of interrupt outputs of the controller. Must contain an + entry for each entry in the interrupt-names property. +- interrupt-names: It could include the following entries: + "intr": The interrupt that is asserted for controller interrupts + "aer": Asserted for aer interrupt when chip support the aer interrupt with + none MSI/MSI-X/INTx mode,but there is interrupt line for aer. + "pme": Asserted for pme interrupt when chip support the pme interrupt with + none MSI/MSI-X/INTx mode,but there is interrupt line for pme. +- dma-coherent: Indicates that the hardware IP block can ensure the coherency + of the data transferred from/to the IP block. This can avoid the software + cache flush/invalid actions, and improve the performance significantly. +- msi-parent : See the generic MSI binding described in + Documentation/devicetree/bindings/interrupt-controller/msi.txt. + +Example: + + pcie@3400000 { + compatible = "fsl,lx2160a-pcie"; + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ + 0x80 0x00000000 0x0 0x00001000>; /* configuration space */ + reg-names = "csr_axi_slave", "config_axi_slave"; + interrupts = , /* AER interrupt */ + , /* PME interrupt */ + ; /* controller interrupt */ + interrupt-names = "aer", "pme", "intr"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + apio-wins = <8>; + ppio-wins = <8>; + dma-coherent; + bus-range = <0x0 0xff>; + msi-parent = <&its>; + ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 084d225583e0..b59763e23392 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11405,6 +11405,14 @@ L: linux-arm-kernel@lists.infradead.org S: Maintained F: drivers/pci/controller/dwc/*layerscape* +PCI DRIVER FOR NXP LAYERSCAPE GEN4 CONTROLLER +M: Hou Zhiqiang +L: linux-pci@vger.kernel.org +L: linux-arm-kernel@lists.infradead.org +S: Maintained +F: Documentation/devicetree/bindings/pci/layerscape-pci.txt +F: drivers/pci/controller/mobibeil/pci-layerscape-gen4.c + PCI DRIVER FOR GENERIC OF HOSTS M: Will Deacon L: linux-pci@vger.kernel.org From patchwork Tue Nov 20 09:27:57 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Z.Q. Hou" X-Patchwork-Id: 1000350 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=nxp.com header.i=@nxp.com header.b="O6Wz3zKZ"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42zgPB2JQCz9s3l for ; Tue, 20 Nov 2018 20:28:30 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727744AbeKTT4M (ORCPT ); Tue, 20 Nov 2018 14:56:12 -0500 Received: from mail-eopbgr70054.outbound.protection.outlook.com ([40.107.7.54]:9376 "EHLO EUR04-HE1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727453AbeKTT4L (ORCPT ); Tue, 20 Nov 2018 14:56:11 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=EsWc3HHrsvCw3TAwiGTFo3m6TFcG6WSs2Q/TCpBa6hQ=; b=O6Wz3zKZW874i7b2OoGIyiiPnTX/l6Br6wt4MiObbqcq/ESmFTTTmosnnYEfBq4D/CSetptjNLlMrWhoSx7zFqLQ1Cjm7vCxjpwN+tWP1DlRD7BGJmWRo4t2cWdx1xzcOmzVPQ0U12asP+M5cS9gHbgHLimRbKaodKFCr+RS69k= Received: from AM6PR04MB5781.eurprd04.prod.outlook.com (20.179.2.80) by AM6PR04MB4775.eurprd04.prod.outlook.com (20.177.32.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1339.21; Tue, 20 Nov 2018 09:27:57 +0000 Received: from AM6PR04MB5781.eurprd04.prod.outlook.com ([fe80::29b5:b3ed:3854:cf1c]) by AM6PR04MB5781.eurprd04.prod.outlook.com ([fe80::29b5:b3ed:3854:cf1c%4]) with mapi id 15.20.1339.026; Tue, 20 Nov 2018 09:27:57 +0000 From: "Z.q. Hou" To: "linux-pci@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "bhelgaas@google.com" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "l.subrahmanya@mobiveil.co.in" , "shawnguo@kernel.org" , Leo Li , "lorenzo.pieralisi@arm.com" , "catalin.marinas@arm.com" , "will.deacon@arm.com" CC: Mingkai Hu , "M.h. Lian" , Xiaowei Bao , "Z.q. Hou" Subject: [PATCHv2 23/25] PCI: mobiveil: add PCIe Gen4 RC driver for NXP Layerscape SoCs Thread-Topic: [PATCHv2 23/25] PCI: mobiveil: add PCIe Gen4 RC driver for NXP Layerscape SoCs Thread-Index: AQHUgLNSP5Bm4CVLVUSREMlUOF4EKw== Date: Tue, 20 Nov 2018 09:27:57 +0000 Message-ID: <20181120092615.11680-24-Zhiqiang.Hou@nxp.com> References: <20181120092615.11680-1-Zhiqiang.Hou@nxp.com> In-Reply-To: <20181120092615.11680-1-Zhiqiang.Hou@nxp.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: HK2PR03CA0050.apcprd03.prod.outlook.com (2603:1096:202:17::20) To AM6PR04MB5781.eurprd04.prod.outlook.com (2603:10a6:20b:aa::16) authentication-results: spf=none (sender IP is ) smtp.mailfrom=zhiqiang.hou@nxp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [119.31.174.73] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; AM6PR04MB4775; 6:oLnUSrZeyDiIt0kSqpvfhdkF4T1mhgt/COeKl+5I+uCUZqXX4eZcQGG69OhZHReemH/7o+B0El0YjxL5EQhXeu4BXLSWAI7W+omDAZogf9Wfq+mwyD/Nb2LR0gr5pS+th89vOGcMcfPfLfUaBG+pzWA0R27ZdxhN5m4BOq/xYOreBX1UD1RHmhQg8T8MC03Yh7XMP+VCSQgPG8Fx6gmsdBfo+tKIKJBbT/nCP9f6tCSmYVjLCqGg1kTOLoC6h6lg3xxp4zGuP1l/U6wXr9m79DJVq/yEwFNIfT0/MRGSrc5dEAgShyUW9gd6MuIp0/us9/QoFQRgBnm8kXKlsufMzbKOoEo6mot4kbWEzbV+gZz8sgNduDnPh0G9/CK1c0BqusrjwphfhAfrEsMZJSt63EBkxdiBC2UtQiAXGHrNs8IK77TjNM3N8QFjJKjQAJuF037aFLhVuEtwgIrxF9i0xw==; 5:htHl+EBHmc/sCJcdFY7Q9CyAzvE/VGvF2vaPyXl3BLVHJ4KPth8C8fRv56P00gL7nyugIoMg6jVuGHioBXzL+0HQ/wQo1gk2Pp1sVzfTF06Os5p8iU/GFDfXXXyFARbBdcasbIWa2YAZfFEdbnZhhdRe9AADo2UBz73frf6fvDY=; 7:bvCuqQYJQ1mWOWGJ8LgKjWAXXAA//I3xEY26p+2fp9HQJbOxW7DsdQtl4kXsMCC9YWJQUmDzmjjA5MhnHfpafqCR7dhhBnLtvdrfvmkueBRU450Mi7lX9I2U9vUlv1VQxVFibHngvXh9ewnGI9E8Xw== x-ms-office365-filtering-correlation-id: 71340e26-cd9b-4209-1975-08d64eca751b x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390098)(7020095)(4652040)(8989299)(5600074)(711020)(4618075)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7153060)(7193020); SRVR:AM6PR04MB4775; x-ms-traffictypediagnostic: AM6PR04MB4775: x-microsoft-antispam-prvs: x-ms-exchange-senderadcheck: 1 x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(8211001083)(6040522)(2401047)(8121501046)(5005006)(93006095)(93001095)(3231442)(944501410)(52105112)(3002001)(10201501046)(6055026)(148016)(149066)(150057)(6041310)(20161123562045)(20161123564045)(20161123560045)(20161123558120)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(201708071742011)(7699051)(76991095); SRVR:AM6PR04MB4775; BCL:0; PCL:0; RULEID:; SRVR:AM6PR04MB4775; x-forefront-prvs: 08626BE3A5 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(6029001)(366004)(39860400002)(136003)(376002)(396003)(346002)(189003)(199004)(66066001)(1076002)(2900100001)(68736007)(8676002)(6486002)(5660300001)(8936002)(6116002)(3846002)(2501003)(97736004)(81166006)(26005)(186003)(81156014)(105586002)(7416002)(102836004)(2906002)(386003)(6506007)(7736002)(305945005)(106356001)(6512007)(76176011)(36756003)(4326008)(99286004)(52116002)(14444005)(25786009)(575784001)(110136005)(54906003)(2616005)(86362001)(53936002)(446003)(11346002)(256004)(2201001)(6436002)(486006)(71190400001)(71200400001)(478600001)(316002)(476003)(14454004)(921003)(1121003); DIR:OUT; SFP:1101; SCL:1; SRVR:AM6PR04MB4775; H:AM6PR04MB5781.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: nQjTqqLGwHw6f09lvx2CppTGmXJEmNZLNWiE09Bv2F8G+z68jN49kVX5lEMIWzwyS8zOcHabef0l8kn0AFklSzfyymymdY8morc7ck/rm+jC6waIvTHCECE9Ov16bl9gmMra2gj8jbIchgU1fENayxaNsIRim51aWXHaayg0snf98Kci+TRBQSlS3o4DxgWm6dok2tnTIzl4GF0c1epTxhR1Qh/mQqFVjvw1e3nTiUYvEz6hHNVKYP1xpaG72MBJxf0tcxYNgjtHfctOygUAnAhFQ1aUNISyBESqXPapNMZQdiwUwuQSLCMsBaJZNj9mLtrvmA1c3YltZ9z6Bir7wE1vVn/IkmpkLKPfoGNVj+c= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-ID: <56EDB6A0BB4E1E40BF3180250A6DE33B@eurprd04.prod.outlook.com> MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 71340e26-cd9b-4209-1975-08d64eca751b X-MS-Exchange-CrossTenant-originalarrivaltime: 20 Nov 2018 09:27:57.7074 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR04MB4775 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Hou Zhiqiang This PCIe controller is based on the Mobiveil GPEX IP, which is compatible with the PCI Express™ Base Specification, Revision 4.0. Signed-off-by: Hou Zhiqiang reviewed-by: Minghuan Lian --- V2: - Changed the name of functions and data structures in this driver. - Moved the reset operations to bottle half of the ISR. - Added timeout check in polling the status of the PAB. - Moved the interrupt init operations to ls_pcie_g4_interrupt_init(). drivers/pci/controller/mobiveil/Kconfig | 10 + drivers/pci/controller/mobiveil/Makefile | 1 + .../controller/mobiveil/pci-layerscape-gen4.c | 254 ++++++++++++++++++ .../pci/controller/mobiveil/pcie-mobiveil.h | 16 +- 4 files changed, 279 insertions(+), 2 deletions(-) create mode 100644 drivers/pci/controller/mobiveil/pci-layerscape-gen4.c diff --git a/drivers/pci/controller/mobiveil/Kconfig b/drivers/pci/controller/mobiveil/Kconfig index 64343c07bfed..3ddb7d6163a9 100644 --- a/drivers/pci/controller/mobiveil/Kconfig +++ b/drivers/pci/controller/mobiveil/Kconfig @@ -21,4 +21,14 @@ config PCIE_MOBIVEIL_PLAT Soft IP. It has up to 8 outbound and inbound windows for address translation and it is a PCIe Gen4 IP. +config PCI_LAYERSCAPE_GEN4 + bool "Freescale Layerscpe PCIe Gen4 controller" + depends on PCI + depends on OF && (ARM64 || ARCH_LAYERSCAPE) + depends on PCI_MSI_IRQ_DOMAIN + select PCIE_MOBIVEIL_HOST + help + Say Y here if you want PCIe Gen4 controller support on + Layerscape SoCs. The PCIe controller can work in RC or + EP mode according to RCW[HOST_AGT_PEX] setting. endmenu diff --git a/drivers/pci/controller/mobiveil/Makefile b/drivers/pci/controller/mobiveil/Makefile index 9fb6d1c6504d..ff66774ccac4 100644 --- a/drivers/pci/controller/mobiveil/Makefile +++ b/drivers/pci/controller/mobiveil/Makefile @@ -2,3 +2,4 @@ obj-$(CONFIG_PCIE_MOBIVEIL) += pcie-mobiveil.o obj-$(CONFIG_PCIE_MOBIVEIL_HOST) += pcie-mobiveil-host.o obj-$(CONFIG_PCIE_MOBIVEIL_PLAT) += pcie-mobiveil-plat.o +obj-$(CONFIG_PCI_LAYERSCAPE_GEN4) += pci-layerscape-gen4.o diff --git a/drivers/pci/controller/mobiveil/pci-layerscape-gen4.c b/drivers/pci/controller/mobiveil/pci-layerscape-gen4.c new file mode 100644 index 000000000000..174cbcac4059 --- /dev/null +++ b/drivers/pci/controller/mobiveil/pci-layerscape-gen4.c @@ -0,0 +1,254 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * PCIe host controller driver for NXP Layerscape SoCs + * + * Copyright 2018 NXP + * + * Author: Zhiqiang Hou + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pcie-mobiveil.h" + +/* LUT and PF control registers */ +#define PCIE_LUT_OFF (0x80000) +#define PCIE_PF_OFF (0xc0000) +#define PCIE_PF_INT_STAT (0x18) +#define PF_INT_STAT_PABRST (31) + +#define PCIE_PF_DBG (0x7fc) +#define PF_DBG_LTSSM_MASK (0x3f) +#define PF_DBG_WE (31) +#define PF_DBG_PABR (27) + +#define LS_PCIE_G4_LTSSM_L0 0x2d /* L0 state */ + +#define to_ls_pcie_g4(x) platform_get_drvdata((x)->pdev) + +struct ls_pcie_g4 { + struct mobiveil_pcie *pci; + struct delayed_work dwork; + int irq; +}; + +static inline u32 ls_pcie_g4_lut_readl(struct ls_pcie_g4 *pcie, u32 off) +{ + return ioread32(pcie->pci->csr_axi_slave_base + PCIE_LUT_OFF + off); +} + +static inline void ls_pcie_g4_lut_writel(struct ls_pcie_g4 *pcie, + u32 off, u32 val) +{ + iowrite32(val, pcie->pci->csr_axi_slave_base + PCIE_LUT_OFF + off); +} + +static inline u32 ls_pcie_g4_pf_readl(struct ls_pcie_g4 *pcie, u32 off) +{ + return ioread32(pcie->pci->csr_axi_slave_base + PCIE_PF_OFF + off); +} + +static inline void ls_pcie_g4_pf_writel(struct ls_pcie_g4 *pcie, + u32 off, u32 val) +{ + iowrite32(val, pcie->pci->csr_axi_slave_base + PCIE_PF_OFF + off); +} + +static bool ls_pcie_g4_is_bridge(struct ls_pcie_g4 *pcie) +{ + struct mobiveil_pcie *mv_pci = pcie->pci; + u32 header_type; + + header_type = csr_readb(mv_pci, PCI_HEADER_TYPE); + header_type &= 0x7f; + + return header_type == PCI_HEADER_TYPE_BRIDGE; +} + +static int ls_pcie_g4_link_up(struct mobiveil_pcie *pci) +{ + struct ls_pcie_g4 *pcie = to_ls_pcie_g4(pci); + u32 state; + + state = ls_pcie_g4_pf_readl(pcie, PCIE_PF_DBG); + state = state & PF_DBG_LTSSM_MASK; + + if (state == LS_PCIE_G4_LTSSM_L0) + return 1; + + return 0; +} + +static void ls_pcie_g4_reinit_hw(struct ls_pcie_g4 *pcie) +{ + struct mobiveil_pcie *mv_pci = pcie->pci; + u32 val, act_stat; + int to = 100; + + /* Poll for pab_csb_reset to set and PAB activity to clear */ + do { + usleep_range(10, 15); + val = ls_pcie_g4_pf_readl(pcie, PCIE_PF_INT_STAT); + act_stat = csr_readl(mv_pci, PAB_ACTIVITY_STAT); + } while (((val & 1 << PF_INT_STAT_PABRST) == 0 || act_stat) && to--); + if (to < 0) { + dev_err(&mv_pci->pdev->dev, "poll PABRST&PABACT timeout\n"); + return; + } + + /* clear PEX_RESET bit in PEX_PF0_DBG register */ + val = ls_pcie_g4_pf_readl(pcie, PCIE_PF_DBG); + val |= 1 << PF_DBG_WE; + ls_pcie_g4_pf_writel(pcie, PCIE_PF_DBG, val); + + val = ls_pcie_g4_pf_readl(pcie, PCIE_PF_DBG); + val |= 1 << PF_DBG_PABR; + ls_pcie_g4_pf_writel(pcie, PCIE_PF_DBG, val); + + val = ls_pcie_g4_pf_readl(pcie, PCIE_PF_DBG); + val &= ~(1 << PF_DBG_WE); + ls_pcie_g4_pf_writel(pcie, PCIE_PF_DBG, val); + + mobiveil_host_init(mv_pci, true); + + to = 100; + while (!ls_pcie_g4_link_up(mv_pci) && to--) + usleep_range(200, 250); + if (to < 0) + dev_err(&mv_pci->pdev->dev, "PCIe link trainning timeout\n"); +} + +static irqreturn_t ls_pcie_g4_handler(int irq, void *dev_id) +{ + struct ls_pcie_g4 *pcie = (struct ls_pcie_g4 *)dev_id; + struct mobiveil_pcie *mv_pci = pcie->pci; + u32 val; + + val = csr_readl(mv_pci, PAB_INTP_AMBA_MISC_STAT); + if (!val) + return IRQ_NONE; + + if (val & PAB_INTP_RESET) + schedule_delayed_work(&pcie->dwork, msecs_to_jiffies(1)); + + csr_writel(mv_pci, val, PAB_INTP_AMBA_MISC_STAT); + + return IRQ_HANDLED; +} + +static int ls_pcie_g4_interrupt_init(struct mobiveil_pcie *mv_pci) +{ + struct ls_pcie_g4 *pcie = to_ls_pcie_g4(mv_pci); + u32 val; + int ret; + + pcie->irq = platform_get_irq_byname(mv_pci->pdev, "intr"); + if (pcie->irq < 0) { + dev_err(&mv_pci->pdev->dev, "Can't get 'intr' irq.\n"); + return pcie->irq; + } + ret = devm_request_irq(&mv_pci->pdev->dev, pcie->irq, + ls_pcie_g4_handler, IRQF_SHARED, + mv_pci->pdev->name, pcie); + if (ret) { + dev_err(&mv_pci->pdev->dev, "Can't register PCIe IRQ.\n"); + return ret; + } + + /* Enable interrupts */ + val = PAB_INTP_INTX_MASK | PAB_INTP_MSI | PAB_INTP_RESET | + PAB_INTP_PCIE_UE | PAB_INTP_IE_PMREDI | PAB_INTP_IE_EC; + csr_writel(mv_pci, val, PAB_INTP_AMBA_MISC_ENB); + + return 0; +} + +static void ls_pcie_g4_reset(struct work_struct *work) +{ + struct delayed_work *dwork = container_of(work, struct delayed_work, + work); + struct ls_pcie_g4 *pcie = container_of(dwork, struct ls_pcie_g4, dwork); + struct mobiveil_pcie *mv_pci = pcie->pci; + u16 ctrl; + + ctrl = csr_readw(mv_pci, PCI_BRIDGE_CONTROL); + ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET; + csr_writew(mv_pci, ctrl, PCI_BRIDGE_CONTROL); + ls_pcie_g4_reinit_hw(pcie); +} + +static struct mobiveil_rp_ops ls_pcie_g4_rp_ops = { + .interrupt_init = ls_pcie_g4_interrupt_init, +}; + +static const struct mobiveil_pab_ops ls_pcie_g4_pab_ops = { + .link_up = ls_pcie_g4_link_up, +}; + +static int __init ls_pcie_g4_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct mobiveil_pcie *mv_pci; + struct ls_pcie_g4 *pcie; + struct device_node *np = dev->of_node; + int ret; + + if (!of_parse_phandle(np, "msi-parent", 0)) { + dev_err(dev, "failed to find msi-parent\n"); + return -EINVAL; + } + + pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); + if (!pcie) + return -ENOMEM; + + mv_pci = devm_kzalloc(dev, sizeof(*mv_pci), GFP_KERNEL); + if (!mv_pci) + return -ENOMEM; + + mv_pci->pdev = pdev; + mv_pci->ops = &ls_pcie_g4_pab_ops; + mv_pci->rp.ops = &ls_pcie_g4_rp_ops; + pcie->pci = mv_pci; + + platform_set_drvdata(pdev, pcie); + + INIT_DELAYED_WORK(&pcie->dwork, ls_pcie_g4_reset); + + ret = mobiveil_pcie_host_probe(mv_pci); + if (ret) { + dev_err(dev, "fail to probe!\n"); + return ret; + } + + if (!ls_pcie_g4_is_bridge(pcie)) + return -ENODEV; + + return 0; +} + +static const struct of_device_id ls_pcie_g4_of_match[] = { + { .compatible = "fsl,lx2160a-pcie", }, + { }, +}; + +static struct platform_driver ls_pcie_g4_driver = { + .driver = { + .name = "layerscape-pcie-gen4", + .of_match_table = ls_pcie_g4_of_match, + .suppress_bind_attrs = true, + }, +}; + +builtin_platform_driver_probe(ls_pcie_g4_driver, ls_pcie_g4_probe); diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.h b/drivers/pci/controller/mobiveil/pcie-mobiveil.h index 0f5303962e88..0ccd6cee5f8f 100644 --- a/drivers/pci/controller/mobiveil/pcie-mobiveil.h +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.h @@ -41,6 +41,8 @@ #define PAGE_LO_MASK 0x3ff #define PAGE_SEL_OFFSET_SHIFT 10 +#define PAB_ACTIVITY_STAT 0x81c + #define PAB_AXI_PIO_CTRL 0x0840 #define APIO_EN_MASK 0xf @@ -49,8 +51,18 @@ #define PAB_INTP_AMBA_MISC_ENB 0x0b0c #define PAB_INTP_AMBA_MISC_STAT 0x0b1c -#define PAB_INTP_INTX_MASK 0x01e0 -#define PAB_INTP_MSI_MASK 0x8 +#define PAB_INTP_RESET (0x1 << 1) +#define PAB_INTP_MSI (0x1 << 3) +#define PAB_INTP_INTA (0x1 << 5) +#define PAB_INTP_INTB (0x1 << 6) +#define PAB_INTP_INTC (0x1 << 7) +#define PAB_INTP_INTD (0x1 << 8) +#define PAB_INTP_PCIE_UE (0x1 << 9) +#define PAB_INTP_IE_PMREDI (0x1 << 29) +#define PAB_INTP_IE_EC (0x1 << 30) +#define PAB_INTP_MSI_MASK PAB_INTP_MSI +#define PAB_INTP_INTX_MASK (PAB_INTP_INTA | PAB_INTP_INTB |\ + PAB_INTP_INTC | PAB_INTP_INTD) #define PAB_AXI_AMAP_CTRL(win) PAB_REG_ADDR(0x0ba0, win) #define WIN_ENABLE_SHIFT 0 From patchwork Tue Nov 20 09:28:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Z.Q. Hou" X-Patchwork-Id: 1000348 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=nxp.com header.i=@nxp.com header.b="DoYNentk"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42zgNt4HpRz9s8F for ; Tue, 20 Nov 2018 20:28:14 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728188AbeKTT4S (ORCPT ); Tue, 20 Nov 2018 14:56:18 -0500 Received: from mail-eopbgr70089.outbound.protection.outlook.com ([40.107.7.89]:12064 "EHLO EUR04-HE1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727728AbeKTT4S (ORCPT ); Tue, 20 Nov 2018 14:56:18 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=zrsGMBADIsqeEU4duNCkqzr5ye0dCRBHJDsrbmznpI4=; b=DoYNentknLCea+B03Mc2Y2lnydHXHpYKbaiuULDXggD42zaR7B2KDqbXtAgEu1pOx3/qOKa37YT2dJRMJl7Bpd/valK4kTCyx3KXwsJr4aZ7U+g5lzNrtGaKkNiXON4/SkA/dFyP+hEozOGTxG9fpW8L69HJdDYHvKpr8gTwW5E= Received: from AM6PR04MB5781.eurprd04.prod.outlook.com (20.179.2.80) by AM6PR04MB4775.eurprd04.prod.outlook.com (20.177.32.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1339.21; Tue, 20 Nov 2018 09:28:03 +0000 Received: from AM6PR04MB5781.eurprd04.prod.outlook.com ([fe80::29b5:b3ed:3854:cf1c]) by AM6PR04MB5781.eurprd04.prod.outlook.com ([fe80::29b5:b3ed:3854:cf1c%4]) with mapi id 15.20.1339.026; Tue, 20 Nov 2018 09:28:03 +0000 From: "Z.q. Hou" To: "linux-pci@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "bhelgaas@google.com" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "l.subrahmanya@mobiveil.co.in" , "shawnguo@kernel.org" , Leo Li , "lorenzo.pieralisi@arm.com" , "catalin.marinas@arm.com" , "will.deacon@arm.com" CC: Mingkai Hu , "M.h. Lian" , Xiaowei Bao , "Z.q. Hou" Subject: [PATCHv2 24/25] arm64: dts: freescale: lx2160a: add pcie DT nodes Thread-Topic: [PATCHv2 24/25] arm64: dts: freescale: lx2160a: add pcie DT nodes Thread-Index: AQHUgLNW1TfB2GtMH0GXyxrHVyVRKg== Date: Tue, 20 Nov 2018 09:28:03 +0000 Message-ID: <20181120092615.11680-25-Zhiqiang.Hou@nxp.com> References: <20181120092615.11680-1-Zhiqiang.Hou@nxp.com> In-Reply-To: <20181120092615.11680-1-Zhiqiang.Hou@nxp.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: HK2PR03CA0050.apcprd03.prod.outlook.com (2603:1096:202:17::20) To AM6PR04MB5781.eurprd04.prod.outlook.com (2603:10a6:20b:aa::16) authentication-results: spf=none (sender IP is ) smtp.mailfrom=zhiqiang.hou@nxp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [119.31.174.73] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; AM6PR04MB4775; 6:B+61WwH01BhOQvBjM9t2eSkCCF2UeWAvhzFzm4yGICRT7tM+kNE6+J466XX+bnjZevmkNS761ldCWJ5Wed6ne544ICDyzDzf/GtiVYnB82qWuupjY4G97ZustIpyQ7z3+hETfTXOprzUuoFcaFmLZcFMR4jhaUh57OA7rO6AJxbBfR0sWFRbqyHPhISti7h7cJ1je/THEryZmf4t66zcVSiMHk6fjSiNEMcnsLt0/D2gdutPIzj8dDXrFgDie0g2pVhxbSj7SFcHwHf6QXO2zjDGTIlFnISTYLS5Wn6GfkugC4yqqimMjWTmXcTAw74VyDFZVCeloM1pkjW9XgcTyLb5tpfTWAX04xxuwFjHG5M4t+18XJHbPH615cXKEEVNQhYIWxm7d5Eu/IERXDxKtQwLd3kztlfqMguJdvZcmCWVpVpArHKo2Uk5InYxXZhTp2eSJXXfir82kBvFUa7Jlg==; 5:MvEgIVOfB/b8UQToi9wBiioCqZKgjQdwfLE0lqrABP7/dHV1Gp8TLhTz1T0IKRz6oNIxaHMaBx9mO1GN1rmJp5+JWmZDKut09qywVRPH9AaDDuGshkkkdlG5S6qWFd1HbCxVQmiSTPLAQu/yQgjSJOJgWOxKlrnWBWIyZOTADeA=; 7:y8vRGBRLVEHWmmYlFy1dFiTjH+AjP4TzOwjuT5FLR3+DWADtwjNo2AnYLe0pWbG9fyHkk9t93u3AW/IsxGnzSdLUVByP1DGFUe8CXOxBbb+Tmi7RynUK1WTng2THoSBRIFZDkHuP+PdYWGnksBtaQw== x-ms-office365-filtering-correlation-id: c1a2c36f-95c8-4f41-8eb7-08d64eca78ba x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390098)(7020095)(4652040)(8989299)(5600074)(711020)(4618075)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7153060)(7193020); SRVR:AM6PR04MB4775; x-ms-traffictypediagnostic: AM6PR04MB4775: x-microsoft-antispam-prvs: x-ms-exchange-senderadcheck: 1 x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(8211001083)(6040522)(2401047)(8121501046)(5005006)(93006095)(93001095)(3231442)(944501410)(52105112)(3002001)(10201501046)(6055026)(148016)(149066)(150057)(6041310)(20161123562045)(20161123564045)(20161123560045)(20161123558120)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(201708071742011)(7699051)(76991095); SRVR:AM6PR04MB4775; BCL:0; PCL:0; RULEID:; SRVR:AM6PR04MB4775; x-forefront-prvs: 08626BE3A5 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(366004)(39860400002)(136003)(376002)(396003)(346002)(189003)(199004)(66066001)(1076002)(2900100001)(68736007)(8676002)(6486002)(5660300001)(8936002)(6116002)(3846002)(2501003)(97736004)(81166006)(26005)(186003)(81156014)(105586002)(7416002)(102836004)(2906002)(386003)(6506007)(7736002)(305945005)(106356001)(6512007)(76176011)(36756003)(4326008)(99286004)(52116002)(14444005)(25786009)(110136005)(54906003)(2616005)(86362001)(53936002)(446003)(11346002)(256004)(2201001)(6436002)(486006)(71190400001)(71200400001)(478600001)(316002)(476003)(14454004)(921003)(1121003); DIR:OUT; SFP:1101; SCL:1; SRVR:AM6PR04MB4775; H:AM6PR04MB5781.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: Ba/f1I8T2tupY/jhvcak62sp4VKj7JpZZzW3wsrc5Kc9L3eH6syRwcod35uuqU1UHPNHZ8ITMI3Q9UycCMrWd0+77FcdShIwnhz1sqj3LyWkr7UcSI408Xaidpw/fXYbHkBoPM7feHRz+sCwKgGMwuimW90bt3T3+8mv+WcnAuQv0Meais7YMsHYfGEodmLo4JBy9ijnuEgrEUwj4glhOXt9Yw2tPc06Euh2IMI5HR4u4WMG2T6t/q1SEtxj85bVRTb7Jb/BdW0MMBi0SNoE8vJB4B3M+dzJJoRHe5weupamfHspd+w/8uESJGtY8+pjNg1u3cF5nhfn0A1Gep3gsKB+VLIADeRFySgBsqAUddU= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: c1a2c36f-95c8-4f41-8eb7-08d64eca78ba X-MS-Exchange-CrossTenant-originalarrivaltime: 20 Nov 2018 09:28:03.7856 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR04MB4775 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Hou Zhiqiang The LX2160A integrated 6 PCIe Gen4 controllers. Signed-off-by: Hou Zhiqiang reviewed-by: Minghuan Lian --- V2: - Change the default status of PCIe DT nodes to disabled. .../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 163 ++++++++++++++++++ 1 file changed, 163 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi index a79f5c1ea56d..3a098c462a25 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi @@ -762,5 +762,168 @@ ; dma-coherent; }; + + pcie@3400000 { + compatible = "fsl,lx2160a-pcie"; + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ + 0x80 0x00000000 0x0 0x00001000>; /* configuration space */ + reg-names = "csr_axi_slave", "config_axi_slave"; + interrupts = , /* AER interrupt */ + , /* PME interrupt */ + ; /* controller interrupt */ + interrupt-names = "aer", "pme", "intr"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + apio-wins = <8>; + ppio-wins = <8>; + bus-range = <0x0 0xff>; + ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + pcie@3500000 { + compatible = "fsl,lx2160a-pcie"; + reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ + 0x88 0x00000000 0x0 0x00001000>; /* configuration space */ + reg-names = "csr_axi_slave", "config_axi_slave"; + interrupts = , /* AER interrupt */ + , /* PME interrupt */ + ; /* controller interrupt */ + interrupt-names = "aer", "pme", "intr"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + apio-wins = <8>; + ppio-wins = <8>; + bus-range = <0x0 0xff>; + ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + pcie@3600000 { + compatible = "fsl,lx2160a-pcie"; + reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ + 0x90 0x00000000 0x0 0x00001000>; /* configuration space */ + reg-names = "csr_axi_slave", "config_axi_slave"; + interrupts = , /* AER interrupt */ + , /* PME interrupt */ + ; /* controller interrupt */ + interrupt-names = "aer", "pme", "intr"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + apio-wins = <8>; + ppio-wins = <8>; + bus-range = <0x0 0xff>; + ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + pcie@3700000 { + compatible = "fsl,lx2160a-pcie"; + reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */ + 0x98 0x00000000 0x0 0x00001000>; /* configuration space */ + reg-names = "csr_axi_slave", "config_axi_slave"; + interrupts = , /* AER interrupt */ + , /* PME interrupt */ + ; /* controller interrupt */ + interrupt-names = "aer", "pme", "intr"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + apio-wins = <8>; + ppio-wins = <8>; + bus-range = <0x0 0xff>; + ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + pcie@3800000 { + compatible = "fsl,lx2160a-pcie"; + reg = <0x00 0x03800000 0x0 0x00100000 /* controller registers */ + 0xa0 0x00000000 0x0 0x00001000>; /* configuration space */ + reg-names = "csr_axi_slave", "config_axi_slave"; + interrupts = , /* AER interrupt */ + , /* PME interrupt */ + ; /* controller interrupt */ + interrupt-names = "aer", "pme", "intr"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + apio-wins = <8>; + ppio-wins = <8>; + bus-range = <0x0 0xff>; + ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + pcie@3900000 { + compatible = "fsl,lx2160a-pcie"; + reg = <0x00 0x03900000 0x0 0x00100000 /* controller registers */ + 0xa8 0x00000000 0x0 0x00001000>; /* configuration space */ + reg-names = "csr_axi_slave", "config_axi_slave"; + interrupts = , /* AER interrupt */ + , /* PME interrupt */ + ; /* controller interrupt */ + interrupt-names = "aer", "pme", "intr"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + apio-wins = <8>; + ppio-wins = <8>; + bus-range = <0x0 0xff>; + ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + }; }; From patchwork Tue Nov 20 09:28:10 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Z.Q. Hou" X-Patchwork-Id: 1000349 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=nxp.com header.i=@nxp.com header.b="FN5UcFo6"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42zgP24hCqz9sB7 for ; Tue, 20 Nov 2018 20:28:22 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727728AbeKTT4W (ORCPT ); Tue, 20 Nov 2018 14:56:22 -0500 Received: from mail-eopbgr70049.outbound.protection.outlook.com ([40.107.7.49]:38103 "EHLO EUR04-HE1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727697AbeKTT4W (ORCPT ); Tue, 20 Nov 2018 14:56:22 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=1WLBUiGq73F57FgZnrI7y4TOTNp+zfSW77paRGsTmAs=; b=FN5UcFo6/DMxwzjNzsDufvNetzc25dVdHISt0+sa1H6A95gAHhMlhGulHBq3aMwKOa1OfdAxU7YNXzSEvGFhHdgBRUkL8/PjDpCqigNKsuNJttJTsE3Ck+YSbV+JkyK0j5wGxD8rj4eNeF8meWiD3c4dp1Jmb3zyomP4X6tq5jg= Received: from AM6PR04MB5781.eurprd04.prod.outlook.com (20.179.2.80) by AM6PR04MB4775.eurprd04.prod.outlook.com (20.177.32.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1339.21; Tue, 20 Nov 2018 09:28:10 +0000 Received: from AM6PR04MB5781.eurprd04.prod.outlook.com ([fe80::29b5:b3ed:3854:cf1c]) by AM6PR04MB5781.eurprd04.prod.outlook.com ([fe80::29b5:b3ed:3854:cf1c%4]) with mapi id 15.20.1339.026; Tue, 20 Nov 2018 09:28:10 +0000 From: "Z.q. Hou" To: "linux-pci@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "bhelgaas@google.com" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "l.subrahmanya@mobiveil.co.in" , "shawnguo@kernel.org" , Leo Li , "lorenzo.pieralisi@arm.com" , "catalin.marinas@arm.com" , "will.deacon@arm.com" CC: Mingkai Hu , "M.h. Lian" , Xiaowei Bao , "Z.q. Hou" Subject: [PATCHv2 25/25] arm64: defconfig: Enable CONFIG_PCI_LAYERSCAPE_GEN4 Thread-Topic: [PATCHv2 25/25] arm64: defconfig: Enable CONFIG_PCI_LAYERSCAPE_GEN4 Thread-Index: AQHUgLNaqALtyRr5VUK0V4PuzhuBiQ== Date: Tue, 20 Nov 2018 09:28:10 +0000 Message-ID: <20181120092615.11680-26-Zhiqiang.Hou@nxp.com> References: <20181120092615.11680-1-Zhiqiang.Hou@nxp.com> In-Reply-To: <20181120092615.11680-1-Zhiqiang.Hou@nxp.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: HK2PR03CA0050.apcprd03.prod.outlook.com (2603:1096:202:17::20) To AM6PR04MB5781.eurprd04.prod.outlook.com (2603:10a6:20b:aa::16) authentication-results: spf=none (sender IP is ) smtp.mailfrom=zhiqiang.hou@nxp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [119.31.174.73] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; AM6PR04MB4775; 6:NVa2/OVR8uC0J2Zm4kTgE9UxstVNZZj+ReIGg9qv02o6mk17gL9k83urfIp14FYz1vrZjJ1jZaJJJPHOI47WmCQa3V82pOq+I9L9TVp2Xpumobo8XvX/4JtCmvjbF0LKhARb2s/k8vPe+gYvEzUhYS+53mfaCe/FhSwS9hqnLBbKwknJ3zutC5N0M0X4EVGxXl105GXt3hLPgtu2tOoSYOtjlMO71Z7G6elBgKi24NPsK+nlSdZyDXb5HysMLLD98ImFUtQij2H0wmfKAkZVHjbojgBwLsy4A+bjkRYn8uycVSdTDRDJIHjKkEycEBwg0grLWdLBjfCZYa4ATKB/qNl9QHBHBzGvziR4INYVKqVRmMBwEHS9PZduwrR0RxVcvxXbpE2drd31hnoh+B82nSy2WxLnQQ/PDd/DEi6KoOf7fGNJAV79BNha0QuW2Opomc3qFyoxd21jkaLsWltu+g==; 5:nwpspzlM7HXeIM32TfezWukr/8st/XniOt9EOa9qTQcfWXbVVHMDDVlxu2ji0Rfzsy38jUWJxazkaAxB4PlHe48RQzE7pMjh3Jg8HUPzdPUAvrEOhDbvRfE3bLLdj0vvAo/wouKGvHKzokw2+FrvBLK64hD+7lZrQi+zvlDDxlU=; 7:Z7P1s8CKr/zviQ55vUVaYEi81mkwBrKup0OcuZw+J1Y7PfEzGM8j1VUecQ0zeDwsWTCUeLPIpMCpDLhaJgoYEPQsKFCGfBiHqSaZa4obixswG1/wylHe/BDYseObsXa6puz5nU3vnf0jcvbCND7Nsw== x-ms-office365-filtering-correlation-id: 7409f87b-57cf-4709-3f48-08d64eca7c55 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390098)(7020095)(4652040)(8989299)(5600074)(711020)(4618075)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7153060)(7193020); SRVR:AM6PR04MB4775; x-ms-traffictypediagnostic: AM6PR04MB4775: x-microsoft-antispam-prvs: x-ms-exchange-senderadcheck: 1 x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(8211001083)(6040522)(2401047)(8121501046)(5005006)(93006095)(93001095)(3231442)(944501410)(52105112)(3002001)(10201501046)(6055026)(148016)(149066)(150057)(6041310)(20161123562045)(20161123564045)(20161123560045)(20161123558120)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(201708071742011)(7699051)(76991095); SRVR:AM6PR04MB4775; BCL:0; PCL:0; RULEID:; SRVR:AM6PR04MB4775; x-forefront-prvs: 08626BE3A5 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(366004)(39860400002)(136003)(376002)(396003)(346002)(189003)(199004)(66066001)(1076002)(2900100001)(68736007)(8676002)(6486002)(5660300001)(8936002)(6116002)(3846002)(2501003)(97736004)(81166006)(26005)(186003)(81156014)(105586002)(7416002)(102836004)(2906002)(386003)(6506007)(7736002)(305945005)(106356001)(6512007)(76176011)(36756003)(4326008)(99286004)(52116002)(25786009)(110136005)(54906003)(2616005)(86362001)(53936002)(446003)(11346002)(256004)(2201001)(6436002)(486006)(71190400001)(71200400001)(478600001)(316002)(476003)(14454004)(921003)(1121003); DIR:OUT; SFP:1101; SCL:1; SRVR:AM6PR04MB4775; H:AM6PR04MB5781.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: f9jnKRxm1yaxXKW1WtTbOrAzAUcI46Jnp6dP7Kp8Aq9BC+Uyz07yGb07V4xctnMRUnUgKQn5zNSkaC+eUBXdI0V1T5w6xAojBlULotnmMZP9m5KS69T+88aYlqN170hQpHxeQvGEPfKgwe6MeSQ1iY7lYk6mTi1mVgHN1Oinoq7otAsoGm2bc7XG2W/qbt3dgJqC9fp7+w+zU6TT/dhHDXPluj+lvlRS/2naXOlE4a4fAGCZWBGJ/d28EtlRElrSn+z6AisF6XIQJQe4/0DAfyCurZaQ93w/hLobqqhkUoG55cSx8+7qy+U3AP7xLIOeHdvJBVFkSIfuv3rckKis7iQ6r4ZC5OTxe1/4AAvJ2GM= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 7409f87b-57cf-4709-3f48-08d64eca7c55 X-MS-Exchange-CrossTenant-originalarrivaltime: 20 Nov 2018 09:28:10.0513 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR04MB4775 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Hou Zhiqiang Enable the PCIe Gen4 controller driver for Layerscape SoCs. Signed-off-by: Hou Zhiqiang reviewed-by: Minghuan Lian --- V2: - New patch arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index ad92daeac585..6b4385f26e85 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -83,6 +83,7 @@ CONFIG_PCI_HOST_THUNDER_PEM=y CONFIG_PCI_HOST_THUNDER_ECAM=y CONFIG_PCIE_ROCKCHIP_HOST=m CONFIG_PCI_LAYERSCAPE=y +CONFIG_PCI_LAYERSCAPE_GEN4=y CONFIG_PCI_HISI=y CONFIG_PCIE_QCOM=y CONFIG_PCIE_ARMADA_8K=y