From patchwork Mon Nov 12 15:18:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 996486 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="iBXgZ8Cz"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42tvYK1htWz9s3C for ; Tue, 13 Nov 2018 02:19:01 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729452AbeKMBMk (ORCPT ); Mon, 12 Nov 2018 20:12:40 -0500 Received: from mail-ed1-f67.google.com ([209.85.208.67]:40503 "EHLO mail-ed1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726443AbeKMBMk (ORCPT ); Mon, 12 Nov 2018 20:12:40 -0500 Received: by mail-ed1-f67.google.com with SMTP id d3so7089933edx.7; Mon, 12 Nov 2018 07:18:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UzI7QItBboJycH/HpslvTFG94WVjeSBxpsz6zXZa7wE=; b=iBXgZ8CzGcK6Z4IAwmgQZF+n+el0Kchck8L0NZMQ8lQs0OVmOIR+Qx4xx+SJiNIRIP WMKHcWYojcDEqUkc99JYn+AIhwTNaNjwH9LBPIjjIb5UNmm+2li76cJOG3Mph7CDLAd7 71h5Zo1kOQ2dI/3TgvoeXIHIQBra5bmOB2GFbF1XzDCte9tLeWgBmf8GDvOHJcHNzza3 afGOYfmnx3qGODEnwzbsP8bpBjOOUIJeYhUptduoIpwMXor6n1C1mP50xdKirwUeZh68 +nDqXmKEj8Uoj05IFyitPe/WXPfd9kdsPdAvmdCAV/3JOMuYHzYVwcp0Tt6FCclIaf54 0SXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UzI7QItBboJycH/HpslvTFG94WVjeSBxpsz6zXZa7wE=; b=MNE4vE3hAQRMXLOvg4zvCm8bEVqVbA2Jf5za0bk8AfIXEjFimmdFOx4qpdL9kpsb42 XWZGfPVVuB2V+ABVN5Lf7SRF3TquiENUoiat16aHAw2OPE0tuYWvdMF6eaoKPAt3QzZv bWzRZDRRcR1vcXMRlPaDO1FJScYsFHvEkMjedQBVGj1TbbcSPS7XMr+cEjyIAjmQtHB8 2FpJbzj8bqfuXWwulI7TTa1Ya4NYB20E+74xa2FA7jVjWyqH29YGbP9EG+pfQUSlIvhg /SPizzM2LUVl+KmeG16OQtIaswWDlze343bUrwAcHP9ewnGVG9zGIRwViOZ3E6WOegwU kaJg== X-Gm-Message-State: AGRZ1gJx08Znw9w7uzdMjLocMdbEa6qKOCbzOM6JJBUEDVTKMY7BxfSg Td2wD/ZWouI8lyT9u3u/RQI= X-Google-Smtp-Source: AJdET5dWj6hZvnuwkvzovvkxCw3BpZVHWPCUBW8bwGFsS5NoRr4JzGHmCMpW1mhOLLnhc98kleGtrg== X-Received: by 2002:a50:a985:: with SMTP id n5-v6mr13033559edc.120.1542035937258; Mon, 12 Nov 2018 07:18:57 -0800 (PST) Received: from localhost (pD9E511F8.dip0.t-ipconnect.de. [217.229.17.248]) by smtp.gmail.com with ESMTPSA id s9-v6sm2396809ejf.27.2018.11.12.07.18.56 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 12 Nov 2018 07:18:56 -0800 (PST) From: Thierry Reding To: Thierry Reding , Jassi Brar , Greg Kroah-Hartman Cc: Jiri Slaby , Mikko Perttunen , Jon Hunter , Timo Alho , Pekka Pessi , Mika Liljeberg , linux-tegra@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 01/10] mailbox: Support blocking transfers in atomic context Date: Mon, 12 Nov 2018 16:18:44 +0100 Message-Id: <20181112151853.29289-2-thierry.reding@gmail.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181112151853.29289-1-thierry.reding@gmail.com> References: <20181112151853.29289-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The mailbox framework supports blocking transfers via completions for clients that can sleep. In order to support blocking transfers in cases where the transmission is not permitted to sleep, add a new ->flush() callback that controller drivers can implement to busy loop until the transmission has been completed. This will automatically be called when available and interrupts are disabled for clients that request blocking transfers. Signed-off-by: Thierry Reding --- drivers/mailbox/mailbox.c | 8 ++++++++ include/linux/mailbox_controller.h | 4 ++++ 2 files changed, 12 insertions(+) diff --git a/drivers/mailbox/mailbox.c b/drivers/mailbox/mailbox.c index 674b35f402f5..0eaf21259874 100644 --- a/drivers/mailbox/mailbox.c +++ b/drivers/mailbox/mailbox.c @@ -267,6 +267,14 @@ int mbox_send_message(struct mbox_chan *chan, void *mssg) unsigned long wait; int ret; + if (irqs_disabled() && chan->mbox->ops->flush) { + ret = chan->mbox->ops->flush(chan, chan->cl->tx_tout); + if (ret < 0) + tx_tick(chan, ret); + + return ret; + } + if (!chan->cl->tx_tout) /* wait forever */ wait = msecs_to_jiffies(3600000); else diff --git a/include/linux/mailbox_controller.h b/include/linux/mailbox_controller.h index 74deadb42d76..2a07d93f781a 100644 --- a/include/linux/mailbox_controller.h +++ b/include/linux/mailbox_controller.h @@ -24,6 +24,9 @@ struct mbox_chan; * transmission of data is reported by the controller via * mbox_chan_txdone (if it has some TX ACK irq). It must not * sleep. + * @flush: Called when a client requests transmissions to be blocking but + * the context doesn't allow sleeping. Typically the controller + * will implement a busy loop waiting for the data to flush out. * @startup: Called when a client requests the chan. The controller * could ask clients for additional parameters of communication * to be provided via client's chan_data. This call may @@ -46,6 +49,7 @@ struct mbox_chan; */ struct mbox_chan_ops { int (*send_data)(struct mbox_chan *chan, void *data); + int (*flush)(struct mbox_chan *chan, unsigned long timeout); int (*startup)(struct mbox_chan *chan); void (*shutdown)(struct mbox_chan *chan); bool (*last_tx_done)(struct mbox_chan *chan); From patchwork Mon Nov 12 15:18:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 996487 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Bp176z7j"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42tvYM2Sx5z9s1x for ; Tue, 13 Nov 2018 02:19:03 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729508AbeKMBMl (ORCPT ); Mon, 12 Nov 2018 20:12:41 -0500 Received: from mail-ed1-f65.google.com ([209.85.208.65]:42424 "EHLO mail-ed1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726385AbeKMBMl (ORCPT ); Mon, 12 Nov 2018 20:12:41 -0500 Received: by mail-ed1-f65.google.com with SMTP id j6so2686930edp.9; Mon, 12 Nov 2018 07:18:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=iEMxDt9SwCq0XVWjm/H323YWWFocKdlsBUZ7Qc5sH0M=; b=Bp176z7jz9EVUz72KS5zAwrBephPha3k/WNOWY8ZkbkfXY5QMsPATSutTFDQhidD+S MhLzqNJKgSKxYjWWhwv99hIRJ2i5EpUP2PK0tjisZNu8LdllS/GYLS3bW438RFrNp/5l 1TZiTOJrJ7ODKMse0eL7exSl3Maqsm5lNl4wvqE9A6SopmoNIwrnO7EQcMXj8932IbhN v4qBgNyvqMQRxf7+9a8Uucqp0dqnHEMZMk6DpUCDTjAK+GL15Vlriy5z8WIEy/YwPXSZ f7FGEWqErYx0JsHqhCOVHR0Bgu2LGjahczGM9Jm6wqRB70fx4rnTg8LXjsJzo76YdDxN vFAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iEMxDt9SwCq0XVWjm/H323YWWFocKdlsBUZ7Qc5sH0M=; b=o9JfQ3ZlJE/xW2p2fz7bwyWi1V7GgWYd5ZeMk7VHAd+cjt+IKH0Kj4D0xbtIeQ2Ua+ 0f2Wb4LYwWp28ouBU+cBpipeBIAOVt8lTw50+G5j5RI7+wjCY5r8xUSBrFGIua9uw7h4 IG73UcBOZBor2E0iKnIoV0R4HeDHJXAP3Zcu2qK58Tz0MqZqPtdvzKIkDVjd2ufEY1Cq YqryOqkaRrCXxcllp3KXwMJelJd17f+mt2b/clJRdhq2fG5cS/Kq++y59GxtfiD38mq1 CZyO+Qx79MhY/slTmElOAGW5AuLd7HX7kpYG0keGSr1lqoyeAQbqn6kCHeqqnmxadoDk yY1w== X-Gm-Message-State: AGRZ1gJf1ttRMJMuzSZuWKfQk5OkkScmNEGwsF9SX5l/YaV8iribVN3c 5X6KjBYIVqpDckPZHcvDvgg= X-Google-Smtp-Source: AJdET5cT/1d3Pq4+yYwHpkfnAOA1p0bxHPsCdNBNCDVvE51GIATwhywBX6Bys37WqQWfC/0iYlrjIA== X-Received: by 2002:a17:906:f04:: with SMTP id z4-v6mr9844197eji.106.1542035938889; Mon, 12 Nov 2018 07:18:58 -0800 (PST) Received: from localhost (pD9E511F8.dip0.t-ipconnect.de. [217.229.17.248]) by smtp.gmail.com with ESMTPSA id h4-v6sm2318625ejx.44.2018.11.12.07.18.58 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 12 Nov 2018 07:18:58 -0800 (PST) From: Thierry Reding To: Thierry Reding , Jassi Brar , Greg Kroah-Hartman Cc: Jiri Slaby , Mikko Perttunen , Jon Hunter , Timo Alho , Pekka Pessi , Mika Liljeberg , linux-tegra@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 02/10] mailbox: Allow multiple controllers per device Date: Mon, 12 Nov 2018 16:18:45 +0100 Message-Id: <20181112151853.29289-3-thierry.reding@gmail.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181112151853.29289-1-thierry.reding@gmail.com> References: <20181112151853.29289-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Mikko Perttunen Look through the whole controller list when mapping device tree phandles to controllers instead of stopping at the first one. Each controller is intended to only contain one kind of mailbox, but some devices (like Tegra HSP) implement multiple kinds and use the same device tree node for all of them. As such, we need to allow multiple mbox_controllers per device tree node. Signed-off-by: Mikko Perttunen Signed-off-by: Thierry Reding --- drivers/mailbox/mailbox.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/mailbox/mailbox.c b/drivers/mailbox/mailbox.c index 0eaf21259874..f34820bcf33c 100644 --- a/drivers/mailbox/mailbox.c +++ b/drivers/mailbox/mailbox.c @@ -335,7 +335,8 @@ struct mbox_chan *mbox_request_channel(struct mbox_client *cl, int index) list_for_each_entry(mbox, &mbox_cons, node) if (mbox->dev->of_node == spec.np) { chan = mbox->of_xlate(mbox, &spec); - break; + if (!IS_ERR(chan)) + break; } of_node_put(spec.np); From patchwork Mon Nov 12 15:18:46 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 996489 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="tw+cI6Dq"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42tvYP47hWz9s1x for ; Tue, 13 Nov 2018 02:19:05 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729823AbeKMBMo (ORCPT ); Mon, 12 Nov 2018 20:12:44 -0500 Received: from mail-ed1-f49.google.com ([209.85.208.49]:33740 "EHLO mail-ed1-f49.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726385AbeKMBMo (ORCPT ); Mon, 12 Nov 2018 20:12:44 -0500 Received: by mail-ed1-f49.google.com with SMTP id r27so4719769eda.0; Mon, 12 Nov 2018 07:19:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/RPli5BOw9+z5QGH2wxe38AOela08ZMXHFWuTc7lj+k=; b=tw+cI6DqJ/wf7uDG57I+33+QaZsFKo/ffCNQYPPqOZnyQVTJKa+7ddYOFpbhnXdCk0 nsiahdChKmp8815xuqCpZmU3dFYeH994iHasU+/DgTJIMr4L7p7SrR60ex7rDFaNrIQi oNblULco4ig/CA/TOPMvy4N5quax2arT9mmBI/wwk9/HG5X7rhRLnkDsfjjRSczX1Nda CSrNbmL+IA6FT53RkEN42g5QeLAV/p06s9BVvijIjPRsrXXwVKEb+sJQxwCjdoEuB/wO H3bnPAMiDk1bXN/xc71LRRu0/p2WZCAKkFVT9IMT5JoeTOeiuaC6c0q4ID47TdD1UniP 7UWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/RPli5BOw9+z5QGH2wxe38AOela08ZMXHFWuTc7lj+k=; b=T8hW+ss5YYwaVVwdEVOq3dBUk4Z2Up8IsCFV6dHZ1URYG/e83JEDpPzBrl3nxqaUj2 8Bhq7ZVG7MMHoQIJVw1sxleAnX4xW4g596QXacEx5QNrmUsyCKCaiMgRV2Zslf5gwW2P 2AM6nXWUoAwKlefeILfidb96H5UuY3tWmDIhi85Ptz50P6mBD+TwO1rY4QdTfylapSP5 fgk3Vt931FpwatAlwO09FcPln+W0lBbVIA3QmWFlPmMzcB0rcqPTHxx9V7FFrvkXIFkK y9wgSIFpi9vZARcl/zY/r+/beyfFQo4zOjjNfZuWdJzOYIYhPJrztZeWGgodfVWBSAgl ClEg== X-Gm-Message-State: AGRZ1gJxVFxKCt7QXOkH8c4AK33ZwdpXLx8dTeau/Azt2ZWd9CmuA6ql QOs8h5BzUai9D94d6omSVSNkl5VV X-Google-Smtp-Source: AJdET5fNuDLUr+mtUkDpW/fzDkbRsarApIkgdppgbykOxgsR3gGoWZHeklojg7/PWCGVeIhWrtIlyg== X-Received: by 2002:a17:906:5a84:: with SMTP id l4-v6mr9801960ejq.229.1542035940426; Mon, 12 Nov 2018 07:19:00 -0800 (PST) Received: from localhost (pD9E511F8.dip0.t-ipconnect.de. [217.229.17.248]) by smtp.gmail.com with ESMTPSA id h51-v6sm4542879edh.91.2018.11.12.07.18.59 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 12 Nov 2018 07:18:59 -0800 (PST) From: Thierry Reding To: Thierry Reding , Jassi Brar , Greg Kroah-Hartman , Rob Herring Cc: Jiri Slaby , Mikko Perttunen , Jon Hunter , Timo Alho , Pekka Pessi , Mika Liljeberg , linux-tegra@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 03/10] dt-bindings: tegra186-hsp: Add shared mailboxes Date: Mon, 12 Nov 2018 16:18:46 +0100 Message-Id: <20181112151853.29289-4-thierry.reding@gmail.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181112151853.29289-1-thierry.reding@gmail.com> References: <20181112151853.29289-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Mikko Perttunen Shared mailboxes are a mechanism to transport data from one processor in the system to another. They are bidirectional links with both a producer and a consumer. Interrupts are used to let the consumer know when data was written to the mailbox by the producer, and to let the producer know when the consumer has read the data from the mailbox. These interrupts are mapped to one or more "shared interrupts". Typically each processor in the system owns one of these shared interrupts. Add documentation to the device tree bindings about how clients can use mailbox specifiers to request a specific shared mailbox and select which direction they drive. Also document how to specify the shared interrupts in addition to the existing doorbell interrupt. Signed-off-by: Mikko Perttunen Acked-by: Jon Hunter Reviewed-by: Rob Herring Acked-by: Thierry Reding Signed-off-by: Thierry Reding --- Changes in v2: - describe in more detail how the mailbox specifiers are constructed - encode mailbox direction in the device tree mailbox specifier Rob, you had already reviewed this and I've kept your tag for now, even though there have been slight changes in this. If you don't mind taking another look to verify that the changes I've made are still okay. Thanks, Thierry .../bindings/mailbox/nvidia,tegra186-hsp.txt | 30 +++++++++++++++---- include/dt-bindings/mailbox/tegra186-hsp.h | 11 +++++++ 2 files changed, 36 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.txt b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.txt index b99d25fc2f26..ff3eafc5a882 100644 --- a/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.txt +++ b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.txt @@ -15,12 +15,15 @@ Required properties: Array of strings. one of: - "nvidia,tegra186-hsp" + - "nvidia,tegra194-hsp", "nvidia,tegra186-hsp" - reg : Offset and length of the register set for the device. - interrupt-names Array of strings. Contains a list of names for the interrupts described by the interrupt property. May contain the following entries, in any order: - "doorbell" + - "sharedN", where 'N' is a number from zero up to the number of + external interrupts supported by the HSP instance minus one. Users of this binding MUST look up entries in the interrupt property by name, using this interrupt-names property to do so. - interrupts @@ -29,12 +32,29 @@ Required properties: in a matching order. - #mbox-cells : Should be 2. -The mbox specifier of the "mboxes" property in the client node should -contain two data. The first one should be the HSP type and the second -one should be the ID that the client is going to use. Those information -can be found in the following file. +The mbox specifier of the "mboxes" property in the client node should contain +two cells. The first cell determines the HSP type and the second cell is used +to identify the mailbox that the client is going to use. -- . +For doorbells, the second cell specifies the index of the doorbell to use. + +For shared mailboxes, the second cell is composed of two fields: +- bits 31..24: + A bit mask of flags that further specify how the shared mailbox will be + used. Valid flags are: + - bit 31: + Defines the direction of the mailbox. If set, the mailbox will be used + as a producer (i.e. used to send data). If cleared, the mailbox is the + consumer of data sent by a producer. + +- bits 23.. 0: + The index of the shared mailbox to use. The number of available mailboxes + may vary by instance of the HSP block and SoC generation. + +The following file contains definitions that can be used to construct mailbox +specifiers: + + Example: diff --git a/include/dt-bindings/mailbox/tegra186-hsp.h b/include/dt-bindings/mailbox/tegra186-hsp.h index bcab5b7ca785..3bdec7a84d35 100644 --- a/include/dt-bindings/mailbox/tegra186-hsp.h +++ b/include/dt-bindings/mailbox/tegra186-hsp.h @@ -22,4 +22,15 @@ #define TEGRA_HSP_DB_MASTER_CCPLEX 17 #define TEGRA_HSP_DB_MASTER_BPMP 19 +/* + * Shared mailboxes are unidirectional, so the direction needs to be specified + * in the device tree. + */ +#define TEGRA_HSP_SM_MASK 0x00ffffff +#define TEGRA_HSP_SM_FLAG_RX (0 << 31) +#define TEGRA_HSP_SM_FLAG_TX (1 << 31) + +#define TEGRA_HSP_SM_RX(x) (TEGRA_HSP_SM_FLAG_RX | ((x) & TEGRA_HSP_SM_MASK)) +#define TEGRA_HSP_SM_TX(x) (TEGRA_HSP_SM_FLAG_TX | ((x) & TEGRA_HSP_SM_MASK)) + #endif From patchwork Mon Nov 12 15:18:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 996491 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="s7EegOh9"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42tvYS3zynz9s3C for ; Tue, 13 Nov 2018 02:19:08 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729914AbeKMBMr (ORCPT ); Mon, 12 Nov 2018 20:12:47 -0500 Received: from mail-ed1-f65.google.com ([209.85.208.65]:46675 "EHLO mail-ed1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729549AbeKMBMr (ORCPT ); Mon, 12 Nov 2018 20:12:47 -0500 Received: by mail-ed1-f65.google.com with SMTP id b34-v6so7650168ede.13; Mon, 12 Nov 2018 07:19:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=J6dG+vX9VMpwexwuGKQ7BoN/oQ1SKV7iWt2djQB1TKI=; b=s7EegOh96FfLskZzpH+GxCyROrCbiRR17a4dD0nhfG0d+MPnLDNSHk3ywNeIB8IEvS PkItx05djI9eOeyDGUN+/jvX6PMaibA+4gnfiIncfbAtm29dfsgp+UyrcrvCt0RZUzXO q+zQ+o7nzlXLUv7Ao6JZEZrQK/8NTyqDHGmnCl/IE4/SLahWpY1AbrSLoQD0H5wjZCPn vHYH8KqVdlbTfoHClPy55I0L5cj7XUAu64ysSqfptJSKqA4v1GMmxz2o7wPM26xI14Iz MtVLt1RYt9rUYB9A/v3NGMYwYA7ND29QAyDes0HagY2rv+Nso5uq5K2AMFDZLyHeVlM+ 8eOg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=J6dG+vX9VMpwexwuGKQ7BoN/oQ1SKV7iWt2djQB1TKI=; b=ijmvdXgchghK5pPkTGy4j5zARibhcFgG5LX8CyQaG3RYRW29sk28C5G1I1E/296IHi irG9Rc0V/OvT1Wd31N3tcybYV5N61G/fEEIS6IgMj9sXGBkPdaD+VuYeU0dGFwC8KobV mzsMiSl1Jc8F3eXDcaSodykFLzxS7SWebBsfAGKuMWFtWA/UY90XWAFruKLllIHO+tae lFRLsX5NaRaKIXfJADkIYZ0cYzm9r/dMuip/5itIe/zcbsZHjdVuzsaQTMt/tprhdaLM 0DuSDT/w6nl+1nSwWyhHcFp1WJyvecyDWwYZOdO2IuZvm6jHncH8x6UQ+evKN1IrrPp2 a4ww== X-Gm-Message-State: AGRZ1gKd5Ntv/pKtESDGZS2Z30+IngmlZ748rpFjXGqopDEisMsKBMMZ kQNkwnELgErH32dhsiTDuJs= X-Google-Smtp-Source: AJdET5esoCTV4rPMpIyWXsPyrCz+yqb7amAwOxqZgSMu7Pzx/6ZvXE9P11FV4Hgow4bSYnLSXzN54g== X-Received: by 2002:a50:a602:: with SMTP id d2-v6mr13137863edc.8.1542035942115; Mon, 12 Nov 2018 07:19:02 -0800 (PST) Received: from localhost (pD9E511F8.dip0.t-ipconnect.de. [217.229.17.248]) by smtp.gmail.com with ESMTPSA id g40sm2291899edg.39.2018.11.12.07.19.01 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 12 Nov 2018 07:19:01 -0800 (PST) From: Thierry Reding To: Thierry Reding , Jassi Brar , Greg Kroah-Hartman Cc: Jiri Slaby , Mikko Perttunen , Jon Hunter , Timo Alho , Pekka Pessi , Mika Liljeberg , linux-tegra@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 04/10] mailbox: tegra-hsp: Add support for shared mailboxes Date: Mon, 12 Nov 2018 16:18:47 +0100 Message-Id: <20181112151853.29289-5-thierry.reding@gmail.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181112151853.29289-1-thierry.reding@gmail.com> References: <20181112151853.29289-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The Tegra HSP block supports 'shared mailboxes' that are simple 32-bit registers consisting of a FULL bit in MSB position and 31 bits of data. The hardware can be configured to trigger interrupts when a mailbox is empty or full. Add support for these shared mailboxes to the HSP driver. The initial use for the mailboxes is the Tegra Combined UART. For this purpose, we use interrupts to receive data, and spinning to wait for the transmit mailbox to be emptied to minimize unnecessary overhead. Based on work by Mikko Perttunen . Signed-off-by: Thierry Reding --- Changes in v2: - do not write per-mailbox interrupt enable registers on Tegra186 - merge handlers for empty and full interrupts - track direction of shared mailboxes drivers/mailbox/tegra-hsp.c | 498 +++++++++++++++++++++++++++++++----- 1 file changed, 437 insertions(+), 61 deletions(-) diff --git a/drivers/mailbox/tegra-hsp.c b/drivers/mailbox/tegra-hsp.c index 0cde356c11ab..0100a974149b 100644 --- a/drivers/mailbox/tegra-hsp.c +++ b/drivers/mailbox/tegra-hsp.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -11,6 +11,7 @@ * more details. */ +#include #include #include #include @@ -21,6 +22,17 @@ #include +#include "mailbox.h" + +#define HSP_INT_IE(x) (0x100 + ((x) * 4)) +#define HSP_INT_IV 0x300 +#define HSP_INT_IR 0x304 + +#define HSP_INT_EMPTY_SHIFT 0 +#define HSP_INT_EMPTY_MASK 0xff +#define HSP_INT_FULL_SHIFT 8 +#define HSP_INT_FULL_MASK 0xff + #define HSP_INT_DIMENSIONING 0x380 #define HSP_nSM_SHIFT 0 #define HSP_nSS_SHIFT 4 @@ -34,6 +46,11 @@ #define HSP_DB_RAW 0x8 #define HSP_DB_PENDING 0xc +#define HSP_SM_SHRD_MBOX 0x0 +#define HSP_SM_SHRD_MBOX_FULL BIT(31) +#define HSP_SM_SHRD_MBOX_FULL_INT_IE 0x04 +#define HSP_SM_SHRD_MBOX_EMPTY_INT_IE 0x08 + #define HSP_DB_CCPLEX 1 #define HSP_DB_BPMP 3 #define HSP_DB_MAX 7 @@ -55,6 +72,12 @@ struct tegra_hsp_doorbell { unsigned int index; }; +struct tegra_hsp_mailbox { + struct tegra_hsp_channel channel; + unsigned int index; + bool producer; +}; + struct tegra_hsp_db_map { const char *name; unsigned int master; @@ -63,13 +86,18 @@ struct tegra_hsp_db_map { struct tegra_hsp_soc { const struct tegra_hsp_db_map *map; + bool has_per_mb_ie; }; struct tegra_hsp { + struct device *dev; const struct tegra_hsp_soc *soc; - struct mbox_controller mbox; + struct mbox_controller mbox_db; + struct mbox_controller mbox_sm; void __iomem *regs; - unsigned int irq; + unsigned int doorbell_irq; + unsigned int *shared_irqs; + unsigned int shared_irq; unsigned int num_sm; unsigned int num_as; unsigned int num_ss; @@ -78,13 +106,10 @@ struct tegra_hsp { spinlock_t lock; struct list_head doorbells; -}; + struct tegra_hsp_mailbox *mailboxes; -static inline struct tegra_hsp * -to_tegra_hsp(struct mbox_controller *mbox) -{ - return container_of(mbox, struct tegra_hsp, mbox); -} + unsigned long mask; +}; static inline u32 tegra_hsp_readl(struct tegra_hsp *hsp, unsigned int offset) { @@ -158,7 +183,7 @@ static irqreturn_t tegra_hsp_doorbell_irq(int irq, void *data) spin_lock(&hsp->lock); - for_each_set_bit(master, &value, hsp->mbox.num_chans) { + for_each_set_bit(master, &value, hsp->mbox_db.num_chans) { struct tegra_hsp_doorbell *db; db = __tegra_hsp_doorbell_get(hsp, master); @@ -182,6 +207,71 @@ static irqreturn_t tegra_hsp_doorbell_irq(int irq, void *data) return IRQ_HANDLED; } +static irqreturn_t tegra_hsp_shared_irq(int irq, void *data) +{ + struct tegra_hsp *hsp = data; + unsigned long bit, mask; + u32 status, value; + void *msg; + + status = tegra_hsp_readl(hsp, HSP_INT_IR) & hsp->mask; + + /* process EMPTY interrupts first */ + mask = (status >> HSP_INT_EMPTY_SHIFT) & HSP_INT_EMPTY_MASK; + + for_each_set_bit(bit, &mask, hsp->num_sm) { + struct tegra_hsp_mailbox *mb = &hsp->mailboxes[bit]; + + if (mb->producer) { + /* + * Disable EMPTY interrupts until data is sent with + * the next message. These interrupts are level- + * triggered, so if we kept them enabled they would + * constantly trigger until we next write data into + * the message. + */ + spin_lock(&hsp->lock); + + hsp->mask &= ~BIT(HSP_INT_EMPTY_SHIFT + mb->index); + tegra_hsp_writel(hsp, hsp->mask, + HSP_INT_IE(hsp->shared_irq)); + + spin_unlock(&hsp->lock); + + mbox_chan_txdone(mb->channel.chan, 0); + } + } + + /* process FULL interrupts */ + mask = (status >> HSP_INT_FULL_SHIFT) & HSP_INT_FULL_MASK; + + for_each_set_bit(bit, &mask, hsp->num_sm) { + struct tegra_hsp_mailbox *mb = &hsp->mailboxes[bit]; + + if (!mb->producer) { + value = tegra_hsp_channel_readl(&mb->channel, + HSP_SM_SHRD_MBOX); + value &= ~HSP_SM_SHRD_MBOX_FULL; + msg = (void *)(unsigned long)value; + mbox_chan_received_data(mb->channel.chan, msg); + + /* + * Need to clear all bits here since some producers, + * such as TCU, depend on fields in the register + * getting cleared by the consumer. + * + * The mailbox API doesn't give the consumers a way + * of doing that explicitly, so we have to make sure + * we cover all possible cases. + */ + tegra_hsp_channel_writel(&mb->channel, 0x0, + HSP_SM_SHRD_MBOX); + } + } + + return IRQ_HANDLED; +} + static struct tegra_hsp_channel * tegra_hsp_doorbell_create(struct tegra_hsp *hsp, const char *name, unsigned int master, unsigned int index) @@ -194,7 +284,7 @@ tegra_hsp_doorbell_create(struct tegra_hsp *hsp, const char *name, if (!db) return ERR_PTR(-ENOMEM); - offset = (1 + (hsp->num_sm / 2) + hsp->num_ss + hsp->num_as) << 16; + offset = (1 + (hsp->num_sm / 2) + hsp->num_ss + hsp->num_as) * SZ_64K; offset += index * 0x100; db->channel.regs = hsp->regs + offset; @@ -235,8 +325,8 @@ static int tegra_hsp_doorbell_startup(struct mbox_chan *chan) unsigned long flags; u32 value; - if (db->master >= hsp->mbox.num_chans) { - dev_err(hsp->mbox.dev, + if (db->master >= chan->mbox->num_chans) { + dev_err(chan->mbox->dev, "invalid master ID %u for HSP channel\n", db->master); return -EINVAL; @@ -281,46 +371,168 @@ static void tegra_hsp_doorbell_shutdown(struct mbox_chan *chan) spin_unlock_irqrestore(&hsp->lock, flags); } -static const struct mbox_chan_ops tegra_hsp_doorbell_ops = { +static const struct mbox_chan_ops tegra_hsp_db_ops = { .send_data = tegra_hsp_doorbell_send_data, .startup = tegra_hsp_doorbell_startup, .shutdown = tegra_hsp_doorbell_shutdown, }; -static struct mbox_chan *of_tegra_hsp_xlate(struct mbox_controller *mbox, +static int tegra_hsp_mailbox_send_data(struct mbox_chan *chan, void *data) +{ + struct tegra_hsp_mailbox *mb = chan->con_priv; + struct tegra_hsp *hsp = mb->channel.hsp; + unsigned long flags; + u32 value; + + WARN_ON(!mb->producer); + + /* copy data and mark mailbox full */ + value = (u32)(unsigned long)data; + value |= HSP_SM_SHRD_MBOX_FULL; + + tegra_hsp_channel_writel(&mb->channel, value, HSP_SM_SHRD_MBOX); + + if (!irqs_disabled()) { + /* enable EMPTY interrupt for the shared mailbox */ + spin_lock_irqsave(&hsp->lock, flags); + + hsp->mask |= BIT(HSP_INT_EMPTY_SHIFT + mb->index); + tegra_hsp_writel(hsp, hsp->mask, HSP_INT_IE(hsp->shared_irq)); + + spin_unlock_irqrestore(&hsp->lock, flags); + } + + return 0; +} + +static int tegra_hsp_mailbox_flush(struct mbox_chan *chan, + unsigned long timeout) +{ + struct tegra_hsp_mailbox *mb = chan->con_priv; + struct tegra_hsp_channel *ch = &mb->channel; + u32 value; + + timeout = jiffies + msecs_to_jiffies(timeout); + + while (time_before(jiffies, timeout)) { + value = tegra_hsp_channel_readl(ch, HSP_SM_SHRD_MBOX); + if ((value & HSP_SM_SHRD_MBOX_FULL) == 0) { + mbox_chan_txdone(chan, 0); + return 0; + } + + udelay(1); + } + + return -ETIME; +} + +static int tegra_hsp_mailbox_startup(struct mbox_chan *chan) +{ + struct tegra_hsp_mailbox *mb = chan->con_priv; + struct tegra_hsp_channel *ch = &mb->channel; + struct tegra_hsp *hsp = mb->channel.hsp; + unsigned long flags; + + chan->txdone_method = TXDONE_BY_IRQ; + + /* + * Shared mailboxes start out as consumers by default. FULL and EMPTY + * interrupts are coalesced at the same shared interrupt. + * + * Keep EMPTY interrupts disabled at startup and only enable them when + * the mailbox is actually full. This is required because the FULL and + * EMPTY interrupts are level-triggered, so keeping EMPTY interrupts + * enabled all the time would cause an interrupt storm while mailboxes + * are idle. + */ + + spin_lock_irqsave(&hsp->lock, flags); + + if (mb->producer) + hsp->mask &= ~BIT(HSP_INT_EMPTY_SHIFT + mb->index); + else + hsp->mask |= BIT(HSP_INT_FULL_SHIFT + mb->index); + + tegra_hsp_writel(hsp, hsp->mask, HSP_INT_IE(hsp->shared_irq)); + + spin_unlock_irqrestore(&hsp->lock, flags); + + if (hsp->soc->has_per_mb_ie) { + if (mb->producer) + tegra_hsp_channel_writel(ch, 0x0, + HSP_SM_SHRD_MBOX_EMPTY_INT_IE); + else + tegra_hsp_channel_writel(ch, 0x1, + HSP_SM_SHRD_MBOX_FULL_INT_IE); + } + + return 0; +} + +static void tegra_hsp_mailbox_shutdown(struct mbox_chan *chan) +{ + struct tegra_hsp_mailbox *mb = chan->con_priv; + struct tegra_hsp_channel *ch = &mb->channel; + struct tegra_hsp *hsp = mb->channel.hsp; + unsigned long flags; + + if (hsp->soc->has_per_mb_ie) { + if (mb->producer) + tegra_hsp_channel_writel(ch, 0x0, + HSP_SM_SHRD_MBOX_EMPTY_INT_IE); + else + tegra_hsp_channel_writel(ch, 0x0, + HSP_SM_SHRD_MBOX_FULL_INT_IE); + } + + spin_lock_irqsave(&hsp->lock, flags); + + if (mb->producer) + hsp->mask &= ~BIT(HSP_INT_EMPTY_SHIFT + mb->index); + else + hsp->mask &= ~BIT(HSP_INT_FULL_SHIFT + mb->index); + + tegra_hsp_writel(hsp, hsp->mask, HSP_INT_IE(hsp->shared_irq)); + + spin_unlock_irqrestore(&hsp->lock, flags); +} + +static const struct mbox_chan_ops tegra_hsp_sm_ops = { + .send_data = tegra_hsp_mailbox_send_data, + .flush = tegra_hsp_mailbox_flush, + .startup = tegra_hsp_mailbox_startup, + .shutdown = tegra_hsp_mailbox_shutdown, +}; + +static struct mbox_chan *tegra_hsp_db_xlate(struct mbox_controller *mbox, const struct of_phandle_args *args) { + struct tegra_hsp *hsp = container_of(mbox, struct tegra_hsp, mbox_db); + unsigned int type = args->args[0], master = args->args[1]; struct tegra_hsp_channel *channel = ERR_PTR(-ENODEV); - struct tegra_hsp *hsp = to_tegra_hsp(mbox); - unsigned int type = args->args[0]; - unsigned int master = args->args[1]; struct tegra_hsp_doorbell *db; struct mbox_chan *chan; unsigned long flags; unsigned int i; - switch (type) { - case TEGRA_HSP_MBOX_TYPE_DB: - db = tegra_hsp_doorbell_get(hsp, master); - if (db) - channel = &db->channel; + if (type != TEGRA_HSP_MBOX_TYPE_DB || !hsp->doorbell_irq) + return ERR_PTR(-ENODEV); - break; - - default: - break; - } + db = tegra_hsp_doorbell_get(hsp, master); + if (db) + channel = &db->channel; if (IS_ERR(channel)) return ERR_CAST(channel); spin_lock_irqsave(&hsp->lock, flags); - for (i = 0; i < hsp->mbox.num_chans; i++) { - chan = &hsp->mbox.chans[i]; + for (i = 0; i < mbox->num_chans; i++) { + chan = &mbox->chans[i]; if (!chan->con_priv) { - chan->con_priv = channel; channel->chan = chan; + chan->con_priv = db; break; } @@ -332,6 +544,29 @@ static struct mbox_chan *of_tegra_hsp_xlate(struct mbox_controller *mbox, return chan ?: ERR_PTR(-EBUSY); } +static struct mbox_chan *tegra_hsp_sm_xlate(struct mbox_controller *mbox, + const struct of_phandle_args *args) +{ + struct tegra_hsp *hsp = container_of(mbox, struct tegra_hsp, mbox_sm); + unsigned int type = args->args[0], index; + struct tegra_hsp_mailbox *mb; + + index = args->args[1] & TEGRA_HSP_SM_MASK; + + if (type != TEGRA_HSP_MBOX_TYPE_SM || !hsp->shared_irqs || + index >= hsp->num_sm) + return ERR_PTR(-ENODEV); + + mb = &hsp->mailboxes[index]; + + if ((args->args[1] & TEGRA_HSP_SM_FLAG_TX) == 0) + mb->producer = false; + else + mb->producer = true; + + return mb->channel.chan; +} + static void tegra_hsp_remove_doorbells(struct tegra_hsp *hsp) { struct tegra_hsp_doorbell *db, *tmp; @@ -364,10 +599,65 @@ static int tegra_hsp_add_doorbells(struct tegra_hsp *hsp) return 0; } +static int tegra_hsp_add_mailboxes(struct tegra_hsp *hsp, struct device *dev) +{ + int i; + + hsp->mailboxes = devm_kcalloc(dev, hsp->num_sm, sizeof(*hsp->mailboxes), + GFP_KERNEL); + if (!hsp->mailboxes) + return -ENOMEM; + + for (i = 0; i < hsp->num_sm; i++) { + struct tegra_hsp_mailbox *mb = &hsp->mailboxes[i]; + + mb->index = i; + + mb->channel.hsp = hsp; + mb->channel.regs = hsp->regs + SZ_64K + i * SZ_32K; + mb->channel.chan = &hsp->mbox_sm.chans[i]; + mb->channel.chan->con_priv = mb; + } + + return 0; +} + +static int tegra_hsp_request_shared_irqs(struct tegra_hsp *hsp) +{ + unsigned int i, irq = 0; + int err; + + for (i = 0; i < hsp->num_si; i++) { + if (hsp->shared_irq == 0 && hsp->shared_irqs[i] > 0) { + irq = hsp->shared_irqs[i]; + hsp->shared_irq = i; + break; + } + } + + if (irq > 0) { + err = devm_request_irq(hsp->dev, irq, tegra_hsp_shared_irq, 0, + dev_name(hsp->dev), hsp); + if (err < 0) { + dev_err(hsp->dev, "failed to request interrupt: %d\n", + err); + return err; + } + + /* disable all interrupts */ + tegra_hsp_writel(hsp, 0, HSP_INT_IE(hsp->shared_irq)); + + dev_dbg(hsp->dev, "interrupt requested: %u\n", irq); + } + + return 0; +} + static int tegra_hsp_probe(struct platform_device *pdev) { struct tegra_hsp *hsp; struct resource *res; + unsigned int i; u32 value; int err; @@ -375,6 +665,7 @@ static int tegra_hsp_probe(struct platform_device *pdev) if (!hsp) return -ENOMEM; + hsp->dev = &pdev->dev; hsp->soc = of_device_get_match_data(&pdev->dev); INIT_LIST_HEAD(&hsp->doorbells); spin_lock_init(&hsp->lock); @@ -392,58 +683,136 @@ static int tegra_hsp_probe(struct platform_device *pdev) hsp->num_si = (value >> HSP_nSI_SHIFT) & HSP_nINT_MASK; err = platform_get_irq_byname(pdev, "doorbell"); - if (err < 0) { - dev_err(&pdev->dev, "failed to get doorbell IRQ: %d\n", err); - return err; + if (err >= 0) + hsp->doorbell_irq = err; + + if (hsp->num_si > 0) { + unsigned int count = 0; + + hsp->shared_irqs = devm_kcalloc(&pdev->dev, hsp->num_si, + sizeof(*hsp->shared_irqs), + GFP_KERNEL); + if (!hsp->shared_irqs) + return -ENOMEM; + + for (i = 0; i < hsp->num_si; i++) { + char *name; + + name = kasprintf(GFP_KERNEL, "shared%u", i); + if (!name) + return -ENOMEM; + + err = platform_get_irq_byname(pdev, name); + if (err >= 0) { + hsp->shared_irqs[i] = err; + count++; + } + + kfree(name); + } + + if (count == 0) { + devm_kfree(&pdev->dev, hsp->shared_irqs); + hsp->shared_irqs = NULL; + } + } + + /* setup the doorbell controller */ + hsp->mbox_db.of_xlate = tegra_hsp_db_xlate; + hsp->mbox_db.num_chans = 32; + hsp->mbox_db.dev = &pdev->dev; + hsp->mbox_db.ops = &tegra_hsp_db_ops; + + hsp->mbox_db.chans = devm_kcalloc(&pdev->dev, hsp->mbox_db.num_chans, + sizeof(*hsp->mbox_db.chans), + GFP_KERNEL); + if (!hsp->mbox_db.chans) + return -ENOMEM; + + if (hsp->doorbell_irq) { + err = tegra_hsp_add_doorbells(hsp); + if (err < 0) { + dev_err(&pdev->dev, "failed to add doorbells: %d\n", + err); + return err; + } } - hsp->irq = err; + err = mbox_controller_register(&hsp->mbox_db); + if (err < 0) { + dev_err(&pdev->dev, "failed to register doorbell mailbox: %d\n", err); + goto remove_doorbells; + } - hsp->mbox.of_xlate = of_tegra_hsp_xlate; - hsp->mbox.num_chans = 32; - hsp->mbox.dev = &pdev->dev; - hsp->mbox.txdone_irq = false; - hsp->mbox.txdone_poll = false; - hsp->mbox.ops = &tegra_hsp_doorbell_ops; + /* setup the shared mailbox controller */ + hsp->mbox_sm.of_xlate = tegra_hsp_sm_xlate; + hsp->mbox_sm.num_chans = hsp->num_sm; + hsp->mbox_sm.dev = &pdev->dev; + hsp->mbox_sm.ops = &tegra_hsp_sm_ops; - hsp->mbox.chans = devm_kcalloc(&pdev->dev, hsp->mbox.num_chans, - sizeof(*hsp->mbox.chans), - GFP_KERNEL); - if (!hsp->mbox.chans) + hsp->mbox_sm.chans = devm_kcalloc(&pdev->dev, hsp->mbox_sm.num_chans, + sizeof(*hsp->mbox_sm.chans), + GFP_KERNEL); + if (!hsp->mbox_sm.chans) return -ENOMEM; - err = tegra_hsp_add_doorbells(hsp); + if (hsp->shared_irqs) { + err = tegra_hsp_add_mailboxes(hsp, &pdev->dev); + if (err < 0) { + dev_err(&pdev->dev, "failed to add mailboxes: %d\n", + err); + goto unregister_mbox_db; + } + } + + err = mbox_controller_register(&hsp->mbox_sm); if (err < 0) { - dev_err(&pdev->dev, "failed to add doorbells: %d\n", err); - return err; + dev_err(&pdev->dev, "failed to register shared mailbox: %d\n", err); + goto unregister_mbox_db; } platform_set_drvdata(pdev, hsp); - err = mbox_controller_register(&hsp->mbox); - if (err) { - dev_err(&pdev->dev, "failed to register mailbox: %d\n", err); - tegra_hsp_remove_doorbells(hsp); - return err; + if (hsp->doorbell_irq) { + err = devm_request_irq(&pdev->dev, hsp->doorbell_irq, + tegra_hsp_doorbell_irq, IRQF_NO_SUSPEND, + dev_name(&pdev->dev), hsp); + if (err < 0) { + dev_err(&pdev->dev, + "failed to request doorbell IRQ#%u: %d\n", + hsp->doorbell_irq, err); + goto unregister_mbox_sm; + } } - err = devm_request_irq(&pdev->dev, hsp->irq, tegra_hsp_doorbell_irq, - IRQF_NO_SUSPEND, dev_name(&pdev->dev), hsp); - if (err < 0) { - dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", - hsp->irq, err); - return err; + if (hsp->shared_irqs) { + err = tegra_hsp_request_shared_irqs(hsp); + if (err < 0) + goto unregister_mbox_sm; } return 0; + +unregister_mbox_sm: + mbox_controller_unregister(&hsp->mbox_sm); +unregister_mbox_db: + mbox_controller_unregister(&hsp->mbox_db); +remove_doorbells: + if (hsp->doorbell_irq) + tegra_hsp_remove_doorbells(hsp); + + return err; } static int tegra_hsp_remove(struct platform_device *pdev) { struct tegra_hsp *hsp = platform_get_drvdata(pdev); - mbox_controller_unregister(&hsp->mbox); - tegra_hsp_remove_doorbells(hsp); + mbox_controller_unregister(&hsp->mbox_sm); + mbox_controller_unregister(&hsp->mbox_db); + + if (hsp->doorbell_irq) + tegra_hsp_remove_doorbells(hsp); return 0; } @@ -456,10 +825,17 @@ static const struct tegra_hsp_db_map tegra186_hsp_db_map[] = { static const struct tegra_hsp_soc tegra186_hsp_soc = { .map = tegra186_hsp_db_map, + .has_per_mb_ie = false, +}; + +static const struct tegra_hsp_soc tegra194_hsp_soc = { + .map = tegra186_hsp_db_map, + .has_per_mb_ie = true, }; static const struct of_device_id tegra_hsp_match[] = { { .compatible = "nvidia,tegra186-hsp", .data = &tegra186_hsp_soc }, + { .compatible = "nvidia,tegra194-hsp", .data = &tegra194_hsp_soc }, { } }; From patchwork Mon Nov 12 15:18:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 996490 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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[217.229.17.248]) by smtp.gmail.com with ESMTPSA id i10-v6sm2370142ejh.71.2018.11.12.07.19.02 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 12 Nov 2018 07:19:03 -0800 (PST) From: Thierry Reding To: Thierry Reding , Jassi Brar , Greg Kroah-Hartman Cc: Jiri Slaby , Mikko Perttunen , Jon Hunter , Timo Alho , Pekka Pessi , Mika Liljeberg , linux-tegra@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 05/10] mailbox: tegra-hsp: Add suspend/resume support Date: Mon, 12 Nov 2018 16:18:48 +0100 Message-Id: <20181112151853.29289-6-thierry.reding@gmail.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181112151853.29289-1-thierry.reding@gmail.com> References: <20181112151853.29289-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding Upon resuming from a system sleep state, the interrupts for all active shared mailboxes need to be reenabled, otherwise they will not work. Signed-off-by: Thierry Reding --- drivers/mailbox/tegra-hsp.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/mailbox/tegra-hsp.c b/drivers/mailbox/tegra-hsp.c index 0100a974149b..1259abf3542f 100644 --- a/drivers/mailbox/tegra-hsp.c +++ b/drivers/mailbox/tegra-hsp.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include @@ -817,6 +818,23 @@ static int tegra_hsp_remove(struct platform_device *pdev) return 0; } +static int tegra_hsp_resume(struct device *dev) +{ + struct tegra_hsp *hsp = dev_get_drvdata(dev); + unsigned int i; + + for (i = 0; i < hsp->num_sm; i++) { + struct tegra_hsp_mailbox *mb = &hsp->mailboxes[i]; + + if (mb->channel.chan->cl) + tegra_hsp_mailbox_startup(mb->channel.chan); + } + + return 0; +} + +static SIMPLE_DEV_PM_OPS(tegra_hsp_pm_ops, NULL, tegra_hsp_resume); + static const struct tegra_hsp_db_map tegra186_hsp_db_map[] = { { "ccplex", TEGRA_HSP_DB_MASTER_CCPLEX, HSP_DB_CCPLEX, }, { "bpmp", TEGRA_HSP_DB_MASTER_BPMP, HSP_DB_BPMP, }, @@ -843,6 +861,7 @@ static struct platform_driver tegra_hsp_driver = { .driver = { .name = "tegra-hsp", .of_match_table = tegra_hsp_match, + .pm = &tegra_hsp_pm_ops, }, .probe = tegra_hsp_probe, .remove = tegra_hsp_remove, From patchwork Mon Nov 12 15:18:49 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 996493 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="cbqwRGAE"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42tvYV1lkvz9s1x for ; Tue, 13 Nov 2018 02:19:10 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729928AbeKMBMs (ORCPT ); Mon, 12 Nov 2018 20:12:48 -0500 Received: from mail-ed1-f66.google.com ([209.85.208.66]:33223 "EHLO mail-ed1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729825AbeKMBMr (ORCPT ); Mon, 12 Nov 2018 20:12:47 -0500 Received: by mail-ed1-f66.google.com with SMTP id r27so4719980eda.0; Mon, 12 Nov 2018 07:19:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=TlbHTmIMzaAHQga/bhk4fz7pIJkLJdzOm9HKY5RROAs=; b=cbqwRGAEpm54pUB3uZltMFMdRHUcCOFXMQN5AKR/zQ16/U8zBkrgT5Wof6bIfEHbFR xlwKRlsAtt9RCgr41KlceuLPfHgMywnK/lzEnRoWvjZ1DU4QvEsQJXNlJY1Cn7t35wBs ej5c2n5kDxmAZNVsTgAFvTi8PFG7PclaWFp2+lJb5By97u6vb0SXNCO3A3jgrLeGzSLc fj33qKIu6t6PpVmJWcjXSpU5oEFoEdDT3D4MdU0nTlaXjsJtZWHCtN1cR+ccyTcmhA1E UEgxrK4KqWZYpHfihRZqD5QXgwCIjCyvWVqqpbX5L312HG8DpdSE1NjsZjMEBbVci9QF zkPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TlbHTmIMzaAHQga/bhk4fz7pIJkLJdzOm9HKY5RROAs=; b=esMk58rXMY8J778Xw2Yo4cTVaHjbWH6r3HY9MalRsizNIeDSnzRfHZIF2YpGYQxwCi LxkX7pDX8/Jt7cEniNDnojIGCp0uwQZaS6iCiNhFY2gOsCedrWj5hgWuZLNxScA0OLxW UepzC44xpxklXIiKfEq8K2Zw2mTPygdkfMqQv4zn3tsr/BW0QsghsD9MegCpn2+8x4hB PplmjOgCQODm6GCJePrAtKArxrjylPhiXB8HkZfjdYrMdftWY5rDfnJpjLCfPyP+p2PK P5zpRBtCwrvd3mWQQac/GokK+NgXcgMsSz6/ACiT3v+rhYPGvKWypvfDkuXq8Ukay3Qc 1yPQ== X-Gm-Message-State: AGRZ1gI7sY/3KSwkzdnOuALQCs2uUQH15NS2MZKCpEoMq1nkq3aQ9lUu /ZvdNQsbsAG6olVgzZfnU7s= X-Google-Smtp-Source: AJdET5eMunoXP88kxBYlQj4J5/HRu3dPLtk4RtlQJPlALDCgqNuXPWHNGX0Cwhwp1v1obg3ZXX+pHA== X-Received: by 2002:a17:906:4e82:: with SMTP id v2-v6mr9627444eju.149.1542035945251; Mon, 12 Nov 2018 07:19:05 -0800 (PST) Received: from localhost (pD9E511F8.dip0.t-ipconnect.de. [217.229.17.248]) by smtp.gmail.com with ESMTPSA id c23-v6sm1261556ejb.62.2018.11.12.07.19.04 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 12 Nov 2018 07:19:04 -0800 (PST) From: Thierry Reding To: Thierry Reding , Jassi Brar , Greg Kroah-Hartman Cc: Jiri Slaby , Mikko Perttunen , Jon Hunter , Timo Alho , Pekka Pessi , Mika Liljeberg , linux-tegra@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 06/10] dt-bindings: serial: Add bindings for nvidia, tegra194-tcu Date: Mon, 12 Nov 2018 16:18:49 +0100 Message-Id: <20181112151853.29289-7-thierry.reding@gmail.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181112151853.29289-1-thierry.reding@gmail.com> References: <20181112151853.29289-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Mikko Perttunen Add bindings for the Tegra Combined UART device used to talk to the UART console on Tegra194 systems. Signed-off-by: Mikko Perttunen Reviewed-by: Rob Herring Acked-by: Jon Hunter Acked-by: Thierry Reding Signed-off-by: Thierry Reding --- .../bindings/serial/nvidia,tegra194-tcu.txt | 35 +++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.txt diff --git a/Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.txt b/Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.txt new file mode 100644 index 000000000000..085a8591accd --- /dev/null +++ b/Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.txt @@ -0,0 +1,35 @@ +NVIDIA Tegra Combined UART (TCU) + +The TCU is a system for sharing a hardware UART instance among multiple +systems within the Tegra SoC. It is implemented through a mailbox- +based protocol where each "virtual UART" has a pair of mailboxes, one +for transmitting and one for receiving, that is used to communicate +with the hardware implementing the TCU. + +Required properties: +- name : Should be tcu +- compatible + Array of strings + One of: + - "nvidia,tegra194-tcu" +- mbox-names: + "rx" - Mailbox for receiving data from hardware UART + "tx" - Mailbox for transmitting data to hardware UART +- mboxes: Mailboxes corresponding to the mbox-names. + +This node is a mailbox consumer. See the following files for details of +the mailbox subsystem, and the specifiers implemented by the relevant +provider(s): + +- .../mailbox/mailbox.txt +- .../mailbox/nvidia,tegra186-hsp.txt + +Example bindings: +----------------- + +tcu: tcu { + compatible = "nvidia,tegra194-tcu"; + mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM 0>, + <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM 1>; + mbox-names = "rx", "tx"; +}; From patchwork Mon Nov 12 15:18:50 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 996495 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="eL9ey71c"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42tvYY2QDkz9s47 for ; Tue, 13 Nov 2018 02:19:13 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729955AbeKMBMv (ORCPT ); Mon, 12 Nov 2018 20:12:51 -0500 Received: from mail-ed1-f68.google.com ([209.85.208.68]:33228 "EHLO mail-ed1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729825AbeKMBMv (ORCPT ); Mon, 12 Nov 2018 20:12:51 -0500 Received: by mail-ed1-f68.google.com with SMTP id r27so4720079eda.0; Mon, 12 Nov 2018 07:19:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UJeDAAQT3FcRXSpRB+VDfAxX5Tfak4Exo42W5TfLOqw=; b=eL9ey71cVCJhkAWH/dhP/K2DZtAdtTLkFEJ2bTuAsi61bSJWQNsxfpLUI06biE7OKz uKMrXud82NEHVQh52INgjrObmHEdZVney/e+JPODCUURLFnoyKkd95WMo33H0Gxn0lyT bJWP3O94sJZBXPi6VnUfrPwd2/74YW8whb9Mh1Z17Zc5CVjEoF5ZCAhamsvAn0eyRB1I 9c0vN32LK3FoQ8WPQhK+IAmQU0RO7XVpBrtL+vf/5fKGxrH6YRBO6PB57xrCOXGlYPQA LVUCCM8GvjheU8a7iESRKXRD/EhT6NTv5vODxcxlAcycfTArNpBNHsyfFT2wn1QlZHs/ AB/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UJeDAAQT3FcRXSpRB+VDfAxX5Tfak4Exo42W5TfLOqw=; b=FVYIfRWj9wkqq3bRhxtSv3lnNI6OL0AyZbDkHmryCQcvV9YwY2X9LUvkKKLScwkjOn ppEP3gs1cS4nlm0YPpbz6ezCA3ThAWxbm6PPB9dxTbDzEgnJgWiH2mtoevdYbWInYLe7 y+GcJOx7osGAu5jVGPR14LX2PptunAI6rvJwkqaqFdIRrrZ9uI+q9S9CLCUfsfBisSjL CcLRYFqDC2AJOotTe/Owzmu0LeHXitxa8TzGUYG2tVHt3aNhf6K5vnSqE23wxma4ZcoD 20q3S0JTetqGUGoCZPHNp1ZLHOWkoAjIs2JQI8sL/rT+PfR1DwUlM6MYAvVIonrI+f8O MpUw== X-Gm-Message-State: AGRZ1gJcepyj3a6xKk6SjOtGSMAFTwnW6aba3i+rvLsVY8c0KMIPvHh0 VAq0b20FYeMETUZDpwcCeUU= X-Google-Smtp-Source: AJdET5dJbnfYI/FeABq0j7ycIm/vn8ZV9Pd7xf6WA2hcv4XQTIhLMeiDkJJtttFN0ZoaGjy1fYui0w== X-Received: by 2002:a17:906:6442:: with SMTP id l2-v6mr9132630ejn.73.1542035946800; Mon, 12 Nov 2018 07:19:06 -0800 (PST) Received: from localhost (pD9E511F8.dip0.t-ipconnect.de. [217.229.17.248]) by smtp.gmail.com with ESMTPSA id j9-v6sm4554174edk.88.2018.11.12.07.19.05 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 12 Nov 2018 07:19:06 -0800 (PST) From: Thierry Reding To: Thierry Reding , Jassi Brar , Greg Kroah-Hartman Cc: Jiri Slaby , Mikko Perttunen , Jon Hunter , Timo Alho , Pekka Pessi , Mika Liljeberg , linux-tegra@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 07/10] serial: Add Tegra Combined UART driver Date: Mon, 12 Nov 2018 16:18:50 +0100 Message-Id: <20181112151853.29289-8-thierry.reding@gmail.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181112151853.29289-1-thierry.reding@gmail.com> References: <20181112151853.29289-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The Tegra Combined UART (TCU) is a mailbox-based mechanism that allows multiplexing multiple "virtual UARTs" into a single hardware serial port. The TCU is the primary serial port on Tegra194 devices. Add a TCU driver utilizing the mailbox framework, as the used mailboxes are part of Tegra HSP blocks that are already controlled by the Tegra HSP mailbox driver. Based on work by Mikko Perttunen . Acked-by: Greg Kroah-Hartman Signed-off-by: Thierry Reding --- drivers/tty/serial/Kconfig | 22 +++ drivers/tty/serial/Makefile | 1 + drivers/tty/serial/tegra-tcu.c | 299 +++++++++++++++++++++++++++++++ include/uapi/linux/serial_core.h | 3 + 4 files changed, 325 insertions(+) create mode 100644 drivers/tty/serial/tegra-tcu.c diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig index 32886c304641..785306388aa4 100644 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig @@ -323,6 +323,28 @@ config SERIAL_TEGRA are enabled). This driver uses the APB DMA to achieve higher baudrate and better performance. +config SERIAL_TEGRA_TCU + tristate "NVIDIA Tegra Combined UART" + depends on ARCH_TEGRA && TEGRA_HSP_MBOX + select SERIAL_CORE + help + Support for the mailbox-based TCU (Tegra Combined UART) serial port. + TCU is a virtual serial port that allows multiplexing multiple data + streams into a single hardware serial port. + +config SERIAL_TEGRA_TCU_CONSOLE + bool "Support for console on a Tegra TCU serial port" + depends on SERIAL_TEGRA_TCU=y + select SERIAL_CORE_CONSOLE + default y + ---help--- + If you say Y here, it will be possible to use a the Tegra TCU as the + system console (the system console is the device which receives all + kernel messages and warnings and which allows logins in single user + mode). + + If unsure, say Y. + config SERIAL_MAX3100 tristate "MAX3100 support" depends on SPI diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile index daac675612df..4ad82231ff8a 100644 --- a/drivers/tty/serial/Makefile +++ b/drivers/tty/serial/Makefile @@ -76,6 +76,7 @@ obj-$(CONFIG_SERIAL_LANTIQ) += lantiq.o obj-$(CONFIG_SERIAL_XILINX_PS_UART) += xilinx_uartps.o obj-$(CONFIG_SERIAL_SIRFSOC) += sirfsoc_uart.o obj-$(CONFIG_SERIAL_TEGRA) += serial-tegra.o +obj-$(CONFIG_SERIAL_TEGRA_TCU) += tegra-tcu.o obj-$(CONFIG_SERIAL_AR933X) += ar933x_uart.o obj-$(CONFIG_SERIAL_EFM32_UART) += efm32-uart.o obj-$(CONFIG_SERIAL_ARC) += arc_uart.o diff --git a/drivers/tty/serial/tegra-tcu.c b/drivers/tty/serial/tegra-tcu.c new file mode 100644 index 000000000000..1d360cd03b18 --- /dev/null +++ b/drivers/tty/serial/tegra-tcu.c @@ -0,0 +1,299 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define TCU_MBOX_BYTE(i, x) ((x) << (i * 8)) +#define TCU_MBOX_BYTE_V(x, i) (((x) >> (i * 8)) & 0xff) +#define TCU_MBOX_NUM_BYTES(x) ((x) << 24) +#define TCU_MBOX_NUM_BYTES_V(x) (((x) >> 24) & 0x3) + +struct tegra_tcu { + struct uart_driver driver; +#if IS_ENABLED(CONFIG_SERIAL_TEGRA_TCU_CONSOLE) + struct console console; +#endif + struct uart_port port; + + struct mbox_client tx_client, rx_client; + struct mbox_chan *tx, *rx; +}; + +static unsigned int tegra_tcu_uart_tx_empty(struct uart_port *port) +{ + return TIOCSER_TEMT; +} + +static void tegra_tcu_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) +{ +} + +static unsigned int tegra_tcu_uart_get_mctrl(struct uart_port *port) +{ + return 0; +} + +static void tegra_tcu_uart_stop_tx(struct uart_port *port) +{ +} + +static void tegra_tcu_write_one(struct tegra_tcu *tcu, u32 value, + unsigned int count) +{ + void *msg; + + value |= TCU_MBOX_NUM_BYTES(count); + msg = (void *)(unsigned long)value; + mbox_send_message(tcu->tx, msg); +} + +static void tegra_tcu_write(struct tegra_tcu *tcu, const char *s, + unsigned int count) +{ + unsigned int written = 0, i = 0; + bool insert_nl = false; + u32 value = 0; + + while (i < count) { + if (insert_nl) { + value |= TCU_MBOX_BYTE(written++, '\n'); + insert_nl = false; + i++; + } else if (s[i] == '\n') { + value |= TCU_MBOX_BYTE(written++, '\r'); + insert_nl = true; + } else { + value |= TCU_MBOX_BYTE(written++, s[i++]); + } + + if (written == 3) { + tegra_tcu_write_one(tcu, value, 3); + value = written = 0; + } + } + + if (written) + tegra_tcu_write_one(tcu, value, written); +} + +static void tegra_tcu_uart_start_tx(struct uart_port *port) +{ + struct tegra_tcu *tcu = port->private_data; + struct circ_buf *xmit = &port->state->xmit; + unsigned long count; + + for (;;) { + count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); + if (!count) + break; + + tegra_tcu_write(tcu, &xmit->buf[xmit->tail], count); + xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); + } + + uart_write_wakeup(port); +} + +static void tegra_tcu_uart_stop_rx(struct uart_port *port) +{ +} + +static void tegra_tcu_uart_break_ctl(struct uart_port *port, int ctl) +{ +} + +static int tegra_tcu_uart_startup(struct uart_port *port) +{ + return 0; +} + +static void tegra_tcu_uart_shutdown(struct uart_port *port) +{ +} + +static void tegra_tcu_uart_set_termios(struct uart_port *port, + struct ktermios *new, + struct ktermios *old) +{ +} + +static const struct uart_ops tegra_tcu_uart_ops = { + .tx_empty = tegra_tcu_uart_tx_empty, + .set_mctrl = tegra_tcu_uart_set_mctrl, + .get_mctrl = tegra_tcu_uart_get_mctrl, + .stop_tx = tegra_tcu_uart_stop_tx, + .start_tx = tegra_tcu_uart_start_tx, + .stop_rx = tegra_tcu_uart_stop_rx, + .break_ctl = tegra_tcu_uart_break_ctl, + .startup = tegra_tcu_uart_startup, + .shutdown = tegra_tcu_uart_shutdown, + .set_termios = tegra_tcu_uart_set_termios, +}; + +#if IS_ENABLED(CONFIG_SERIAL_TEGRA_TCU_CONSOLE) +static void tegra_tcu_console_write(struct console *cons, const char *s, + unsigned int count) +{ + struct tegra_tcu *tcu = container_of(cons, struct tegra_tcu, console); + + tegra_tcu_write(tcu, s, count); +} + +static int tegra_tcu_console_setup(struct console *cons, char *options) +{ + return 0; +} +#endif + +static void tegra_tcu_receive(struct mbox_client *cl, void *msg) +{ + struct tegra_tcu *tcu = container_of(cl, struct tegra_tcu, rx_client); + struct tty_port *port = &tcu->port.state->port; + u32 value = (u32)(unsigned long)msg; + unsigned int num_bytes, i; + + num_bytes = TCU_MBOX_NUM_BYTES_V(value); + + for (i = 0; i < num_bytes; i++) + tty_insert_flip_char(port, TCU_MBOX_BYTE_V(value, i), + TTY_NORMAL); + + tty_flip_buffer_push(port); +} + +static int tegra_tcu_probe(struct platform_device *pdev) +{ + struct uart_port *port; + struct tegra_tcu *tcu; + int err; + + tcu = devm_kzalloc(&pdev->dev, sizeof(*tcu), GFP_KERNEL); + if (!tcu) + return -ENOMEM; + + tcu->tx_client.dev = &pdev->dev; + tcu->tx_client.tx_block = true; + tcu->tx_client.tx_tout = 10000; + tcu->rx_client.dev = &pdev->dev; + tcu->rx_client.rx_callback = tegra_tcu_receive; + + tcu->tx = mbox_request_channel_byname(&tcu->tx_client, "tx"); + if (IS_ERR(tcu->tx)) { + err = PTR_ERR(tcu->tx); + dev_err(&pdev->dev, "failed to get tx mailbox: %d\n", err); + return err; + } + + tcu->rx = mbox_request_channel_byname(&tcu->rx_client, "rx"); + if (IS_ERR(tcu->rx)) { + err = PTR_ERR(tcu->rx); + dev_err(&pdev->dev, "failed to get rx mailbox: %d\n", err); + goto free_tx; + } + +#if IS_ENABLED(CONFIG_SERIAL_TEGRA_TCU_CONSOLE) + /* setup the console */ + strcpy(tcu->console.name, "ttyTCU"); + tcu->console.device = uart_console_device; + tcu->console.flags = CON_PRINTBUFFER | CON_ANYTIME; + tcu->console.index = -1; + tcu->console.write = tegra_tcu_console_write; + tcu->console.setup = tegra_tcu_console_setup; + tcu->console.data = &tcu->driver; +#endif + + /* setup the driver */ + tcu->driver.owner = THIS_MODULE; + tcu->driver.driver_name = "tegra-tcu"; + tcu->driver.dev_name = "ttyTCU"; +#if IS_ENABLED(CONFIG_SERIAL_TEGRA_TCU_CONSOLE) + tcu->driver.cons = &tcu->console; +#endif + tcu->driver.nr = 1; + + err = uart_register_driver(&tcu->driver); + if (err) { + dev_err(&pdev->dev, "failed to register UART driver: %d\n", + err); + goto free_rx; + } + + /* setup the port */ + port = &tcu->port; + spin_lock_init(&port->lock); + port->dev = &pdev->dev; + port->type = PORT_TEGRA_TCU; + port->ops = &tegra_tcu_uart_ops; + port->fifosize = 1; + port->iotype = UPIO_MEM; + port->flags = UPF_BOOT_AUTOCONF; + port->private_data = tcu; + + err = uart_add_one_port(&tcu->driver, port); + if (err) { + dev_err(&pdev->dev, "failed to add UART port: %d\n", err); + goto unregister_uart; + } + + platform_set_drvdata(pdev, tcu); +#if IS_ENABLED(CONFIG_SERIAL_TEGRA_TCU_CONSOLE) + register_console(&tcu->console); +#endif + + return 0; + +unregister_uart: + uart_unregister_driver(&tcu->driver); +free_rx: + mbox_free_channel(tcu->rx); +free_tx: + mbox_free_channel(tcu->tx); + + return err; +} + +static int tegra_tcu_remove(struct platform_device *pdev) +{ + struct tegra_tcu *tcu = platform_get_drvdata(pdev); + +#if IS_ENABLED(CONFIG_SERIAL_TEGRA_TCU_CONSOLE) + unregister_console(&tcu->console); +#endif + uart_remove_one_port(&tcu->driver, &tcu->port); + uart_unregister_driver(&tcu->driver); + mbox_free_channel(tcu->rx); + mbox_free_channel(tcu->tx); + + return 0; +} + +static const struct of_device_id tegra_tcu_match[] = { + { .compatible = "nvidia,tegra194-tcu" }, + { } +}; + +static struct platform_driver tegra_tcu_driver = { + .driver = { + .name = "tegra-tcu", + .of_match_table = tegra_tcu_match, + }, + .probe = tegra_tcu_probe, + .remove = tegra_tcu_remove, +}; +module_platform_driver(tegra_tcu_driver); + +MODULE_AUTHOR("Mikko Perttunen "); +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("NVIDIA Tegra Combined UART driver"); diff --git a/include/uapi/linux/serial_core.h b/include/uapi/linux/serial_core.h index dce5f9dae121..69883c32cb98 100644 --- a/include/uapi/linux/serial_core.h +++ b/include/uapi/linux/serial_core.h @@ -79,6 +79,9 @@ /* Nuvoton UART */ #define PORT_NPCM 40 +/* NVIDIA Tegra Combined UART */ +#define PORT_TEGRA_TCU 41 + /* Intel EG20 */ #define PORT_PCH_8LINE 44 #define PORT_PCH_2LINE 45 From patchwork Mon Nov 12 15:18:51 2018 Content-Type: text/plain; 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[217.229.17.248]) by smtp.gmail.com with ESMTPSA id h28-v6sm4323021ede.49.2018.11.12.07.19.07 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 12 Nov 2018 07:19:07 -0800 (PST) From: Thierry Reding To: Thierry Reding , Jassi Brar , Greg Kroah-Hartman Cc: Jiri Slaby , Mikko Perttunen , Jon Hunter , Timo Alho , Pekka Pessi , Mika Liljeberg , linux-tegra@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 08/10] arm64: tegra: Add nodes for TCU on Tegra194 Date: Mon, 12 Nov 2018 16:18:51 +0100 Message-Id: <20181112151853.29289-9-thierry.reding@gmail.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181112151853.29289-1-thierry.reding@gmail.com> References: <20181112151853.29289-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Mikko Perttunen Add nodes required for communication through the Tegra Combined UART. This includes the AON HSP instance, addition of shared interrupts for the TOP0 HSP instance, and finally the TCU node itself. Also mark the HSP instances as compatible to tegra194-hsp, as the hardware is not identical but is compatible to tegra186-hsp. Signed-off-by: Mikko Perttunen Acked-by: Jon Hunter Signed-off-by: Thierry Reding --- Changes in v2: - encode direction of mailboxes in device tree mailbox specifier arch/arm64/boot/dts/nvidia/tegra194.dtsi | 38 ++++++++++++++++++++++-- 1 file changed, 35 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index c2091bb16546..4451532a2b4c 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -340,10 +340,35 @@ }; hsp_top0: hsp@3c00000 { - compatible = "nvidia,tegra186-hsp"; + compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; reg = <0x03c00000 0xa0000>; - interrupts = ; - interrupt-names = "doorbell"; + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "doorbell", "shared0", "shared1", "shared2", + "shared3", "shared4", "shared5", "shared6", + "shared7"; + #mbox-cells = <2>; + }; + + hsp_aon: hsp@c150000 { + compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; + reg = <0x0c150000 0xa0000>; + interrupts = , + , + , + ; + /* + * Shared interrupt 0 is routed only to AON/SPE, so + * we only have 4 shared interrupts for the CCPLEX. + */ + interrupt-names = "shared1", "shared2", "shared3", "shared4"; #mbox-cells = <2>; }; @@ -531,6 +556,13 @@ method = "smc"; }; + tcu: tcu { + compatible = "nvidia,tegra194-tcu"; + mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, + <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; + mbox-names = "rx", "tx"; + }; + timer { compatible = "arm,armv8-timer"; interrupts = X-Patchwork-Id: 996496 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="fmSZ+llA"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42tvYZ4xWwz9s47 for ; Tue, 13 Nov 2018 02:19:14 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729937AbeKMBMw (ORCPT ); Mon, 12 Nov 2018 20:12:52 -0500 Received: from mail-ed1-f67.google.com ([209.85.208.67]:41142 "EHLO mail-ed1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729945AbeKMBMw (ORCPT ); Mon, 12 Nov 2018 20:12:52 -0500 Received: by mail-ed1-f67.google.com with SMTP id c25-v6so7678743edt.8; Mon, 12 Nov 2018 07:19:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QGIL//nMYgHHZ4GYaDWliMktQ6b/Y8DmGZjHhB9Vabs=; b=fmSZ+llAl6w5aziLvy1SbJHIYxoCMbPte2FzvxiKhhghiJb7hTOZzGaGNQww9C9jO8 tZ7kdMu4Gx7zkLGywBhajLHnYUPyZBWtTSF/WGDJ+HXMDym+k7tAvvY7bakeQLwQ/iuS Dl5t0cNj67yl2H7g/+UHlVqyJ96q8w/i+s1574BRN98gG8n+5Mw+5Ij8JJ448xtcaEtO AUOj3glaJJrSLFg5Rdf3UCTjCwgz5Iptk4FKtCcfCw5XDNOK8ltpkAgdA09/jGnKaDkQ QKp7Z8CVJiBnkN6YJ1Hffkvn76+v5s/02vtwTlpVLB3gk66dVrPLkBpBdiBUfNnsGGVX hs3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QGIL//nMYgHHZ4GYaDWliMktQ6b/Y8DmGZjHhB9Vabs=; b=S1EDxwWRCxYu3dhJweX4uNR4a5aA76X4njYUuDud6RGF+OX3tvz28bN04Gk9dj+xNL zx3tS6XGWNyffX1zw+ytKhpRemXiXmIRC7oJYvBzdl7VxewrD2gmbTNmKvW2HOmdRkki 97Ux5BIxwH3VG6HqonIM1Z/goa4vhlCasmF+9xd5TRjMxhitPpx86HkP5EGzeDCI3jzB qrys2esDJYcy4GFy+qibGJlOv1g6LQnJqacAe1ePj/G++EYR9oElWk7QDbmuRqK9soBr KYGvyo5yiChp8iSHJKeH1TF3Kxm1NDG2tOtVYFdMS/9lNxwl771nKnUH4/1B35TKgIwr 4J9w== X-Gm-Message-State: AGRZ1gJcR2ScwbWw6otlQSb7QTFP4azjl4qwJXfX8yzhJVnPdhPLVS3W cPfD7olJmNDL7+Nf42gJotU= X-Google-Smtp-Source: AJdET5c4w1XbEsHM5lqmIMnSHsXtK+Rmcc8NX/OZuc3B0anWHDWJmaaCNxjnujMmlVpLl+PHs8caYg== X-Received: by 2002:a50:87d9:: with SMTP id 25mr1969882edz.280.1542035949987; Mon, 12 Nov 2018 07:19:09 -0800 (PST) Received: from localhost (pD9E511F8.dip0.t-ipconnect.de. [217.229.17.248]) by smtp.gmail.com with ESMTPSA id dc5-v6sm2369072ejb.53.2018.11.12.07.19.09 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 12 Nov 2018 07:19:09 -0800 (PST) From: Thierry Reding To: Thierry Reding , Jassi Brar , Greg Kroah-Hartman Cc: Jiri Slaby , Mikko Perttunen , Jon Hunter , Timo Alho , Pekka Pessi , Mika Liljeberg , linux-tegra@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 09/10] arm64: tegra: Mark TCU as primary serial port on Tegra194 P2888 Date: Mon, 12 Nov 2018 16:18:52 +0100 Message-Id: <20181112151853.29289-10-thierry.reding@gmail.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181112151853.29289-1-thierry.reding@gmail.com> References: <20181112151853.29289-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Mikko Perttunen The Tegra Combined UART is the proper primary serial port on P2888, so use it. Signed-off-by: Mikko Perttunen Acked-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi index 57d3f00464ce..fcbe2a88f8db 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi @@ -10,7 +10,7 @@ aliases { sdhci0 = "/cbb/sdhci@3460000"; sdhci1 = "/cbb/sdhci@3400000"; - serial0 = &uartb; + serial0 = &tcu; i2c0 = "/bpmp/i2c"; i2c1 = "/cbb/i2c@3160000"; i2c2 = "/cbb/i2c@c240000"; From patchwork Mon Nov 12 15:18:53 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 996497 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="pz/5Nd9R"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42tvYd08Dnz9s1x for ; Tue, 13 Nov 2018 02:19:17 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729979AbeKMBMy (ORCPT ); Mon, 12 Nov 2018 20:12:54 -0500 Received: from mail-ed1-f66.google.com ([209.85.208.66]:33236 "EHLO mail-ed1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728064AbeKMBMx (ORCPT ); Mon, 12 Nov 2018 20:12:53 -0500 Received: by mail-ed1-f66.google.com with SMTP id r27so4720312eda.0; Mon, 12 Nov 2018 07:19:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NzZSE4BcB43mE4VU7H9S6FeooiJOUOh2MBRVHGfg4Yg=; b=pz/5Nd9RDshfwrM+7JPFstLBYszhNpQnDMOplPSWA1fDcF8pUlDkta1q3aM5+tum5U JfB/+p/4vvC9JGF+63YjGnmj1/M/Wet+fgw7dSNyqC79zHaVdziGJmax8/+H0zyzu/Br D9smnaisATx4ebwkybFowfO3bP5KV8DMeN9X0LrSgsuKCauKYHqAHpGFdOBADHY21Ujf hmXjPdZWVInUHLq9QeihhplkTEUaMx+KFo4SawlleZKGiVtfLVjJD8oL3ZqCDlxXjAIp I+2Zx3FEbvCXQqmpJCk0hsqoWfHPFQqeak8YXElS0SB8mj2n6btkw6dvqJ+7HCaukkFh uB9A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NzZSE4BcB43mE4VU7H9S6FeooiJOUOh2MBRVHGfg4Yg=; b=H3PR9W/tI6tyvK0GrRChdRzKTrg/LsftMeN2wG916g8ztzA7JVseYq85sN96+U9A/s 1P98joLtpG2eJIn/8ur/W81x4bauhOWrkIYl6KKnwtfhX9RQewzwGOJ6y5DjeVAiXvHc LzqL1YXe/rCL1IhmcuePB/rA72ZHI59fnnAtin6NyDUEVo9awQlkPCUPI72ftMaJL6Kp 9Pfc+/NnpLnvqXdFkRS571C66m5SIhviiZwSZLsWU4ng3GqtmYgLbRjg1Gbz5apR+6Ea 0zSL065R9oL/UmDV3ReBdEL8ZLLkneWwWdgjkglBt+YmGX2VbKigwvX9fHOmYjBjpl3V ncUg== X-Gm-Message-State: AGRZ1gLAL9PIz78nMkpawya7krVowjvnHvoMrfCVGDlH/8D9YcDJJI0l p2bAPOR8VLj1PRFn7sfQQzQ= X-Google-Smtp-Source: AJdET5cM5LFavbgjgLdz1XW3hfLyxJrxY3Vjn/4+0pLieYUbS0Sw1qCLnBY+7WWPFMU1Ny8jJK+UZg== X-Received: by 2002:aa7:c398:: with SMTP id k24-v6mr13035868edq.170.1542035951530; Mon, 12 Nov 2018 07:19:11 -0800 (PST) Received: from localhost (pD9E511F8.dip0.t-ipconnect.de. [217.229.17.248]) by smtp.gmail.com with ESMTPSA id l51sm1830738edb.36.2018.11.12.07.19.10 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 12 Nov 2018 07:19:10 -0800 (PST) From: Thierry Reding To: Thierry Reding , Jassi Brar , Greg Kroah-Hartman Cc: Jiri Slaby , Mikko Perttunen , Jon Hunter , Timo Alho , Pekka Pessi , Mika Liljeberg , linux-tegra@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 10/10] arm64: defconfig: Enable Tegra TCU Date: Mon, 12 Nov 2018 16:18:53 +0100 Message-Id: <20181112151853.29289-11-thierry.reding@gmail.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181112151853.29289-1-thierry.reding@gmail.com> References: <20181112151853.29289-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The Tegra Combined UART is used on some Tegra194 devices as a way of multiplexing output from multiple producers onto a single physical UART. Enable this by default so that it can be used as the default console to write kernel messages to. Signed-off-by: Thierry Reding --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index c0a5275210c7..fdb9d60905ac 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -300,6 +300,7 @@ CONFIG_SERIAL_MESON_CONSOLE=y CONFIG_SERIAL_SAMSUNG=y CONFIG_SERIAL_SAMSUNG_CONSOLE=y CONFIG_SERIAL_TEGRA=y +CONFIG_SERIAL_TEGRA_TCU=y CONFIG_SERIAL_SH_SCI=y CONFIG_SERIAL_MSM=y CONFIG_SERIAL_MSM_CONSOLE=y