From patchwork Tue Oct 9 18:51:22 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 981487 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=wdc.com header.i=@wdc.com header.b="UEIzF27P"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42V5tS4zphz9sBk for ; Wed, 10 Oct 2018 05:51:44 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727164AbeJJCJu (ORCPT ); Tue, 9 Oct 2018 22:09:50 -0400 Received: from esa6.hgst.iphmx.com ([216.71.154.45]:53214 "EHLO esa6.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726460AbeJJCJs (ORCPT ); Tue, 9 Oct 2018 22:09:48 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1539111087; x=1570647087; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=3buQbls5/gIS7422ozrHmZ63B7g/jc69OByotZi7u7I=; b=UEIzF27PKT4lMQ7oWm3gm+dRjYC12BVFvEZsGj7oALm3jKmfT7K9HrfC X2mMn4hKlKtjxhOLzQ+lYi5elUzfFSG/ItzYdbJ39Huo0t66pNV19pTsJ KZKVhcX6arWf/oy1Ie2T4T7NyCLvLmefs4jzQ/AyPgPfLd47phXwwrzge Tqoe1FIaVZzI2g6gP5s17eqCv/HStxVqV87xgnRYNHqoppsXFn2JryfHw fPqATc8nfgBjBkMu2tt7ki5Y+SSICgYWKYPzrRBaUsx5YoVo/huI2GtSi 6bjI+CjoeM9OvTeLlZyGJ3yAN1Nh8V6tvYyWoGIIad8A4JwcVT+3MhRId w==; X-IronPort-AV: E=Sophos;i="5.54,361,1534780800"; d="scan'208";a="93263449" Received: from uls-op-cesaip02.wdc.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 10 Oct 2018 02:51:26 +0800 Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep02.wdc.com with ESMTP; 09 Oct 2018 11:36:35 -0700 Received: from jedi-01.sdcorp.global.sandisk.com (HELO jedi-01.int.fusionio.com) ([10.11.143.218]) by uls-op-cesaip02.wdc.com with ESMTP; 09 Oct 2018 11:51:26 -0700 From: Atish Patra To: palmer@sifive.com, linux-riscv@lists.infradead.org, linux-pwm@vger.kernel.org, linux-gpio@vger.kernel.org Cc: linus.walleij@linaro.org, robh+dt@kernel.org, thierry.reding@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, mark.rutland@arm.com, hch@infradead.org, atish.patra@wdc.com Subject: [RFC 1/4] pwm: sifive: Add DT documentation for SiFive PWM Controller. Date: Tue, 9 Oct 2018 11:51:22 -0700 Message-Id: <1539111085-25502-2-git-send-email-atish.patra@wdc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1539111085-25502-1-git-send-email-atish.patra@wdc.com> References: <1539111085-25502-1-git-send-email-atish.patra@wdc.com> Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org From: "Wesley W. Terpstra" DT documentation for PWM controller added with updated compatible string. Signed-off-by: Wesley W. Terpstra [Atish: Compatible string update] Signed-off-by: Atish Patra --- .../devicetree/bindings/pwm/pwm-sifive.txt | 32 ++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/pwm-sifive.txt diff --git a/Documentation/devicetree/bindings/pwm/pwm-sifive.txt b/Documentation/devicetree/bindings/pwm/pwm-sifive.txt new file mode 100644 index 00000000..532b10fc --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/pwm-sifive.txt @@ -0,0 +1,32 @@ +SiFive PWM controller + +Unlike most other PWM controllers, the SiFive PWM controller currently only +supports one period for all channels in the PWM. This is set globally in DTS. +The period also has significant restrictions on the values it can achieve, +which the driver rounds to the nearest achievable frequency. + +Required properties: +- compatible: should be one of + "sifive,fu540-c000-pwm0","sifive,pwm0". + PWM controller is HiFive Unleashed specific chip which warrants a + specific compatible string. The second string is kept for backward + compatibility until a firmware update with latest compatible string. +- reg: physical base address and length of the controller's registers +- clocks: The frequency the controller runs at +- #pwm-cells: Should be 2. + The first cell is the PWM channel number + The second cell is the PWM polarity +- sifive,approx-period: the driver will get as close to this period as it can +- interrupts: one interrupt per PWM channel (currently unused in the driver) + +Examples: + +pwm: pwm@10020000 { + compatible = "sifive,fu540-c000-pwm0","sifive,pwm0"; + reg = <0x0 0x10020000 0x0 0x1000>; + clocks = <&tlclk>; + interrupt-parent = <&plic>; + interrupts = <42 43 44 45>; + #pwm-cells = <2>; + sifive,approx-period = <1000000>; +}; From patchwork Tue Oct 9 18:51:23 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 981484 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=wdc.com header.i=@wdc.com header.b="j8zWq7Zu"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42V5tN4G43z9sBk for ; Wed, 10 Oct 2018 05:51:40 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727291AbeJJCJu (ORCPT ); Tue, 9 Oct 2018 22:09:50 -0400 Received: from esa6.hgst.iphmx.com ([216.71.154.45]:53214 "EHLO esa6.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726836AbeJJCJu (ORCPT ); Tue, 9 Oct 2018 22:09:50 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1539111088; x=1570647088; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=jYSy18F/N8laeC0OVGMn3FOciObDX877wWPhX25tco8=; b=j8zWq7Zu4eZMvO+FmV0lyRhGsasP8N1SxgtpJrcCBTL3kI3yVU5OcJjm KOA5HFvENxAlNppb9pXLIZ+2GPNgStasm3iglETPrieMDEGO/yjXY2v4k 6OecdBCJuFwUfi6RHkj4Ze4dTwVfY9YiiYBMIsyEb1WoWXJ0vJ/1eXtlb rxptvel9HK+sUIe1Xz/vPNXyEgF9n3/HWNQaXWlk7B5YnZQ1C0u4YA9fD V//6b+YMJsIdBtSzaeFs6pF/VXdxefp1atjYMYEUeCjlbm5u+ELrpbIWg +MMDNQnC0a5CnDIoal1kBk30AzPr4Mp98SyPC686fhexXAomiieElPOQF Q==; X-IronPort-AV: E=Sophos;i="5.54,361,1534780800"; d="scan'208";a="93263452" Received: from uls-op-cesaip02.wdc.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 10 Oct 2018 02:51:26 +0800 Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep02.wdc.com with ESMTP; 09 Oct 2018 11:36:36 -0700 Received: from jedi-01.sdcorp.global.sandisk.com (HELO jedi-01.int.fusionio.com) ([10.11.143.218]) by uls-op-cesaip02.wdc.com with ESMTP; 09 Oct 2018 11:51:26 -0700 From: Atish Patra To: palmer@sifive.com, linux-riscv@lists.infradead.org, linux-pwm@vger.kernel.org, linux-gpio@vger.kernel.org Cc: linus.walleij@linaro.org, robh+dt@kernel.org, thierry.reding@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, mark.rutland@arm.com, hch@infradead.org, atish.patra@wdc.com Subject: [RFC 2/4] pwm: sifive: Add a driver for SiFive SoC PWM Date: Tue, 9 Oct 2018 11:51:23 -0700 Message-Id: <1539111085-25502-3-git-send-email-atish.patra@wdc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1539111085-25502-1-git-send-email-atish.patra@wdc.com> References: <1539111085-25502-1-git-send-email-atish.patra@wdc.com> Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org From: "Wesley W. Terpstra" Adds a PWM driver for PWM chip present in SiFive's HiFive Unleashed SoC. Signed-off-by: Wesley W. Terpstra [Atish: Various fixes and code cleanup] Signed-off-by: Atish Patra --- drivers/pwm/Kconfig | 10 ++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-sifive.c | 240 +++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 251 insertions(+) create mode 100644 drivers/pwm/pwm-sifive.c diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 504d2527..dd12144d 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -378,6 +378,16 @@ config PWM_SAMSUNG To compile this driver as a module, choose M here: the module will be called pwm-samsung. +config PWM_SIFIVE + tristate "SiFive PWM support" + depends on OF + depends on COMMON_CLK + help + Generic PWM framework driver for SiFive SoCs. + + To compile this driver as a module, choose M here: the module + will be called pwm-sifive. + config PWM_SPEAR tristate "STMicroelectronics SPEAr PWM support" depends on PLAT_SPEAR diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 9c676a0d..30089ca6 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -37,6 +37,7 @@ obj-$(CONFIG_PWM_RCAR) += pwm-rcar.o obj-$(CONFIG_PWM_RENESAS_TPU) += pwm-renesas-tpu.o obj-$(CONFIG_PWM_ROCKCHIP) += pwm-rockchip.o obj-$(CONFIG_PWM_SAMSUNG) += pwm-samsung.o +obj-$(CONFIG_PWM_SIFIVE) += pwm-sifive.o obj-$(CONFIG_PWM_SPEAR) += pwm-spear.o obj-$(CONFIG_PWM_STI) += pwm-sti.o obj-$(CONFIG_PWM_STM32) += pwm-stm32.o diff --git a/drivers/pwm/pwm-sifive.c b/drivers/pwm/pwm-sifive.c new file mode 100644 index 00000000..99580025 --- /dev/null +++ b/drivers/pwm/pwm-sifive.c @@ -0,0 +1,240 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2017 SiFive + */ +#include +#include +#include +#include +#include +#include +#include + +#define MAX_PWM 4 + +/* Register offsets */ +#define REG_PWMCFG 0x0 +#define REG_PWMCOUNT 0x8 +#define REG_PWMS 0x10 +#define REG_PWMCMP0 0x20 + +/* PWMCFG fields */ +#define BIT_PWM_SCALE 0 +#define BIT_PWM_STICKY 8 +#define BIT_PWM_ZERO_ZMP 9 +#define BIT_PWM_DEGLITCH 10 +#define BIT_PWM_EN_ALWAYS 12 +#define BIT_PWM_EN_ONCE 13 +#define BIT_PWM0_CENTER 16 +#define BIT_PWM0_GANG 24 +#define BIT_PWM0_IP 28 + +#define SIZE_PWMCMP 4 +#define MASK_PWM_SCALE 0xf + +struct sifive_pwm_device { + struct pwm_chip chip; + struct notifier_block notifier; + struct clk *clk; + void __iomem *regs; + unsigned int approx_period; + unsigned int real_period; +}; + +static inline struct sifive_pwm_device *to_sifive_pwm_chip(struct pwm_chip *c) +{ + return container_of(c, struct sifive_pwm_device, chip); +} + +static int sifive_pwm_apply(struct pwm_chip *chip, struct pwm_device *dev, + struct pwm_state *state) +{ + struct sifive_pwm_device *pwm = to_sifive_pwm_chip(chip); + unsigned int duty_cycle; + u32 frac; + + duty_cycle = state->duty_cycle; + if (!state->enabled) + duty_cycle = 0; + if (state->polarity == PWM_POLARITY_NORMAL) + duty_cycle = state->period - duty_cycle; + + frac = ((u64)duty_cycle << 16) / state->period; + frac = min(frac, 0xFFFFU); + + iowrite32(frac, pwm->regs + REG_PWMCMP0 + (dev->hwpwm * SIZE_PWMCMP)); + + if (state->enabled) { + state->period = pwm->real_period; + state->duty_cycle = ((u64)frac * pwm->real_period) >> 16; + if (state->polarity == PWM_POLARITY_NORMAL) + state->duty_cycle = state->period - state->duty_cycle; + } + + return 0; +} + +static void sifive_pwm_get_state(struct pwm_chip *chip, struct pwm_device *dev, + struct pwm_state *state) +{ + struct sifive_pwm_device *pwm = to_sifive_pwm_chip(chip); + unsigned long duty; + + duty = ioread32(pwm->regs + REG_PWMCMP0 + (dev->hwpwm * SIZE_PWMCMP)); + + state->period = pwm->real_period; + state->duty_cycle = ((u64)duty * pwm->real_period) >> 16; + state->polarity = PWM_POLARITY_INVERSED; + state->enabled = duty > 0; +} + +static const struct pwm_ops sifive_pwm_ops = { + .get_state = sifive_pwm_get_state, + .apply = sifive_pwm_apply, + .owner = THIS_MODULE, +}; + +static struct pwm_device *sifive_pwm_xlate(struct pwm_chip *chip, + const struct of_phandle_args *args) +{ + struct sifive_pwm_device *pwm = to_sifive_pwm_chip(chip); + struct pwm_device *dev; + + if (args->args[0] >= chip->npwm) + return ERR_PTR(-EINVAL); + + dev = pwm_request_from_chip(chip, args->args[0], NULL); + if (IS_ERR(dev)) + return dev; + + /* The period cannot be changed on a per-PWM basis */ + dev->args.period = pwm->real_period; + dev->args.polarity = PWM_POLARITY_NORMAL; + if (args->args[1] & PWM_POLARITY_INVERTED) + dev->args.polarity = PWM_POLARITY_INVERSED; + + return dev; +} + +static void sifive_pwm_update_clock(struct sifive_pwm_device *pwm, + unsigned long rate) +{ + /* (1 << (16+scale)) * 10^9/rate = real_period */ + unsigned long scalePow = (pwm->approx_period * (u64)rate) / 1000000000; + int scale = ilog2(scalePow) - 16; + + scale = clamp(scale, 0, 0xf); + iowrite32((1 << BIT_PWM_EN_ALWAYS) | (scale << BIT_PWM_SCALE), + pwm->regs + REG_PWMCFG); + + pwm->real_period = (1000000000ULL << (16 + scale)) / rate; +} + +static int sifive_pwm_clock_notifier(struct notifier_block *nb, + unsigned long event, void *data) +{ + struct clk_notifier_data *ndata = data; + struct sifive_pwm_device *pwm = container_of(nb, + struct sifive_pwm_device, + notifier); + + if (event == POST_RATE_CHANGE) + sifive_pwm_update_clock(pwm, ndata->new_rate); + + return NOTIFY_OK; +} + +static int sifive_pwm_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *node = pdev->dev.of_node; + struct sifive_pwm_device *pwm; + struct pwm_chip *chip; + struct resource *res; + int ret; + + pwm = devm_kzalloc(dev, sizeof(*pwm), GFP_KERNEL); + if (!pwm) + return -ENOMEM; + + chip = &pwm->chip; + chip->dev = dev; + chip->ops = &sifive_pwm_ops; + chip->of_xlate = sifive_pwm_xlate; + chip->of_pwm_n_cells = 2; + chip->base = -1; + + ret = of_property_read_u32(node, "sifive,npwm", &chip->npwm); + if (ret < 0 || chip->npwm > MAX_PWM) + chip->npwm = MAX_PWM; + + ret = of_property_read_u32(node, "sifive,approx-period", + &pwm->approx_period); + if (ret < 0) { + dev_err(dev, "Unable to read sifive,approx-period from DTS\n"); + return -ENOENT; + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + pwm->regs = devm_ioremap_resource(dev, res); + if (IS_ERR(pwm->regs)) { + dev_err(dev, "Unable to map IO resources\n"); + return PTR_ERR(pwm->regs); + } + + pwm->clk = devm_clk_get(dev, NULL); + if (IS_ERR(pwm->clk)) { + dev_err(dev, "Unable to find controller clock\n"); + return PTR_ERR(pwm->clk); + } + + /* Watch for changes to underlying clock frequency */ + pwm->notifier.notifier_call = sifive_pwm_clock_notifier; + clk_notifier_register(pwm->clk, &pwm->notifier); + + /* Initialize PWM config */ + sifive_pwm_update_clock(pwm, clk_get_rate(pwm->clk)); + + /* No interrupt handler needed yet */ + + ret = pwmchip_add(chip); + if (ret < 0) { + dev_err(dev, "cannot register PWM: %d\n", ret); + clk_notifier_unregister(pwm->clk, &pwm->notifier); + return ret; + } + + platform_set_drvdata(pdev, pwm); + dev_info(dev, "SiFive PWM chip registered %d PWMs\n", chip->npwm); + + return 0; +} + +static int sifive_pwm_remove(struct platform_device *dev) +{ + struct sifive_pwm_device *pwm = platform_get_drvdata(dev); + struct pwm_chip *chip = &pwm->chip; + + clk_notifier_unregister(pwm->clk, &pwm->notifier); + return pwmchip_remove(chip); +} + +static const struct of_device_id sifive_pwm_of_match[] = { + { .compatible = "sifive,pwm0" }, + { .compatible = "sifive,fu540-c000-pwm0" }, + {}, +}; +MODULE_DEVICE_TABLE(of, sifive_pwm_of_match); + +static struct platform_driver sifive_pwm_driver = { + .probe = sifive_pwm_probe, + .remove = sifive_pwm_remove, + .driver = { + .name = "pwm-sifivem", + .of_match_table = of_match_ptr(sifive_pwm_of_match), + }, +}; +module_platform_driver(sifive_pwm_driver); + +MODULE_DESCRIPTION("SiFive PWM driver"); +MODULE_LICENSE("GPL v2"); From patchwork Tue Oct 9 18:51:24 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 981481 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=wdc.com header.i=@wdc.com header.b="SxrOQmHx"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42V5tB6CwFz9s89 for ; Wed, 10 Oct 2018 05:51:30 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726910AbeJJCJt (ORCPT ); Tue, 9 Oct 2018 22:09:49 -0400 Received: from esa1.hgst.iphmx.com ([68.232.141.245]:38343 "EHLO esa1.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726795AbeJJCJs (ORCPT ); Tue, 9 Oct 2018 22:09:48 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1539111087; x=1570647087; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=TtsfGcDM3h5ap+H9kxy/xjXfnWIH0/v0qN2/iTEdC0c=; b=SxrOQmHxTv8mFcdkj5o0I8zamextg6M7ML3EtOL6pWEpwqCDPnIDClIS jlS+KumiLqyFAvCp2/obTs1DRSdiN/rvquT96mPOQUy5KUlQXgOckiAjD uSCZEqzCrc+OXGDQEQ6lggTwpa7ZKBxagXj2vpVLhXA+j7N9navtEPWUX gO3aYKvhAHWqZrULKY9HFORs662Fp+F8dFm6IzAhAs9cnIWcIUYwYMfS/ fqZklGlplLUHSn7QVbJ5kor4zGIcU6u2WlUzbKzEBCSPpUFbEgLl8czzF U/YUoAGKT57uYdwAX3Z+5FNfw9w1xrhSu+S1uni7Y5iaKG7bhgCLzxmuu g==; X-IronPort-AV: E=Sophos;i="5.54,361,1534780800"; d="scan'208";a="195909237" Received: from uls-op-cesaip02.wdc.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 10 Oct 2018 02:51:26 +0800 Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep02.wdc.com with ESMTP; 09 Oct 2018 11:36:36 -0700 Received: from jedi-01.sdcorp.global.sandisk.com (HELO jedi-01.int.fusionio.com) ([10.11.143.218]) by uls-op-cesaip02.wdc.com with ESMTP; 09 Oct 2018 11:51:26 -0700 From: Atish Patra To: palmer@sifive.com, linux-riscv@lists.infradead.org, linux-pwm@vger.kernel.org, linux-gpio@vger.kernel.org Cc: linus.walleij@linaro.org, robh+dt@kernel.org, thierry.reding@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, mark.rutland@arm.com, hch@infradead.org, atish.patra@wdc.com Subject: [RFC 3/4] gpio: sifive: Add DT documentation for SiFive GPIO. Date: Tue, 9 Oct 2018 11:51:24 -0700 Message-Id: <1539111085-25502-4-git-send-email-atish.patra@wdc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1539111085-25502-1-git-send-email-atish.patra@wdc.com> References: <1539111085-25502-1-git-send-email-atish.patra@wdc.com> Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org From: "Wesley W. Terpstra" DT documentation for GPIO added with updated compatible string. Signed-off-by: Wesley W. Terpstra [Atish: Compatible string update] Signed-off-by: Atish Patra --- .../devicetree/bindings/gpio/gpio-sifive.txt | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/gpio-sifive.txt diff --git a/Documentation/devicetree/bindings/gpio/gpio-sifive.txt b/Documentation/devicetree/bindings/gpio/gpio-sifive.txt new file mode 100644 index 00000000..781fe4ad --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio-sifive.txt @@ -0,0 +1,28 @@ +SiFive GPIO controller bindings + +Required properties: +- compatible: should be one of + "sifive,fu540-c000-gpio0","sifive,gpio0" +- reg: Physical base address and length of the controller's registers. +- #gpio-cells : Should be 2 + - The first cell is the GPIO offset number. + - The second cell indicates the polarity of the GPIO +- gpio-controller : Marks the device node as a GPIO controller. +- interrupt-controller: Marks the device node as an interrupt controller. +- #interrupt-cells : Should be 2. + - The first cell is the GPIO offset number within the GPIO controller. + - The second cell is the edge/level to use for interrupt generation. +- interrupts: Specify the interrupts, one per GPIO + +Example: + +gpio: gpio@10060000 { + compatible = "sifive,fu540-c000-gpio0","sifive,gpio0"; + interrupt-parent = <&plic>; + interrupts = <7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22>; + reg = <0x0 0x10060000 0x0 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; +}; From patchwork Tue Oct 9 18:51:25 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 981489 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=wdc.com header.i=@wdc.com header.b="Ytsy+q+D"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42V5tX3fLGz9s8r for ; Wed, 10 Oct 2018 05:51:48 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727447AbeJJCKD (ORCPT ); Tue, 9 Oct 2018 22:10:03 -0400 Received: from esa1.hgst.iphmx.com ([68.232.141.245]:38343 "EHLO esa1.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726798AbeJJCJt (ORCPT ); Tue, 9 Oct 2018 22:09:49 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1539111088; x=1570647088; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=ZCsXdpWFIii6ThOSa4DBjpjO+85+A3BePvg+RFDxO1c=; b=Ytsy+q+DhzTKCl+w0BjQBY1H3nPLhZr2QWF8QLfV70MdGC1uUsxmhWVd +1yijK9L+WZCUKfSr89aFDsxfD7EiuGEchs9b8YYlKV2Lq3pPPdVY9hv9 lRGXmCv6hA/a5H5DTvCQ+L2f0s6OjRegDOjNY9QY6jBQDN/Zs8sUZO9tp VE0Yz0avVs91b73vpfJ/4mJ4FSPQK71u+L91kv6in09dgIA5+rKYFoL6s 3Rcy06Zeh+wi9+5m6Hhk3majDKFU/BtvXGoUYOZy5DJfIsfazelZx/Yjv J6SUmeGO/fumu0h5JE7zawgiZSN6v+Vb3IAzFB3bkd1+niRm5UnJ2c7bW A==; X-IronPort-AV: E=Sophos;i="5.54,361,1534780800"; d="scan'208";a="195909238" Received: from uls-op-cesaip02.wdc.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 10 Oct 2018 02:51:26 +0800 Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep02.wdc.com with ESMTP; 09 Oct 2018 11:36:36 -0700 Received: from jedi-01.sdcorp.global.sandisk.com (HELO jedi-01.int.fusionio.com) ([10.11.143.218]) by uls-op-cesaip02.wdc.com with ESMTP; 09 Oct 2018 11:51:27 -0700 From: Atish Patra To: palmer@sifive.com, linux-riscv@lists.infradead.org, linux-pwm@vger.kernel.org, linux-gpio@vger.kernel.org Cc: linus.walleij@linaro.org, robh+dt@kernel.org, thierry.reding@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, mark.rutland@arm.com, hch@infradead.org, atish.patra@wdc.com Subject: [RFC 4/4] gpio: sifive: Add GPIO driver for SiFive SoCs Date: Tue, 9 Oct 2018 11:51:25 -0700 Message-Id: <1539111085-25502-5-git-send-email-atish.patra@wdc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1539111085-25502-1-git-send-email-atish.patra@wdc.com> References: <1539111085-25502-1-git-send-email-atish.patra@wdc.com> Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org From: "Wesley W. Terpstra" Adds the GPIO driver for SiFive RISC-V SoCs. Signed-off-by: Wesley W. Terpstra [Atish: Various fixes and code cleanup] Signed-off-by: Atish Patra --- drivers/gpio/Kconfig | 7 + drivers/gpio/Makefile | 1 + drivers/gpio/gpio-sifive.c | 326 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 334 insertions(+) create mode 100644 drivers/gpio/gpio-sifive.c diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 4f52c3a8..7755f49e 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -439,6 +439,13 @@ config GPIO_REG A 32-bit single register GPIO fixed in/out implementation. This can be used to represent any register as a set of GPIO signals. +config GPIO_SIFIVE + bool "SiFive GPIO support" + depends on OF_GPIO + select GPIOLIB_IRQCHIP + help + Say yes here to support the GPIO device on SiFive SoCs. + config GPIO_SPEAR_SPICS bool "ST SPEAr13xx SPI Chip Select as GPIO support" depends on PLAT_SPEAR diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index c256aff6..244a3696 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -111,6 +111,7 @@ obj-$(CONFIG_GPIO_REG) += gpio-reg.o obj-$(CONFIG_ARCH_SA1100) += gpio-sa1100.o obj-$(CONFIG_GPIO_SCH) += gpio-sch.o obj-$(CONFIG_GPIO_SCH311X) += gpio-sch311x.o +obj-$(CONFIG_GPIO_SIFIVE) += gpio-sifive.o obj-$(CONFIG_GPIO_SODAVILLE) += gpio-sodaville.o obj-$(CONFIG_GPIO_SPEAR_SPICS) += gpio-spear-spics.o obj-$(CONFIG_GPIO_SPRD) += gpio-sprd.o diff --git a/drivers/gpio/gpio-sifive.c b/drivers/gpio/gpio-sifive.c new file mode 100644 index 00000000..5af2b405 --- /dev/null +++ b/drivers/gpio/gpio-sifive.c @@ -0,0 +1,326 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2017 SiFive + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define GPIO_INPUT_VAL 0x00 +#define GPIO_INPUT_EN 0x04 +#define GPIO_OUTPUT_EN 0x08 +#define GPIO_OUTPUT_VAL 0x0C +#define GPIO_RISE_IE 0x18 +#define GPIO_RISE_IP 0x1C +#define GPIO_FALL_IE 0x20 +#define GPIO_FALL_IP 0x24 +#define GPIO_HIGH_IE 0x28 +#define GPIO_HIGH_IP 0x2C +#define GPIO_LOW_IE 0x30 +#define GPIO_LOW_IP 0x34 +#define GPIO_OUTPUT_XOR 0x40 + +#define MAX_GPIO 32 + +struct sifive_gpio { + raw_spinlock_t lock; + void __iomem *base; + struct gpio_chip gc; + unsigned long enabled; + unsigned int trigger[MAX_GPIO]; + unsigned int irq_parent[MAX_GPIO]; + struct sifive_gpio *self_ptr[MAX_GPIO]; +}; + +static void sifive_assign_bit(void __iomem *ptr, unsigned int offset, int value) +{ + /* + * It's frustrating that we are not allowed to use the device atomics + * which are GUARANTEED to be supported by this device on RISC-V + */ + u32 bit = BIT(offset), old = ioread32(ptr); + + if (value) + iowrite32(old | bit, ptr); + else + iowrite32(old & ~bit, ptr); +} + +static int sifive_direction_input(struct gpio_chip *gc, unsigned int offset) +{ + struct sifive_gpio *chip = gpiochip_get_data(gc); + unsigned long flags; + + if (offset >= gc->ngpio) + return -EINVAL; + + raw_spin_lock_irqsave(&chip->lock, flags); + sifive_assign_bit(chip->base + GPIO_OUTPUT_EN, offset, 0); + sifive_assign_bit(chip->base + GPIO_INPUT_EN, offset, 1); + raw_spin_unlock_irqrestore(&chip->lock, flags); + + return 0; +} + +static int sifive_direction_output(struct gpio_chip *gc, unsigned int offset, + int value) +{ + struct sifive_gpio *chip = gpiochip_get_data(gc); + unsigned long flags; + + if (offset >= gc->ngpio) + return -EINVAL; + + raw_spin_lock_irqsave(&chip->lock, flags); + sifive_assign_bit(chip->base + GPIO_INPUT_EN, offset, 0); + sifive_assign_bit(chip->base + GPIO_OUTPUT_VAL, offset, value); + sifive_assign_bit(chip->base + GPIO_OUTPUT_EN, offset, 1); + raw_spin_unlock_irqrestore(&chip->lock, flags); + + return 0; +} + +static int sifive_get_direction(struct gpio_chip *gc, unsigned int offset) +{ + struct sifive_gpio *chip = gpiochip_get_data(gc); + + if (offset >= gc->ngpio) + return -EINVAL; + + return !(ioread32(chip->base + GPIO_OUTPUT_EN) & BIT(offset)); +} + +static int sifive_get_value(struct gpio_chip *gc, unsigned int offset) +{ + struct sifive_gpio *chip = gpiochip_get_data(gc); + + if (offset >= gc->ngpio) + return -EINVAL; + + return !!(ioread32(chip->base + GPIO_INPUT_VAL) & BIT(offset)); +} + +static void sifive_set_value(struct gpio_chip *gc, unsigned int offset, + int value) +{ + struct sifive_gpio *chip = gpiochip_get_data(gc); + unsigned long flags; + + if (offset >= gc->ngpio) + return; + + raw_spin_lock_irqsave(&chip->lock, flags); + sifive_assign_bit(chip->base + GPIO_OUTPUT_VAL, offset, value); + raw_spin_unlock_irqrestore(&chip->lock, flags); +} + +static void sifive_set_ie(struct sifive_gpio *chip, unsigned int offset) +{ + unsigned long flags; + unsigned int trigger; + + raw_spin_lock_irqsave(&chip->lock, flags); + trigger = (chip->enabled & BIT(offset)) ? chip->trigger[offset] : 0; + sifive_assign_bit(chip->base + GPIO_RISE_IE, offset, + trigger & IRQ_TYPE_EDGE_RISING); + sifive_assign_bit(chip->base + GPIO_FALL_IE, offset, + trigger & IRQ_TYPE_EDGE_FALLING); + sifive_assign_bit(chip->base + GPIO_HIGH_IE, offset, + trigger & IRQ_TYPE_LEVEL_HIGH); + sifive_assign_bit(chip->base + GPIO_LOW_IE, offset, + trigger & IRQ_TYPE_LEVEL_LOW); + raw_spin_unlock_irqrestore(&chip->lock, flags); +} + +static int sifive_irq_set_type(struct irq_data *d, unsigned int trigger) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct sifive_gpio *chip = gpiochip_get_data(gc); + int offset = irqd_to_hwirq(d); + + if (offset < 0 || offset >= gc->ngpio) + return -EINVAL; + + chip->trigger[offset] = trigger; + sifive_set_ie(chip, offset); + return 0; +} + +/* chained_irq_{enter,exit} already mask the parent */ +static void sifive_irq_mask(struct irq_data *d) { } +static void sifive_irq_unmask(struct irq_data *d) { } + +static void sifive_irq_enable(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct sifive_gpio *chip = gpiochip_get_data(gc); + int offset = irqd_to_hwirq(d) % MAX_GPIO; // must not fail + u32 bit = BIT(offset); + + /* Switch to input */ + sifive_direction_input(gc, offset); + + /* Clear any sticky pending interrupts */ + iowrite32(bit, chip->base + GPIO_RISE_IP); + iowrite32(bit, chip->base + GPIO_FALL_IP); + iowrite32(bit, chip->base + GPIO_HIGH_IP); + iowrite32(bit, chip->base + GPIO_LOW_IP); + + /* Enable interrupts */ + assign_bit(offset, &chip->enabled, 1); + sifive_set_ie(chip, offset); +} + +static void sifive_irq_disable(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct sifive_gpio *chip = gpiochip_get_data(gc); + int offset = irqd_to_hwirq(d) % MAX_GPIO; // must not fail + + assign_bit(offset, &chip->enabled, 0); + sifive_set_ie(chip, offset); +} + +static struct irq_chip sifive_irqchip = { + .name = "sifive-gpio", + .irq_set_type = sifive_irq_set_type, + .irq_mask = sifive_irq_mask, + .irq_unmask = sifive_irq_unmask, + .irq_enable = sifive_irq_enable, + .irq_disable = sifive_irq_disable, +}; + +static void sifive_irq_handler(struct irq_desc *desc) +{ + struct irq_chip *irqchip = irq_desc_get_chip(desc); + struct sifive_gpio **self_ptr = irq_desc_get_handler_data(desc); + struct sifive_gpio *chip = *self_ptr; + int offset = self_ptr - &chip->self_ptr[0]; + u32 bit = BIT(offset); + + chained_irq_enter(irqchip, desc); + + /* Re-arm the edge triggers so don't miss the next one */ + iowrite32(bit, chip->base + GPIO_RISE_IP); + iowrite32(bit, chip->base + GPIO_FALL_IP); + + generic_handle_irq(irq_find_mapping(chip->gc.irq.domain, offset)); + + /* Re-arm the level triggers after handling to prevent spurious refire */ + iowrite32(bit, chip->base + GPIO_HIGH_IP); + iowrite32(bit, chip->base + GPIO_LOW_IP); + + chained_irq_exit(irqchip, desc); +} + +static int sifive_gpio_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *node = pdev->dev.of_node; + struct sifive_gpio *chip; + struct resource *res; + int gpio, irq, ret, ngpio; + + chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); + if (!chip) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + chip->base = devm_ioremap_resource(dev, res); + if (IS_ERR(chip->base)) { + dev_err(dev, "failed to allocate device memory\n"); + return PTR_ERR(chip->base); + } + + ngpio = of_irq_count(node); + if (ngpio >= MAX_GPIO) { + dev_err(dev, "Too many GPIO interrupts (max=%d)\n", MAX_GPIO); + return -ENXIO; + } + + raw_spin_lock_init(&chip->lock); + chip->gc.direction_input = sifive_direction_input; + chip->gc.direction_output = sifive_direction_output; + chip->gc.get_direction = sifive_get_direction; + chip->gc.get = sifive_get_value; + chip->gc.set = sifive_set_value; + chip->gc.base = -1; + chip->gc.ngpio = ngpio; + chip->gc.label = dev_name(dev); + chip->gc.parent = dev; + chip->gc.owner = THIS_MODULE; + + ret = gpiochip_add_data(&chip->gc, chip); + if (ret) + return ret; + + /* Disable all GPIO interrupts before enabling parent interrupts */ + iowrite32(0, chip->base + GPIO_RISE_IE); + iowrite32(0, chip->base + GPIO_FALL_IE); + iowrite32(0, chip->base + GPIO_HIGH_IE); + iowrite32(0, chip->base + GPIO_LOW_IE); + chip->enabled = 0; + + ret = gpiochip_irqchip_add(&chip->gc, &sifive_irqchip, 0, + handle_simple_irq, IRQ_TYPE_NONE); + if (ret) { + dev_err(dev, "could not add irqchip\n"); + gpiochip_remove(&chip->gc); + return ret; + } + + chip->gc.irq.num_parents = ngpio; + chip->gc.irq.parents = &chip->irq_parent[0]; + chip->gc.irq.map = &chip->irq_parent[0]; + + for (gpio = 0; gpio < ngpio; ++gpio) { + irq = platform_get_irq(pdev, gpio); + if (irq < 0) { + dev_err(dev, "invalid IRQ\n"); + gpiochip_remove(&chip->gc); + return -ENODEV; + } + + chip->irq_parent[gpio] = irq; + chip->self_ptr[gpio] = chip; + chip->trigger[gpio] = IRQ_TYPE_LEVEL_HIGH; + } + + for (gpio = 0; gpio < ngpio; ++gpio) { + irq = chip->irq_parent[gpio]; + irq_set_chained_handler_and_data(irq, sifive_irq_handler, + &chip->self_ptr[gpio]); + irq_set_parent(irq_find_mapping(chip->gc.irq.domain, gpio), + irq); + } + + platform_set_drvdata(pdev, chip); + dev_info(dev, "SiFive GPIO chip registered %d GPIOs\n", ngpio); + + return 0; +} + +static const struct of_device_id sifive_gpio_match[] = { + { .compatible = "sifive,gpio0" }, + { .compatible = "sifive,fu540-c000-gpio0" }, + { }, +}; + +static struct platform_driver sifive_gpio_driver = { + .probe = sifive_gpio_probe, + .driver = { + .name = "sifive_gpio", + .of_match_table = of_match_ptr(sifive_gpio_match), + }, +}; +builtin_platform_driver(sifive_gpio_driver)