From patchwork Tue Oct 2 20:55:33 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 978026 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="KHkDW4Fy"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 42Pryy372dz9s1c for ; Wed, 3 Oct 2018 06:55:50 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id B79DCC220B2; Tue, 2 Oct 2018 20:55:47 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id E89C5C21FB5; Tue, 2 Oct 2018 20:55:43 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 1DB11C21FB5; Tue, 2 Oct 2018 20:55:42 +0000 (UTC) Received: from mail-wr1-f67.google.com (mail-wr1-f67.google.com [209.85.221.67]) by lists.denx.de (Postfix) with ESMTPS id 93D3CC21F93 for ; Tue, 2 Oct 2018 20:55:41 +0000 (UTC) Received: by mail-wr1-f67.google.com with SMTP id g15-v6so1117292wru.9 for ; Tue, 02 Oct 2018 13:55:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=lbEtea0ILDxkbU+ssRHds0EFH/8rNmdBZjKOK0hkFo4=; b=KHkDW4Fy6nQaA75crId0ZGIytAu3QHQi5CL5Klu+8odeyB7RWa8d+3V5XfD/8uIhLt LsvMdlsq50ff3GTLhwfCBvkm77CnAQ7KBMZll63y7nH6g1UcK2SoqxZGdLc2NWTZBnP8 3tb4k585lZGb+T48Lvf+24CBA9oHq3DbJKcyS+omoLURxH+FNCy1dDcdEIxG1A+1Wx8S SI+h3h6bQnUlH5xwN5967Xrl6/oppeenEwCd8mUiYproDB6Je4Fz1YMQX2i7XC14McPP onh03yBadN85l2o4AO12oqYA48sRLYTTc40Fu+lzwKZSRbONptgPRBZg3a+bU3js+59D mthw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=lbEtea0ILDxkbU+ssRHds0EFH/8rNmdBZjKOK0hkFo4=; b=sj2VtgojmFJ6ynuR0MnoBlAIbMwu5EofAHO6ndTOZeEVAWlU5eCXIfzwruNOM/ujz5 oEWS+7C51toqKxfZW2BaAcFXSV701tX04hI/4cciqB+go3kfdVH2d2wYpz9u6kdAJRac 3+Ma/uwJMn+/vjGiH4jEn7UW+tUzdaAUay+binwKMhuaPXURFQh/fS47dPKvxSjh9RqV 12Y8tGtSffYdpBSuSFwA6Rq59FEysuqZYM6jsGIYLhf2Ilm1/dL5hAmYTfsHu9x89TDW PRvj/uV7YhVc+4mA1F5dvmwhABTqJiphAb7M3F5bUgD+runW+0VPCL+vPRHIdPt694uS laPg== X-Gm-Message-State: ABuFfog3KLRvgwfAk9uOY3SyVzh+VE25pRjxzxLROyI5g7dJeia639Kk 1svNVvUj7q6k+VvNOIIlioSTE9Jm X-Google-Smtp-Source: ACcGV625vdc9hzimZNoI0PSveTBNy6JPSgcv9SS2pjBMijkyrcipi3faO7qXOtIEIj8L0+amPFV9Jw== X-Received: by 2002:adf:b6a0:: with SMTP id j32-v6mr10954139wre.55.1538513740750; Tue, 02 Oct 2018 13:55:40 -0700 (PDT) Received: from kurokawa.lan (ip-86-49-30-92.net.upcbroadband.cz. [86.49.30.92]) by smtp.gmail.com with ESMTPSA id q5-v6sm20692301wmd.29.2018.10.02.13.55.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 02 Oct 2018 13:55:39 -0700 (PDT) From: Marek Vasut X-Google-Original-From: Marek Vasut To: u-boot@lists.denx.de Date: Tue, 2 Oct 2018 22:55:33 +0200 Message-Id: <20181002205534.9958-1-marek.vasut+renesas@gmail.com> X-Mailer: git-send-email 2.18.0 Cc: Marek Vasut Subject: [U-Boot] [PATCH 1/2] phy: rcar: Add R-Car Gen3 PHY driver X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add a PHY driver for the R-Car Gen3 which allows configuring USB OTG PHY on Gen3 into host mode and toggles VBUS in case a dedicated regulator is present. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- drivers/phy/Kconfig | 8 ++ drivers/phy/Makefile | 1 + drivers/phy/phy-rcar-gen3.c | 161 ++++++++++++++++++++++++++++++++++++ 3 files changed, 170 insertions(+) create mode 100644 drivers/phy/phy-rcar-gen3.c diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index bcc8e22795..14d82b93ed 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -118,6 +118,14 @@ config PHY_RCAR_GEN2 PHY connected to USBHS module, PCI EHCI module and USB3.0 module and allows configuring the module multiplexing. +config PHY_RCAR_GEN3 + tristate "Renesas R-Car Gen3 USB PHY" + depends on PHY && RCAR_GEN3 && CLK && DM_REGULATOR + default y if RCAR_GEN3 + help + Support for the Renesas R-Car Gen3 USB PHY. This driver operates the + PHY connected to EHCI USB module and controls USB OTG operation. + config PHY_STM32_USBPHYC tristate "STMicroelectronics STM32 SoC USB HS PHY driver" depends on PHY && ARCH_STM32MP diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index 1e1e4ca11e..8030d599e7 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_PHY_SANDBOX) += sandbox-phy.o obj-$(CONFIG_$(SPL_)PIPE3_PHY) += ti-pipe3-phy.o obj-$(CONFIG_STI_USB_PHY) += sti_usb_phy.o obj-$(CONFIG_PHY_RCAR_GEN2) += phy-rcar-gen2.o +obj-$(CONFIG_PHY_RCAR_GEN3) += phy-rcar-gen3.o obj-$(CONFIG_PHY_STM32_USBPHYC) += phy-stm32-usbphyc.o obj-$(CONFIG_MESON_GXL_USB_PHY) += meson-gxl-usb2.o meson-gxl-usb3.o obj-$(CONFIG_MSM8916_USB_PHY) += msm8916-usbh-phy.o diff --git a/drivers/phy/phy-rcar-gen3.c b/drivers/phy/phy-rcar-gen3.c new file mode 100644 index 0000000000..b662935626 --- /dev/null +++ b/drivers/phy/phy-rcar-gen3.c @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Renesas RCar Gen3 USB PHY driver + * + * Copyright (C) 2018 Marek Vasut + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* USB2.0 Host registers (original offset is +0x200) */ +#define USB2_INT_ENABLE 0x000 +#define USB2_USBCTR 0x00c +#define USB2_SPD_RSM_TIMSET 0x10c +#define USB2_OC_TIMSET 0x110 +#define USB2_COMMCTRL 0x600 +#define USB2_OBINTSTA 0x604 +#define USB2_OBINTEN 0x608 +#define USB2_VBCTRL 0x60c +#define USB2_LINECTRL1 0x610 +#define USB2_ADPCTRL 0x630 + +/* USBCTR */ +#define USB2_USBCTR_PLL_RST BIT(1) + +/* SPD_RSM_TIMSET */ +#define USB2_SPD_RSM_TIMSET_INIT 0x014e029b + +/* OC_TIMSET */ +#define USB2_OC_TIMSET_INIT 0x000209ab + +/* COMMCTRL */ +#define USB2_COMMCTRL_OTG_PERI BIT(31) /* 1 = Peripheral mode */ + +/* LINECTRL1 */ +#define USB2_LINECTRL1_DP_RPD BIT(18) +#define USB2_LINECTRL1_DM_RPD BIT(16) + +/* ADPCTRL */ +#define USB2_ADPCTRL_DRVVBUS BIT(4) + +struct rcar_gen3_phy { + fdt_addr_t regs; + struct clk clk; + struct udevice *vbus_supply; +}; + +static int rcar_gen3_phy_phy_init(struct phy *phy) +{ + struct rcar_gen3_phy *priv = dev_get_priv(phy->dev); + + /* Initialize USB2 part */ + writel(0, priv->regs + USB2_INT_ENABLE); + writel(USB2_SPD_RSM_TIMSET_INIT, priv->regs + USB2_SPD_RSM_TIMSET); + writel(USB2_OC_TIMSET_INIT, priv->regs + USB2_OC_TIMSET); + + setbits_le32(priv->regs + USB2_LINECTRL1, + USB2_LINECTRL1_DP_RPD | USB2_LINECTRL1_DM_RPD); + + clrbits_le32(priv->regs + USB2_COMMCTRL, USB2_COMMCTRL_OTG_PERI); + + setbits_le32(priv->regs + USB2_ADPCTRL, USB2_ADPCTRL_DRVVBUS); + + return 0; +} + +static int rcar_gen3_phy_phy_power_on(struct phy *phy) +{ + struct rcar_gen3_phy *priv = dev_get_priv(phy->dev); + int ret; + + if (priv->vbus_supply) { + ret = regulator_set_enable(priv->vbus_supply, true); + if (ret) + return ret; + } + + setbits_le32(priv->regs + USB2_USBCTR, USB2_USBCTR_PLL_RST); + clrbits_le32(priv->regs + USB2_USBCTR, USB2_USBCTR_PLL_RST); + + return 0; +} + +static int rcar_gen3_phy_phy_power_off(struct phy *phy) +{ + struct rcar_gen3_phy *priv = dev_get_priv(phy->dev); + + if (!priv->vbus_supply) + return 0; + + return regulator_set_enable(priv->vbus_supply, false); +} + +static const struct phy_ops rcar_gen3_phy_phy_ops = { + .init = rcar_gen3_phy_phy_init, + .power_on = rcar_gen3_phy_phy_power_on, + .power_off = rcar_gen3_phy_phy_power_off, +}; + +static int rcar_gen3_phy_probe(struct udevice *dev) +{ + struct rcar_gen3_phy *priv = dev_get_priv(dev); + int ret; + + priv->regs = dev_read_addr(dev); + if (priv->regs == FDT_ADDR_T_NONE) + return -EINVAL; + + ret = device_get_supply_regulator(dev, "vbus-supply", + &priv->vbus_supply); + if (ret && ret != -ENOENT) { + pr_err("Failed to get PHY regulator\n"); + return ret; + } + + /* Enable clock */ + ret = clk_get_by_index(dev, 0, &priv->clk); + if (ret) + return ret; + + ret = clk_enable(&priv->clk); + if (ret) + return ret; + + return 0; +} + +static int rcar_gen3_phy_remove(struct udevice *dev) +{ + struct rcar_gen3_phy *priv = dev_get_priv(dev); + + clk_disable(&priv->clk); + clk_free(&priv->clk); + + return 0; +} + +static const struct udevice_id rcar_gen3_phy_of_match[] = { + { .compatible = "renesas,rcar-gen3-usb2-phy", }, + { }, +}; + +U_BOOT_DRIVER(rcar_gen3_phy) = { + .name = "rcar-gen3-phy", + .id = UCLASS_PHY, + .of_match = rcar_gen3_phy_of_match, + .ops = &rcar_gen3_phy_phy_ops, + .probe = rcar_gen3_phy_probe, + .remove = rcar_gen3_phy_remove, + .priv_auto_alloc_size = sizeof(struct rcar_gen3_phy), +}; From patchwork Tue Oct 2 20:55:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 978027 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; 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[86.49.30.92]) by smtp.gmail.com with ESMTPSA id q5-v6sm20692301wmd.29.2018.10.02.13.55.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 02 Oct 2018 13:55:41 -0700 (PDT) From: Marek Vasut X-Google-Original-From: Marek Vasut To: u-boot@lists.denx.de Date: Tue, 2 Oct 2018 22:55:34 +0200 Message-Id: <20181002205534.9958-2-marek.vasut+renesas@gmail.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20181002205534.9958-1-marek.vasut+renesas@gmail.com> References: <20181002205534.9958-1-marek.vasut+renesas@gmail.com> Cc: Marek Vasut Subject: [U-Boot] [PATCH 2/2] ARM: rmobile: Enable PHY framework on Gen3 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Enable PHY framework on Gen3, this is required for USB EHCI PHY support. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- arch/arm/mach-rmobile/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-rmobile/Kconfig b/arch/arm/mach-rmobile/Kconfig index fc4b3c3219..ac08d6eb12 100644 --- a/arch/arm/mach-rmobile/Kconfig +++ b/arch/arm/mach-rmobile/Kconfig @@ -11,6 +11,7 @@ config RCAR_32 config RCAR_GEN3 bool "Renesas ARM SoCs R-Car Gen3 (64bit)" select ARM64 + select PHY endchoice