From patchwork Wed Sep 26 15:22:31 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Uros Bizjak X-Patchwork-Id: 975209 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-486465-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="lIUgSs7D"; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="V2RiUdln"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42L1sJ5zMcz9s55 for ; Thu, 27 Sep 2018 01:22:43 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:content-type; q= dns; s=default; b=YsR01gsXPKAURC5npOR5IKAd6a3G/GdBoIis9R0MBDriQn xVab4eJKCMUvNSDSRvQbtnGplGSBI9rg0d8yrUSXuPXrEab8JavyblqYJCfQ1S41 6Co9WugQe2MNxlg6UNmUtaaasFJq3tEMxV69Yo3xWMyTVQktaIrR2EK/piudo= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:content-type; s= default; bh=LLdphHuBeYbvDvGVyyYSUAv5SOk=; b=lIUgSs7D16IbR9CZ/g3f TC0Z6ewV55Zz5P4UHDXw+s0BrYneinNshqbRh8Gggj1PaD9lbvxaF4b04rB6wwBO NlejWLNNDVk+A/i585hF8+S1YNatbct14XNa4kGQAWhKrKbD/XeNsyJVOWi3+OWy WbkVGOZy5WFoxIMhxDQXK3A= Received: (qmail 31095 invoked by alias); 26 Sep 2018 15:22:35 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 31081 invoked by uid 89); 26 Sep 2018 15:22:35 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-11.0 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, GIT_PATCH_2, GIT_PATCH_3, KAM_ASCII_DIVIDERS, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mail-it1-f180.google.com Received: from mail-it1-f180.google.com (HELO mail-it1-f180.google.com) (209.85.166.180) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 26 Sep 2018 15:22:33 +0000 Received: by mail-it1-f180.google.com with SMTP id f14-v6so3465027ita.4 for ; Wed, 26 Sep 2018 08:22:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:from:date:message-id:subject:to; bh=GOwpQlsA9g7PW9Yr+plVl/oRehAxshwVLAIHtN77GNY=; b=V2RiUdln5S8LhSYGNy5bjTMXQzsZZEUjmT7JHj+HM0pMvqWpMoQb4NEXgY1ntaAey5 k9ug+WSDzC0PnY6itujX2Gps7iyPZCJzPTwoqAmge/zboK0oINyhmr4FjmOmwSN0QSKC V5rD8IKkN3El06JM13brt+WPcCypf2pytYkvy6EEAqJQxY+4QBP/3BXC26/qyeP6E3C2 hF7yQEPc76M9YjDYe0mUb2q9iS/r3Yv4ZOiL13nEeMKC0PLnHzYLZScdi9yQhOV6u8w0 2Q7P4PdWE4D9zBAeNaK70JH3yQ4zn2wFmjPKYAZ2+/bpGMQ982g7iBEx4YTpox4IVyTP JtVg== MIME-Version: 1.0 Received: by 2002:a02:569c:0:0:0:0:0 with HTTP; Wed, 26 Sep 2018 08:22:31 -0700 (PDT) From: Uros Bizjak Date: Wed, 26 Sep 2018 17:22:31 +0200 Message-ID: Subject: [PATCH, i386]: Do not use "u" constraint and remove FP_TOP_SSE_REGS and FP_SECOND_SSE_REGS register classes To: "gcc-patches@gcc.gnu.org" Hello! Stack registers are fixed up by regstack pass, so there is no point to specify "upper" FP register in the instruction patterns. This change allows register allocator a bit more freedom, which results in a few fxch instructions less. The patch also removes FP_TOP_SSE_REGS and FP_SECOND_SSE_REGS mixed classes. We don't have any insn patterns that would allow the mix of "t"/"u" and SSE regs, so the class is neverused. Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}. Committed to mainline SVN. Uros. Index: config/i386/i386.c =================================================================== --- config/i386/i386.c (revision 264643) +++ config/i386/i386.c (working copy) @@ -39043,10 +39043,6 @@ ix86_preferred_reload_class (rtx x, reg_class_t re /* Limit class to FP regs. */ if (FLOAT_CLASS_P (regclass)) return FLOAT_REGS; - else if (regclass == FP_TOP_SSE_REGS) - return FP_TOP_REG; - else if (regclass == FP_SECOND_SSE_REGS) - return FP_SECOND_REG; } return NO_REGS; @@ -39092,14 +39088,7 @@ ix86_preferred_output_reload_class (rtx x, reg_cla return MAYBE_SSE_CLASS_P (regclass) ? ALL_SSE_REGS : NO_REGS; if (IS_STACK_MODE (mode)) - { - if (regclass == FP_TOP_SSE_REGS) - return FP_TOP_REG; - else if (regclass == FP_SECOND_SSE_REGS) - return FP_SECOND_REG; - else - return FLOAT_CLASS_P (regclass) ? regclass : NO_REGS; - } + return FLOAT_CLASS_P (regclass) ? regclass : NO_REGS; return regclass; } Index: config/i386/i386.h =================================================================== --- config/i386/i386.h (revision 264645) +++ config/i386/i386.h (working copy) @@ -1337,8 +1337,6 @@ enum reg_class SSE_REGS, ALL_SSE_REGS, MMX_REGS, - FP_TOP_SSE_REGS, - FP_SECOND_SSE_REGS, FLOAT_SSE_REGS, FLOAT_INT_REGS, INT_SSE_REGS, @@ -1398,8 +1396,6 @@ enum reg_class "SSE_REGS", \ "ALL_SSE_REGS", \ "MMX_REGS", \ - "FP_TOP_SSE_REGS", \ - "FP_SECOND_SSE_REGS", \ "FLOAT_SSE_REGS", \ "FLOAT_INT_REGS", \ "INT_SSE_REGS", \ @@ -1438,8 +1434,6 @@ enum reg_class { 0x1fe00000, 0x1fe000, 0x0 }, /* SSE_REGS */ \ { 0x1fe00000, 0xffffe000, 0x1f }, /* ALL_SSE_REGS */ \ { 0xe0000000, 0x1f, 0x0 }, /* MMX_REGS */ \ -{ 0x1fe00100, 0xffffe000, 0x1f }, /* FP_TOP_SSE_REG */ \ -{ 0x1fe00200, 0xffffe000, 0x1f }, /* FP_SECOND_SSE_REG */ \ { 0x1fe0ff00, 0xffffe000, 0x1f }, /* FLOAT_SSE_REGS */ \ { 0x11ffff, 0x1fe0, 0x0 }, /* FLOAT_INT_REGS */ \ { 0x1ff100ff, 0xffffffe0, 0x1f }, /* INT_SSE_REGS */ \ Index: config/i386/i386.md =================================================================== --- config/i386/i386.md (revision 264643) +++ config/i386/i386.md (working copy) @@ -4973,7 +4973,7 @@ (define_insn "fix_trunc_i387_fisttp" [(set (match_operand:SWI248x 0 "nonimmediate_operand" "=m") (fix:SWI248x (match_operand 1 "register_operand" "f"))) - (clobber (match_scratch:XF 2 "=&1f"))] + (clobber (match_scratch:XF 2 "=&f"))] "X87_FLOAT_MODE_P (GET_MODE (operands[1])) && TARGET_FISTTP && !((SSE_FLOAT_MODE_P (GET_MODE (operands[1])) @@ -5019,7 +5019,7 @@ (fix:DI (match_operand 1 "register_operand" "f"))) (use (match_operand:HI 2 "memory_operand" "m")) (use (match_operand:HI 3 "memory_operand" "m")) - (clobber (match_scratch:XF 4 "=&1f"))] + (clobber (match_scratch:XF 4 "=&f"))] "X87_FLOAT_MODE_P (GET_MODE (operands[1])) && !TARGET_FISTTP && !(TARGET_64BIT && SSE_FLOAT_MODE_P (GET_MODE (operands[1])))" @@ -15178,7 +15178,7 @@ (unspec:XF [(match_operand:XF 2 "register_operand" "0") (match_operand:XF 3 "register_operand" "1")] UNSPEC_FPREM_F)) - (set (match_operand:XF 1 "register_operand" "=u") + (set (match_operand:XF 1 "register_operand" "=f") (unspec:XF [(match_dup 2) (match_dup 3)] UNSPEC_FPREM_U)) (set (reg:CCFP FPSR_REG) @@ -15253,7 +15253,7 @@ (unspec:XF [(match_operand:XF 2 "register_operand" "0") (match_operand:XF 3 "register_operand" "1")] UNSPEC_FPREM1_F)) - (set (match_operand:XF 1 "register_operand" "=u") + (set (match_operand:XF 1 "register_operand" "=f") (unspec:XF [(match_dup 2) (match_dup 3)] UNSPEC_FPREM1_U)) (set (reg:CCFP FPSR_REG) @@ -15365,7 +15365,7 @@ [(set (match_operand:XF 0 "register_operand" "=f") (unspec:XF [(match_operand:XF 2 "register_operand" "0")] UNSPEC_SINCOS_COS)) - (set (match_operand:XF 1 "register_operand" "=u") + (set (match_operand:XF 1 "register_operand" "=f") (unspec:XF [(match_dup 2)] UNSPEC_SINCOS_SIN))] "TARGET_USE_FANCY_MATH_387 && flag_unsafe_math_optimizations" @@ -15397,7 +15397,7 @@ (define_insn "fptanxf4_i387" [(set (match_operand:SF 0 "register_operand" "=f") (match_operand:SF 3 "const1_operand")) - (set (match_operand:XF 1 "register_operand" "=u") + (set (match_operand:XF 1 "register_operand" "=f") (unspec:XF [(match_operand:XF 2 "register_operand" "0")] UNSPEC_TAN))] "TARGET_USE_FANCY_MATH_387 @@ -15439,7 +15439,7 @@ (define_insn "atan2xf3" [(set (match_operand:XF 0 "register_operand" "=f") (unspec:XF [(match_operand:XF 1 "register_operand" "0") - (match_operand:XF 2 "register_operand" "u")] + (match_operand:XF 2 "register_operand" "f")] UNSPEC_FPATAN)) (clobber (match_scratch:XF 3 "=2"))] "TARGET_USE_FANCY_MATH_387 @@ -15576,7 +15576,7 @@ (define_insn "fyl2xxf3_i387" [(set (match_operand:XF 0 "register_operand" "=f") (unspec:XF [(match_operand:XF 1 "register_operand" "0") - (match_operand:XF 2 "register_operand" "u")] + (match_operand:XF 2 "register_operand" "f")] UNSPEC_FYL2X)) (clobber (match_scratch:XF 3 "=2"))] "TARGET_USE_FANCY_MATH_387 @@ -15673,7 +15673,7 @@ (define_insn "fyl2xp1xf3_i387" [(set (match_operand:XF 0 "register_operand" "=f") (unspec:XF [(match_operand:XF 1 "register_operand" "0") - (match_operand:XF 2 "register_operand" "u")] + (match_operand:XF 2 "register_operand" "f")] UNSPEC_FYL2XP1)) (clobber (match_scratch:XF 3 "=2"))] "TARGET_USE_FANCY_MATH_387 @@ -15714,7 +15714,7 @@ [(set (match_operand:XF 0 "register_operand" "=f") (unspec:XF [(match_operand:XF 2 "register_operand" "0")] UNSPEC_XTRACT_FRACT)) - (set (match_operand:XF 1 "register_operand" "=u") + (set (match_operand:XF 1 "register_operand" "=f") (unspec:XF [(match_dup 2)] UNSPEC_XTRACT_EXP))] "TARGET_USE_FANCY_MATH_387 && flag_unsafe_math_optimizations" @@ -15808,7 +15808,7 @@ (unspec:XF [(match_operand:XF 2 "register_operand" "0") (match_operand:XF 3 "register_operand" "1")] UNSPEC_FSCALE_FRACT)) - (set (match_operand:XF 1 "register_operand" "=u") + (set (match_operand:XF 1 "register_operand" "=f") (unspec:XF [(match_dup 2) (match_dup 3)] UNSPEC_FSCALE_EXP))] "TARGET_USE_FANCY_MATH_387 @@ -16193,7 +16193,7 @@ [(set (match_operand:DI 0 "nonimmediate_operand" "=m") (unspec:DI [(match_operand:XF 1 "register_operand" "f")] UNSPEC_FIST)) - (clobber (match_scratch:XF 2 "=&1f"))] + (clobber (match_scratch:XF 2 "=&f"))] "TARGET_USE_FANCY_MATH_387" "* return output_fix_trunc (insn, operands, false);" [(set_attr "type" "fpspc") @@ -16404,7 +16404,7 @@ FIST_ROUNDING)) (use (match_operand:HI 2 "memory_operand" "m")) (use (match_operand:HI 3 "memory_operand" "m")) - (clobber (match_scratch:XF 4 "=&1f"))] + (clobber (match_scratch:XF 4 "=&f"))] "TARGET_USE_FANCY_MATH_387 && flag_unsafe_math_optimizations" "* return output_fix_trunc (insn, operands, false);"