From patchwork Fri Sep 21 10:27:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 973116 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="WVNhdzdl"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42GqYN2FgRz9sCR for ; Fri, 21 Sep 2018 20:27:52 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390158AbeIUQQD (ORCPT ); Fri, 21 Sep 2018 12:16:03 -0400 Received: from mail-wm1-f66.google.com ([209.85.128.66]:39339 "EHLO mail-wm1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389597AbeIUQQC (ORCPT ); Fri, 21 Sep 2018 12:16:02 -0400 Received: by mail-wm1-f66.google.com with SMTP id q8-v6so2650085wmq.4 for ; Fri, 21 Sep 2018 03:27:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=6eG+y8DE0e6kg/HMySbQLPa84rZ5sgM7GX6ZmEsFO7M=; b=WVNhdzdlYnxxT4WgBI7+13ZEjrADDBXaX8YeA9hgNJ81vdHDzu9Nsnxp4PiI3mKuH3 ZKZVZC4NWG4rFvVd/H3tW3dzbhi58O9t9bCoEjkHkBjrnq+VyXtPglr0INj0ga+5hezc DjXBl427PzGyq8Ta9VcQ4dYldZOzkY38Sf5Z9wxa0pzfiwLVKbWLr5S//Ar8dhr2xi9J hBtHyUf91Jl5cTvlDVIEMb7GPM3oePv9mEbqN6ThH8GS72vCRthSrdkrFdbrEVYFDVDk xuc3MGtcoVgy61YInvKgW/23m7H6t1t2N4Xk4w0EJHiE+YY8LYQTAl2n7sDDGYLJ5hnn fDug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=6eG+y8DE0e6kg/HMySbQLPa84rZ5sgM7GX6ZmEsFO7M=; b=i8tsbim7lIz/HO0tKeX9gIhYBAHORr7y4A4WqkztrOAow/Ai5Li3e/nsl/+/1Kv+rQ stCJt8h2LBcg6JkH2Rn9l0jNhJjltrYB2j9/fFE4Y0SMZ/PL9lGdueTj4PXFHdQX05hP eUbMPVRTq56pCZRDe73/usxiVEmik3QgWdYlGa09E4EwcBo9+OlwAzEFPiwC/O8A1a5x gw++1VPZzy49AiWoV1l+uCscHz1YMCXhv2S0sC/zMNv9xaRVNALt+V0QT2QcDw99bttX NqbMQFGsBvjJRmjfOzqOdFWO7kYV7TROdoPWu0i953sq79HM4PX4T7RTTEsdzoX5Rh6F zjpQ== X-Gm-Message-State: ABuFfohJXKgYa5GCieP34YTcdl++icyPv+EPDpmb9BTsfHmU6AJoX1S5 zni5kSNmJ+sdAU+slfkDCb0Scrca X-Google-Smtp-Source: ANB0VdYMVFdFWFPugDKVZ7RcZCQeRrrYNnNnWHDDluHIhuduivxuiZaGHFweukDwB+Buc0RVNSFuIw== X-Received: by 2002:a1c:545d:: with SMTP id p29-v6mr6268544wmi.94.1537525667710; Fri, 21 Sep 2018 03:27:47 -0700 (PDT) Received: from localhost (pD9E515A3.dip0.t-ipconnect.de. [217.229.21.163]) by smtp.gmail.com with ESMTPSA id t25-v6sm3527519wmh.15.2018.09.21.03.27.47 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 21 Sep 2018 03:27:47 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: dri-devel@lists.freedesktop.org, linux-tegra@vger.kernel.org Subject: [PATCH 1/5] drm/tegra: dc: Do not register DC without primary plane Date: Fri, 21 Sep 2018 12:27:42 +0200 Message-Id: <20180921102746.13095-1-thierry.reding@gmail.com> X-Mailer: git-send-email 2.19.0 MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding Tegra194 contains a fourth display controller that does not own any windows. Therefore, we cannot currently assign a primary plane to it which causes KMS to eventually crash. Do not register the display controller if it owns no windows to work around this. Note that we still have to enable and probe the display controller because for some reason all display controllers need to be powered (and/or clocked) before any registers can be accessed in any of the display controllers. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/dc.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c index 965088afcfad..7e36ca204cbb 100644 --- a/drivers/gpu/drm/tegra/dc.c +++ b/drivers/gpu/drm/tegra/dc.c @@ -1988,6 +1988,28 @@ static int tegra_dc_init(struct host1x_client *client) struct drm_plane *cursor = NULL; int err; + /* + * XXX do not register DCs with no window groups because we cannot + * assign a primary plane to them, which in turn will cause KMS to + * crash. + */ + if (dc->soc->wgrps) { + bool has_wgrps = false; + unsigned int i; + + for (i = 0; i < dc->soc->num_wgrps; i++) { + const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i]; + + if (wgrp->dc == dc->pipe && wgrp->num_windows > 0) { + has_wgrps = true; + break; + } + } + + if (!has_wgrps) + return 0; + } + dc->syncpt = host1x_syncpt_request(client, flags); if (!dc->syncpt) dev_warn(dc->dev, "failed to allocate syncpoint\n"); From patchwork Fri Sep 21 10:27:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 973118 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="utDjxaSl"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42GqYQ1lSyz9sCc for ; Fri, 21 Sep 2018 20:27:54 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390179AbeIUQQE (ORCPT ); Fri, 21 Sep 2018 12:16:04 -0400 Received: from mail-wm1-f65.google.com ([209.85.128.65]:33242 "EHLO mail-wm1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389559AbeIUQQD (ORCPT ); Fri, 21 Sep 2018 12:16:03 -0400 Received: by mail-wm1-f65.google.com with SMTP id r1-v6so3810674wmh.0 for ; Fri, 21 Sep 2018 03:27:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=40bb0+WmqLAtyKglgtWlL+4iGnuAWWqAbBMxdPn3vkM=; b=utDjxaSlW+pkPCX8P5KhLbCQ0jFwo1PKnKoZ8cHScr4JXbykkoSr5O8mUqB5EtdlVZ Qx9gx6HyPH/4wq3OsdMg3qDPgVsmqC7iIgyfKpBA7MCN5Y98PXAIKnICqokn87V5OPxB OpQTQkEQXmgxjI7OnOpFjqWdTtJQ7kz3p/aWeEAQY3QgV2TJwvjEdal5r6ePFvIv9Cnj yhcoFdU4KyOPN4fDMtyWutWWJnRTpz6eTtnoNAyP0QoTn/iNCiAlLyWvxzo9llcNhzRc 061Tnl1oIUJUfUl7IvCXvFcAmdiY1auGIPQuI8tsuofL5HJ6v2WVPBgFtRCF9JvaPI6J iSgg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=40bb0+WmqLAtyKglgtWlL+4iGnuAWWqAbBMxdPn3vkM=; b=fgfsUSDp0Ma4RpxtIskG4Hsf1GFNoVzEWjyXubliaoKR5HFjKFNGHERLoUKVOactYI YWp0nAf1OwAh0F2evXowBHXpMWubt2N4NyZrDdBjyJ+B5b6LH/eNBEGlAH6ZVInx5zEv zYsNbqVc0dS/IvaO2DKAdCyqDuChg+kBGAZzq7DvCgF/CFezfBh2l7akrlfPyghpcFTn xyaUU5p40ikkjXDuSe9Bn2vYn7oLv2rSLvLMsdvedURnbH6O087W1AJ22qK0Ig66QwOO SWlIYFc2GpQ27hEO2AC3SJE0ojMPJm0TMhNEjdtWlE45LdyJErFmka/DfLgZRa0qOiBk tGGA== X-Gm-Message-State: APzg51B/TZNdEgHKoiRXCOX9HOvPJlTP2PG99HoPQF1q1ladNRqb4SW7 T9VHAfF0SywDWStuZT3I0rs= X-Google-Smtp-Source: ACcGV60Bz8m6uaWsfFgH2BIPbye41MI9SHp//TUhzdnXhB9t/qtsgTKfmoTQl5FkGfD59DBBAC0wAw== X-Received: by 2002:a1c:2dc8:: with SMTP id t191-v6mr6724971wmt.94.1537525669045; Fri, 21 Sep 2018 03:27:49 -0700 (PDT) Received: from localhost (pD9E515A3.dip0.t-ipconnect.de. [217.229.21.163]) by smtp.gmail.com with ESMTPSA id 198-v6sm7578530wmm.0.2018.09.21.03.27.48 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 21 Sep 2018 03:27:48 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: dri-devel@lists.freedesktop.org, linux-tegra@vger.kernel.org Subject: [PATCH 2/5] drm/tegra: hub: Add Tegra194 support Date: Fri, 21 Sep 2018 12:27:43 +0200 Message-Id: <20180921102746.13095-2-thierry.reding@gmail.com> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20180921102746.13095-1-thierry.reding@gmail.com> References: <20180921102746.13095-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The display hub integrated into Tegra194 is almost identical to the one found on Tegra186. However, it doesn't support DSC (display stream compression) so it isn't fully compatible. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/drm.c | 1 + drivers/gpu/drm/tegra/hub.c | 19 +++++++++++++++---- drivers/gpu/drm/tegra/hub.h | 1 + 3 files changed, 17 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c index b424bc911b95..b31dcf5c9524 100644 --- a/drivers/gpu/drm/tegra/drm.c +++ b/drivers/gpu/drm/tegra/drm.c @@ -1275,6 +1275,7 @@ static const struct of_device_id host1x_drm_subdevs[] = { { .compatible = "nvidia,tegra186-sor", }, { .compatible = "nvidia,tegra186-sor1", }, { .compatible = "nvidia,tegra186-vic", }, + { .compatible = "nvidia,tegra194-display", }, { /* sentinel */ } }; diff --git a/drivers/gpu/drm/tegra/hub.c b/drivers/gpu/drm/tegra/hub.c index 8f4fcbb515fb..6112d9042979 100644 --- a/drivers/gpu/drm/tegra/hub.c +++ b/drivers/gpu/drm/tegra/hub.c @@ -758,10 +758,12 @@ static int tegra_display_hub_probe(struct platform_device *pdev) return err; } - hub->clk_dsc = devm_clk_get(&pdev->dev, "dsc"); - if (IS_ERR(hub->clk_dsc)) { - err = PTR_ERR(hub->clk_dsc); - return err; + if (hub->soc->supports_dsc) { + hub->clk_dsc = devm_clk_get(&pdev->dev, "dsc"); + if (IS_ERR(hub->clk_dsc)) { + err = PTR_ERR(hub->clk_dsc); + return err; + } } hub->clk_hub = devm_clk_get(&pdev->dev, "hub"); @@ -890,10 +892,19 @@ static const struct dev_pm_ops tegra_display_hub_pm_ops = { static const struct tegra_display_hub_soc tegra186_display_hub = { .num_wgrps = 6, + .supports_dsc = true, +}; + +static const struct tegra_display_hub_soc tegra194_display_hub = { + .num_wgrps = 6, + .supports_dsc = false, }; static const struct of_device_id tegra_display_hub_of_match[] = { { + .compatible = "nvidia,tegra194-display", + .data = &tegra194_display_hub + }, { .compatible = "nvidia,tegra186-display", .data = &tegra186_display_hub }, { diff --git a/drivers/gpu/drm/tegra/hub.h b/drivers/gpu/drm/tegra/hub.h index 85b8bf41a395..6696a85fc1f2 100644 --- a/drivers/gpu/drm/tegra/hub.h +++ b/drivers/gpu/drm/tegra/hub.h @@ -38,6 +38,7 @@ to_tegra_shared_plane(struct drm_plane *plane) struct tegra_display_hub_soc { unsigned int num_wgrps; + bool supports_dsc; }; struct tegra_display_hub { From patchwork Fri Sep 21 10:27:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 973119 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="NDguGpQ/"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42GqYR0CbJz9sCR for ; Fri, 21 Sep 2018 20:27:55 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390159AbeIUQQF (ORCPT ); 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[217.229.21.163]) by smtp.gmail.com with ESMTPSA id b189-v6sm5784005wmd.39.2018.09.21.03.27.49 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 21 Sep 2018 03:27:49 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: dri-devel@lists.freedesktop.org, linux-tegra@vger.kernel.org Subject: [PATCH 3/5] drm/tegra: dc: Add Tegra194 support Date: Fri, 21 Sep 2018 12:27:44 +0200 Message-Id: <20180921102746.13095-3-thierry.reding@gmail.com> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20180921102746.13095-1-thierry.reding@gmail.com> References: <20180921102746.13095-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The display controllers found on Tegra194 are almost identical to those found on Tegra186. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/dc.c | 51 +++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/tegra/dc.h | 2 +- drivers/gpu/drm/tegra/drm.c | 1 + 3 files changed, 53 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c index 7e36ca204cbb..f80e82e16475 100644 --- a/drivers/gpu/drm/tegra/dc.c +++ b/drivers/gpu/drm/tegra/dc.c @@ -2256,8 +2256,59 @@ static const struct tegra_dc_soc_info tegra186_dc_soc_info = { .num_wgrps = ARRAY_SIZE(tegra186_dc_wgrps), }; +static const struct tegra_windowgroup_soc tegra194_dc_wgrps[] = { + { + .index = 0, + .dc = 0, + .windows = (const unsigned int[]) { 0 }, + .num_windows = 1, + }, { + .index = 1, + .dc = 1, + .windows = (const unsigned int[]) { 1 }, + .num_windows = 1, + }, { + .index = 2, + .dc = 1, + .windows = (const unsigned int[]) { 2 }, + .num_windows = 1, + }, { + .index = 3, + .dc = 2, + .windows = (const unsigned int[]) { 3 }, + .num_windows = 1, + }, { + .index = 4, + .dc = 2, + .windows = (const unsigned int[]) { 4 }, + .num_windows = 1, + }, { + .index = 5, + .dc = 2, + .windows = (const unsigned int[]) { 5 }, + .num_windows = 1, + }, +}; + +static const struct tegra_dc_soc_info tegra194_dc_soc_info = { + .supports_background_color = true, + .supports_interlacing = true, + .supports_cursor = true, + .supports_block_linear = true, + .has_legacy_blending = false, + .pitch_align = 64, + .has_powergate = false, + .coupled_pm = false, + .has_nvdisplay = true, + .wgrps = tegra194_dc_wgrps, + .num_wgrps = ARRAY_SIZE(tegra194_dc_wgrps), +}; + static const struct of_device_id tegra_dc_of_match[] = { { + .compatible = "nvidia,tegra194-dc", + .data = &tegra194_dc_soc_info, + }, { .compatible = "nvidia,tegra186-dc", .data = &tegra186_dc_soc_info, }, { diff --git a/drivers/gpu/drm/tegra/dc.h b/drivers/gpu/drm/tegra/dc.h index e96f582ca692..1256dfb6b2f5 100644 --- a/drivers/gpu/drm/tegra/dc.h +++ b/drivers/gpu/drm/tegra/dc.h @@ -300,7 +300,7 @@ int tegra_dc_rgb_exit(struct tegra_dc *dc); #define SOR1_TIMING_CYA (1 << 27) #define CURSOR_ENABLE (1 << 16) -#define SOR_ENABLE(x) (1 << (25 + (x))) +#define SOR_ENABLE(x) (1 << (25 + (((x) > 1) ? ((x) + 1) : (x)))) #define DC_DISP_DISP_MEM_HIGH_PRIORITY 0x403 #define CURSOR_THRESHOLD(x) (((x) & 0x03) << 24) diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c index b31dcf5c9524..395b048447b2 100644 --- a/drivers/gpu/drm/tegra/drm.c +++ b/drivers/gpu/drm/tegra/drm.c @@ -1276,6 +1276,7 @@ static const struct of_device_id host1x_drm_subdevs[] = { { .compatible = "nvidia,tegra186-sor1", }, { .compatible = "nvidia,tegra186-vic", }, { .compatible = "nvidia,tegra194-display", }, + { .compatible = "nvidia,tegra194-dc", }, { /* sentinel */ } }; From patchwork Fri Sep 21 10:27:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 973120 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="FTSU01NL"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42GqYT2QlFz9sCS for ; Fri, 21 Sep 2018 20:27:57 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389264AbeIUQQG (ORCPT ); Fri, 21 Sep 2018 12:16:06 -0400 Received: from mail-wm1-f65.google.com ([209.85.128.65]:40746 "EHLO mail-wm1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389559AbeIUQQG (ORCPT ); Fri, 21 Sep 2018 12:16:06 -0400 Received: by mail-wm1-f65.google.com with SMTP id 207-v6so2629104wme.5 for ; Fri, 21 Sep 2018 03:27:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=53iGXaBAXugRK1ScM7OaH9kvHSwsJY7aMadyLnnbN4Q=; b=FTSU01NL970tIIwbccZ7zbuUJ0R95L3bq+Ne4d+dvUkT+Ea9L4IrucNNuir4lA3Ddp tMlOpTOTVz086JZtdDSP1prz385scYbMhbALVgB1FAg5Zue1gIh4ucjkVd+EvEybbSKp dg9yxEaD99XntOhQva/0oxQeNEAayfcUPPlM+xFJcrvbwKJekzQriyF+G06qAlbfH+Wl U4moS9f1JfSZIe8K7XcQleHZB1Fl9ASCEWUFnn1NPRqjN+cCXe5pqV89hqfQNjpajZ5e 7Bjtl2FEqxw3RXYVG5EZwUZdUFKwm7kIs/Ef55TcF4UUx9qf0gF/V97KIvt/0PYUt9OB vQCw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=53iGXaBAXugRK1ScM7OaH9kvHSwsJY7aMadyLnnbN4Q=; b=CDY253N01srUv2K0djBCYW5PIXlSu314XpomFq/iFek3Z7uljmhIlENQ7PjPhDU7js zG0J79m7XS+/3eNuAfb4WFGFh9QSHTpFzGaNYYHBqmZjYkaF6bIhq5NSc4WoHrKImusL zkAFd611QNdsB9TcK3/T7tYWii/w/b3P8bKakPK8jShuRAvqkKdsAV30G6Q4RBUVW/WE gOs3MbmCA0KBj91JBjfIIYgA7rCi1BYACOdMIyDo9sJIGQS9G73b5PatMuBUz2e/2dy+ RDVzYcDFN+1ss1USWiDfpNQQUT3PWLmle6y/LWIbCNFsuNimr+1jy8M7waGK5nibZwj4 CHcA== X-Gm-Message-State: APzg51DHhYgCl1ewKnEywXnIS3enS1/WW9DB8myfkMtzzoTbaNh5GpGN mdiLm8PecVztGpRnc5pTXyc= X-Google-Smtp-Source: ANB0VdbDD+4U2Zv0kb8esHgPclFRqSyPy9U3Tk+EvIDWYWUD6Hbes+UY/jI7x8foodVh9tRDrSL3gA== X-Received: by 2002:a1c:e4c3:: with SMTP id b186-v6mr6651121wmh.116.1537525671770; Fri, 21 Sep 2018 03:27:51 -0700 (PDT) Received: from localhost (pD9E515A3.dip0.t-ipconnect.de. [217.229.21.163]) by smtp.gmail.com with ESMTPSA id p89-v6sm61966740wrc.97.2018.09.21.03.27.51 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 21 Sep 2018 03:27:51 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: dri-devel@lists.freedesktop.org, linux-tegra@vger.kernel.org Subject: [PATCH 4/5] drm/tegra: dpaux: Add Tegra194 support Date: Fri, 21 Sep 2018 12:27:45 +0200 Message-Id: <20180921102746.13095-4-thierry.reding@gmail.com> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20180921102746.13095-1-thierry.reding@gmail.com> References: <20180921102746.13095-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The DPAUX controller found on Tegra194 is almost identical to its predecessor from Tegra186. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/dpaux.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/tegra/dpaux.c b/drivers/gpu/drm/tegra/dpaux.c index d84e81ff36ad..b96817b0130d 100644 --- a/drivers/gpu/drm/tegra/dpaux.c +++ b/drivers/gpu/drm/tegra/dpaux.c @@ -639,6 +639,7 @@ static const struct dev_pm_ops tegra_dpaux_pm_ops = { }; static const struct of_device_id tegra_dpaux_of_match[] = { + { .compatible = "nvidia,tegra194-dpaux", }, { .compatible = "nvidia,tegra186-dpaux", }, { .compatible = "nvidia,tegra210-dpaux", }, { .compatible = "nvidia,tegra124-dpaux", }, From patchwork Fri Sep 21 10:27:46 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 973121 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="gCMC8Kgf"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42GqYV4F98z9sCc for ; Fri, 21 Sep 2018 20:27:58 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727391AbeIUQQI (ORCPT ); Fri, 21 Sep 2018 12:16:08 -0400 Received: from mail-wr1-f68.google.com ([209.85.221.68]:42035 "EHLO mail-wr1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389559AbeIUQQI (ORCPT ); Fri, 21 Sep 2018 12:16:08 -0400 Received: by mail-wr1-f68.google.com with SMTP id v17-v6so12318052wrr.9 for ; Fri, 21 Sep 2018 03:27:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pU1UdwqX3pzFP/4HBGNwbB0dkyzur8ElohRzRFhApkU=; b=gCMC8KgfTIpJIgfmbXB6kAB4khux15f4acdPjDmEE3wyRA2Va7kdgTZUVGFpMpT/M+ lmc/29kOFBzhS1YNPwaK2SKlCHcTBJD+LLYrQXK7HQHwEmLAMG6o/ya4LphK/SqvLgbr YI5RiSqBsgaek088BByjwS1ann1Fyq+NqAc3V5XQJtuDzJXAeisBxWqq3CBA9u/qhYb8 byeed/O812Xu4wpVMUr+uhELUPa8mFEEAMWLkUA7RTCKXEaG5e590H4KhLgfADKTbMEO pkSvQ1OOYTqwL5pL0vM4Q9K16VzP/R0MGoxsrsTOlx45ioPbSDY/BxzNLmq+XOxnVWxO 7CsA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pU1UdwqX3pzFP/4HBGNwbB0dkyzur8ElohRzRFhApkU=; b=Wc+4tRhHfEdxJR7QU/BTdbk1j1J+IuMhZG5/Uzm2cHnPuyHskCGLvKUW6FqYP678X1 X0CX1gqWE3Cwy1SZ4rSCrw5llxFaf/FQL0qIX1+BQgD96Q0WYjioWgpUaXtMrpRtR3oR OIneojNre6XOP376g4ZG3bN63bIyRQVCEIWnsUMjZlhB1B7pBMYsomt/hNIcPaAb6apf Rq6Li4N0LPQzZQDZkk46pZjo6ku0fJNRzBvRtjUuHYhOxvopmK0ayEQMt0epXhFVpF9d H1tAPCCQ05vN+6RoKp6yjyfztWGzRw1ITa1egWpKNoceiy4lYUTj7WWqd/K3gWcVUcd5 Mf/w== X-Gm-Message-State: APzg51BO+Ddha4Rg20G1QFZ5KMUKFuefV+qmsSZVhM/Uk+dTLLdELISe 9hC+4nQkDFzhhVs41GHodcU= X-Google-Smtp-Source: ANB0VdZz259ZpwfLjvpiPOq7qrcHZHP/KTgGqV36Ic7E1ShVPQmZz/RRc9e7qczaCB4prCZ8mmnpQQ== X-Received: by 2002:adf:c554:: with SMTP id s20-v6mr35485292wrf.46.1537525673151; Fri, 21 Sep 2018 03:27:53 -0700 (PDT) Received: from localhost (pD9E515A3.dip0.t-ipconnect.de. [217.229.21.163]) by smtp.gmail.com with ESMTPSA id x16-v6sm19870883wro.84.2018.09.21.03.27.52 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 21 Sep 2018 03:27:52 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: dri-devel@lists.freedesktop.org, linux-tegra@vger.kernel.org Subject: [PATCH 5/5] drm/tegra: sor: Add Tegra194 support Date: Fri, 21 Sep 2018 12:27:46 +0200 Message-Id: <20180921102746.13095-5-thierry.reding@gmail.com> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20180921102746.13095-1-thierry.reding@gmail.com> References: <20180921102746.13095-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The SOR implemented in Tegra194 is subtly different from its predecessor found in Tegra186. Most notably some registers have been moved around so it is no longer compatible. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/drm.c | 1 + drivers/gpu/drm/tegra/sor.c | 110 ++++++++++++++++++++++++++++++++++++ 2 files changed, 111 insertions(+) diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c index 395b048447b2..67a7cffe89fc 100644 --- a/drivers/gpu/drm/tegra/drm.c +++ b/drivers/gpu/drm/tegra/drm.c @@ -1277,6 +1277,7 @@ static const struct of_device_id host1x_drm_subdevs[] = { { .compatible = "nvidia,tegra186-vic", }, { .compatible = "nvidia,tegra194-display", }, { .compatible = "nvidia,tegra194-dc", }, + { .compatible = "nvidia,tegra194-sor", }, { /* sentinel */ } }; diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c index d7fe9f15def1..b129da2e5afd 100644 --- a/drivers/gpu/drm/tegra/sor.c +++ b/drivers/gpu/drm/tegra/sor.c @@ -282,6 +282,85 @@ static const struct tegra_sor_hdmi_settings tegra186_sor_hdmi_defaults[] = { } }; +static const struct tegra_sor_hdmi_settings tegra194_sor_hdmi_defaults[] = { + { + .frequency = 54000000, + .vcocap = 0, + .filter = 5, + .ichpmp = 5, + .loadadj = 3, + .tmds_termadj = 0xf, + .tx_pu_value = 0, + .bg_temp_coef = 3, + .bg_vref_level = 8, + .avdd10_level = 4, + .avdd14_level = 4, + .sparepll = 0x54, + .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 }, + .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, + }, { + .frequency = 75000000, + .vcocap = 1, + .filter = 5, + .ichpmp = 5, + .loadadj = 3, + .tmds_termadj = 0xf, + .tx_pu_value = 0, + .bg_temp_coef = 3, + .bg_vref_level = 8, + .avdd10_level = 4, + .avdd14_level = 4, + .sparepll = 0x44, + .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 }, + .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, + }, { + .frequency = 150000000, + .vcocap = 3, + .filter = 5, + .ichpmp = 5, + .loadadj = 3, + .tmds_termadj = 15, + .tx_pu_value = 0x66 /* 0 */, + .bg_temp_coef = 3, + .bg_vref_level = 8, + .avdd10_level = 4, + .avdd14_level = 4, + .sparepll = 0x00, /* 0x34 */ + .drive_current = { 0x3a, 0x3a, 0x3a, 0x37 }, + .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, + }, { + .frequency = 300000000, + .vcocap = 3, + .filter = 5, + .ichpmp = 5, + .loadadj = 3, + .tmds_termadj = 15, + .tx_pu_value = 64, + .bg_temp_coef = 3, + .bg_vref_level = 8, + .avdd10_level = 4, + .avdd14_level = 4, + .sparepll = 0x34, + .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 }, + .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, + }, { + .frequency = 600000000, + .vcocap = 3, + .filter = 5, + .ichpmp = 5, + .loadadj = 3, + .tmds_termadj = 12, + .tx_pu_value = 96, + .bg_temp_coef = 3, + .bg_vref_level = 8, + .avdd10_level = 4, + .avdd14_level = 4, + .sparepll = 0x34, + .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 }, + .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, + } +}; + struct tegra_sor_regs { unsigned int head_state0; unsigned int head_state1; @@ -2894,7 +2973,38 @@ static const struct tegra_sor_soc tegra186_sor1 = { .xbar_cfg = tegra124_sor_xbar_cfg, }; +static const struct tegra_sor_regs tegra194_sor_regs = { + .head_state0 = 0x151, + .head_state1 = 0x155, + .head_state2 = 0x159, + .head_state3 = 0x15d, + .head_state4 = 0x161, + .head_state5 = 0x165, + .pll0 = 0x169, + .pll1 = 0x16a, + .pll2 = 0x16b, + .pll3 = 0x16c, + .dp_padctl0 = 0x16e, + .dp_padctl2 = 0x16f, +}; + +static const struct tegra_sor_soc tegra194_sor = { + .supports_edp = true, + .supports_lvds = false, + .supports_hdmi = true, + .supports_dp = true, + + .regs = &tegra194_sor_regs, + .has_nvdisplay = true, + + .num_settings = ARRAY_SIZE(tegra194_sor_hdmi_defaults), + .settings = tegra194_sor_hdmi_defaults, + + .xbar_cfg = tegra210_sor_xbar_cfg, +}; + static const struct of_device_id tegra_sor_of_match[] = { + { .compatible = "nvidia,tegra194-sor", .data = &tegra194_sor }, { .compatible = "nvidia,tegra186-sor1", .data = &tegra186_sor1 }, { .compatible = "nvidia,tegra186-sor", .data = &tegra186_sor }, { .compatible = "nvidia,tegra210-sor1", .data = &tegra210_sor1 },