From patchwork Fri Sep 21 10:25:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 973098 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="r4q6L4UA"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42GqXK1DVNz9sCD for ; Fri, 21 Sep 2018 20:26:57 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390337AbeIUQOF (ORCPT ); Fri, 21 Sep 2018 12:14:05 -0400 Received: from mail-wr1-f66.google.com ([209.85.221.66]:39545 "EHLO mail-wr1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389264AbeIUQOE (ORCPT ); Fri, 21 Sep 2018 12:14:04 -0400 Received: by mail-wr1-f66.google.com with SMTP id s14-v6so12312869wrw.6; Fri, 21 Sep 2018 03:25:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=TqMEwFyf4ZquG+hsptIWBhDxrXZUsJ1QshY0+jeRlTs=; b=r4q6L4UAVTMoK2ERprIkcNWzc4/0KqTOFEZvr+NPV0vKJ5kdPAV92sYMY8K6zwyfaM Vu0GgNChLOt9NLrg8xuuzngh3Gt4/XaOIxrCHC7kQ9ctqpgcZuqPja8/PIciYnkh1pBw 98xWEBXKzwX6jFcSJkjR1X0OwA9f1JXVQzz+DpuguHWYZtatBjC6cyFi6JfvnwTdZTzd j5rtxMIy5rBODGNozk0Hy3h8n2OjWQNlnaXmp1ECeYoHjKE9T3rbzWuAriwdX1rniyFe qW/LRBercTZ+H7SyE7HcdM2l/1hH4d04hEyB19O3QcFr5ntnuStRqiTrnyNmCwR/cjm2 lACw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TqMEwFyf4ZquG+hsptIWBhDxrXZUsJ1QshY0+jeRlTs=; b=Nskbp4KV4DaQPZtGOLD45EN/WIHYuwuyuyyWtqL6pc55xt2sSZzOYJFwiDgRyli3tu SfzDp0JT2XwPavBxDsDOuUo+fUwlIMYfWqM2MFD/OYAPCWDsrkSVy/FQsO0r4uMtYoke iUv888SBT4VEbHcbmIvJ8ss+WgAhiYrwNllCSBc45hr2T4fYcEMKxjDJ37mZqYrmTYRH izuqVNfbwM1tvE4gDHSUapd7t2Om01kjnrVkszT0tQVEFX0FPgaz4RanybW8aHFcZVY0 Ro4v1HmMoQgLwBbUuZRf073DR1P0cPcjVoqpZKjBYNqNzWrdATrQHlIxvCJWfXQ+2TIJ ckog== X-Gm-Message-State: APzg51AEvun/x3BqM0JBhZCsD1tGVU55KcXZdMyl/CtmzyftM2M/hB+H R0paejCYIZ+ihEqfZp2cigE= X-Google-Smtp-Source: ANB0VdYesVJtYnC4uh/aFTCTBIGLrHzLUjWJ7LVm8+nC4THhGRtNJ4nEjovV0fzupudGiy2+XTEB7Q== X-Received: by 2002:adf:ea92:: with SMTP id s18-v6mr36031329wrm.284.1537525550020; Fri, 21 Sep 2018 03:25:50 -0700 (PDT) Received: from localhost (pD9E515A3.dip0.t-ipconnect.de. [217.229.21.163]) by smtp.gmail.com with ESMTPSA id d22-v6sm45651320wra.80.2018.09.21.03.25.49 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 21 Sep 2018 03:25:49 -0700 (PDT) From: Thierry Reding To: Linus Walleij , Thierry Reding Cc: Thomas Gleixner , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/9] dt-bindings: tegra186-pmc: Add interrupt controller properties Date: Fri, 21 Sep 2018 12:25:38 +0200 Message-Id: <20180921102546.12745-2-thierry.reding@gmail.com> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20180921102546.12745-1-thierry.reding@gmail.com> References: <20180921102546.12745-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The PMC can be a top-level interrupt controller that provides the top- level controls for wake events. Add optional properties to mark the PMC as interrupt controller. Signed-off-by: Thierry Reding Reviewed-by: Rob Herring --- .../devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt index c9fd6d1de57e..2d89cdc39eb0 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt @@ -15,6 +15,9 @@ Required properties: Optional properties: - nvidia,invert-interrupt: If present, inverts the PMU interrupt signal. +- interrupt-controller: Identifies the node as an interrupt controller. +- #interrupt-cells: Specifies the number of cells needed to encode an + interrupt source. The value must be 2. Example: From patchwork Fri Sep 21 10:25:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 973097 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="kk6IfjVZ"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42GqXH3jwcz9sDF for ; Fri, 21 Sep 2018 20:26:55 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390350AbeIUQOH (ORCPT ); Fri, 21 Sep 2018 12:14:07 -0400 Received: from mail-wm1-f68.google.com ([209.85.128.68]:50825 "EHLO mail-wm1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725898AbeIUQOG (ORCPT ); Fri, 21 Sep 2018 12:14:06 -0400 Received: by mail-wm1-f68.google.com with SMTP id s12-v6so2523108wmc.0; Fri, 21 Sep 2018 03:25:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BmRuSD8EMihenFkLdU/jKTXF74csBfSkzLsp6aRLNdw=; b=kk6IfjVZl2lGG5hDD3r2ISCb72ubwB1aR4N/g3XOPC8qwwKWGv7tGyZyfnP96E27qj fGqYMYyRCoMKLgrOg9bLhtYg+BdR4dYGD6zxffJYFV91VeS8wyIGGrgPvHkBole/0Y5b oxz4XY4tZxrwJT6gWVeOqM2tCwqXnTAlp//Jo3f2R1BCBRR/IVyCgDiw6L6a9Eyk5ktH GbSSwRlTEtwrtIj7ctEYbqI0kcosxiVmVRfONSi2dqhnECf5krv9AqN3itEptI/DU+o+ y2tl95YU8gZqlacsF95Kxq0YNTm1E5WhyOfCrvEluKNpwPdg6I51hxMBYS/q6V3lF6tR YZvw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BmRuSD8EMihenFkLdU/jKTXF74csBfSkzLsp6aRLNdw=; b=oamH4mWB+Y5BQ5AL49WxasaODBrBZPbFZ4IZ55QC7BqtRM8PeGkyeMt/CNstrcbgsH V7jlqkqIUhabBQonGYMKKtl7B7AEajO2Z/i0Ui/V+f8tn75+LXY+Nbb8okUbtwPIT+1L EyKrsUAGUXfIDdJkv9uXSd4LTi5jBC85Gjp3Cl8M3S/3rACDS2t6bNe+pa+NHhBRBppi AfXptGjYC9wBjlMMI5tpteJtHOcy7aKV2iJlGKsZVdjfzm1YKFxwGR4t4TMeu0eRowqs 7Xl0EDjoUbfuaUGaKTlm+tvgVifTEna0/1dLHquI31EfNGxjxXk9kFzJslkZiMn7lHF+ 8qEA== X-Gm-Message-State: APzg51D3yhfn990Q5md8gOmej0bHpGYP8TZUh30mWT65JB+IepkcGN0T Oyz1Ybk8+ow/uZJoyxjUVvU= X-Google-Smtp-Source: ANB0VdYFvFzSfI/FwLZ7Yb64x8VMRjk3xh825kVd0iNUKPAv5FJPDeTUdyExrjLrLCzO4IQQQl/LxA== X-Received: by 2002:a7b:c248:: with SMTP id b8-v6mr6843361wmj.21.1537525551434; Fri, 21 Sep 2018 03:25:51 -0700 (PDT) Received: from localhost (pD9E515A3.dip0.t-ipconnect.de. [217.229.21.163]) by smtp.gmail.com with ESMTPSA id h18-v6sm38600387wru.42.2018.09.21.03.25.50 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 21 Sep 2018 03:25:50 -0700 (PDT) From: Thierry Reding To: Linus Walleij , Thierry Reding Cc: Thomas Gleixner , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/9] soc/tegra: pmc: Add Tegra194 support Date: Fri, 21 Sep 2018 12:25:39 +0200 Message-Id: <20180921102546.12745-3-thierry.reding@gmail.com> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20180921102546.12745-1-thierry.reding@gmail.com> References: <20180921102546.12745-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The PMC controller on Tegra194 has a couple of new I/O pads and drops others compared to Tegra186. Signed-off-by: Thierry Reding --- drivers/soc/tegra/pmc.c | 66 ++++++++++++++++++++++++++++++++++++++++- include/soc/tegra/pmc.h | 21 +++++++++++++ 2 files changed, 86 insertions(+), 1 deletion(-) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index ab719fa90150..c08f0b942020 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -2138,8 +2138,72 @@ static const struct tegra_pmc_soc tegra186_pmc_soc = { .setup_irq_polarity = tegra186_pmc_setup_irq_polarity, }; +static const struct tegra_io_pad_soc tegra194_io_pads[] = { + { .id = TEGRA_IO_PAD_CSIA, .dpd = 0, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_CSIB, .dpd = 1, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_MIPI_BIAS, .dpd = 3, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_PEX_CLK_BIAS, .dpd = 4, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_PEX_CLK3, .dpd = 5, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_PEX_CLK2, .dpd = 6, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_PEX_CLK1, .dpd = 7, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_EQOS, .dpd = 8, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_PEX_CLK2_BIAS, .dpd = 9, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_PEX_CLK2, .dpd = 10, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_DAP3, .dpd = 11, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_DAP5, .dpd = 12, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_UART, .dpd = 14, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_PWR_CTL, .dpd = 15, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_SOC_GPIO53, .dpd = 16, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_AUDIO, .dpd = 17, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_GP_PWM2, .dpd = 18, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_GP_PWM3, .dpd = 19, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_SOC_GPIO12, .dpd = 20, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_SOC_GPIO13, .dpd = 21, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_SOC_GPIO10, .dpd = 22, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_UART4, .dpd = 23, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_UART5, .dpd = 24, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_DBG, .dpd = 25, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_HDMI_DP3, .dpd = 26, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_HDMI_DP2, .dpd = 27, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_HDMI_DP0, .dpd = 28, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_HDMI_DP1, .dpd = 29, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_PEX_CNTRL, .dpd = 32, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_PEX_CTL2, .dpd = 33, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_PEX_L0_RST_N, .dpd = 34, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_PEX_L1_RST_N, .dpd = 35, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_SDMMC4, .dpd = 36, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_PEX_L5_RST_N, .dpd = 37, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_CSIC, .dpd = 43, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_CSID, .dpd = 44, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_CSIE, .dpd = 45, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_CSIF, .dpd = 46, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_SPI, .dpd = 47, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_UFS, .dpd = 49, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_CSIG, .dpd = 50, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_CSIH, .dpd = 51, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_EDP, .dpd = 53, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_SDMMC1_HV, .dpd = 55, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_SDMMC3_HV, .dpd = 56, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_CONN, .dpd = 60, .voltage = UINT_MAX }, + { .id = TEGRA_IO_PAD_AUDIO_HV, .dpd = 61, .voltage = UINT_MAX }, +}; + +static const struct tegra_pmc_soc tegra194_pmc_soc = { + .num_powergates = 0, + .powergates = NULL, + .num_cpu_powergates = 0, + .cpu_powergates = NULL, + .has_tsense_reset = false, + .has_gpu_clamps = false, + .num_io_pads = ARRAY_SIZE(tegra194_io_pads), + .io_pads = tegra194_io_pads, + .regs = &tegra186_pmc_regs, + .init = NULL, + .setup_irq_polarity = tegra186_pmc_setup_irq_polarity, +}; + static const struct of_device_id tegra_pmc_match[] = { - { .compatible = "nvidia,tegra194-pmc", .data = &tegra186_pmc_soc }, + { .compatible = "nvidia,tegra194-pmc", .data = &tegra194_pmc_soc }, { .compatible = "nvidia,tegra186-pmc", .data = &tegra186_pmc_soc }, { .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc }, { .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc }, diff --git a/include/soc/tegra/pmc.h b/include/soc/tegra/pmc.h index 562426812ab2..fd816f6aa9cc 100644 --- a/include/soc/tegra/pmc.h +++ b/include/soc/tegra/pmc.h @@ -90,6 +90,10 @@ enum tegra_io_pad { TEGRA_IO_PAD_CSID, TEGRA_IO_PAD_CSIE, TEGRA_IO_PAD_CSIF, + TEGRA_IO_PAD_CSIG, + TEGRA_IO_PAD_CSIH, + TEGRA_IO_PAD_DAP3, + TEGRA_IO_PAD_DAP5, TEGRA_IO_PAD_DBG, TEGRA_IO_PAD_DEBUG_NONAO, TEGRA_IO_PAD_DMIC, @@ -102,10 +106,15 @@ enum tegra_io_pad { TEGRA_IO_PAD_EDP, TEGRA_IO_PAD_EMMC, TEGRA_IO_PAD_EMMC2, + TEGRA_IO_PAD_EQOS, TEGRA_IO_PAD_GPIO, + TEGRA_IO_PAD_GP_PWM2, + TEGRA_IO_PAD_GP_PWM3, TEGRA_IO_PAD_HDMI, TEGRA_IO_PAD_HDMI_DP0, TEGRA_IO_PAD_HDMI_DP1, + TEGRA_IO_PAD_HDMI_DP2, + TEGRA_IO_PAD_HDMI_DP3, TEGRA_IO_PAD_HSIC, TEGRA_IO_PAD_HV, TEGRA_IO_PAD_LVDS, @@ -115,8 +124,14 @@ enum tegra_io_pad { TEGRA_IO_PAD_PEX_CLK_BIAS, TEGRA_IO_PAD_PEX_CLK1, TEGRA_IO_PAD_PEX_CLK2, + TEGRA_IO_PAD_PEX_CLK2_BIAS, TEGRA_IO_PAD_PEX_CLK3, TEGRA_IO_PAD_PEX_CNTRL, + TEGRA_IO_PAD_PEX_CTL2, + TEGRA_IO_PAD_PEX_L0_RST_N, + TEGRA_IO_PAD_PEX_L1_RST_N, + TEGRA_IO_PAD_PEX_L5_RST_N, + TEGRA_IO_PAD_PWR_CTL, TEGRA_IO_PAD_SDMMC1, TEGRA_IO_PAD_SDMMC1_HV, TEGRA_IO_PAD_SDMMC2, @@ -124,10 +139,16 @@ enum tegra_io_pad { TEGRA_IO_PAD_SDMMC3, TEGRA_IO_PAD_SDMMC3_HV, TEGRA_IO_PAD_SDMMC4, + TEGRA_IO_PAD_SOC_GPIO10, + TEGRA_IO_PAD_SOC_GPIO12, + TEGRA_IO_PAD_SOC_GPIO13, + TEGRA_IO_PAD_SOC_GPIO53, TEGRA_IO_PAD_SPI, TEGRA_IO_PAD_SPI_HV, TEGRA_IO_PAD_SYS_DDC, TEGRA_IO_PAD_UART, + TEGRA_IO_PAD_UART4, + TEGRA_IO_PAD_UART5, TEGRA_IO_PAD_UFS, TEGRA_IO_PAD_USB0, TEGRA_IO_PAD_USB1, From patchwork Fri Sep 21 10:25:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 973096 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="iqjKw20O"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42GqX90pQSz9sCD for ; Fri, 21 Sep 2018 20:26:49 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725898AbeIUQOI (ORCPT ); Fri, 21 Sep 2018 12:14:08 -0400 Received: from mail-wm1-f65.google.com ([209.85.128.65]:40539 "EHLO mail-wm1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389264AbeIUQOI (ORCPT ); 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[217.229.21.163]) by smtp.gmail.com with ESMTPSA id 60-v6sm31243592wre.82.2018.09.21.03.25.52 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 21 Sep 2018 03:25:52 -0700 (PDT) From: Thierry Reding To: Linus Walleij , Thierry Reding Cc: Thomas Gleixner , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/9] soc/tegra: pmc: Add wake event support Date: Fri, 21 Sep 2018 12:25:40 +0200 Message-Id: <20180921102546.12745-4-thierry.reding@gmail.com> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20180921102546.12745-1-thierry.reding@gmail.com> References: <20180921102546.12745-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The power management controller has top-level controls that allow certain interrupts (such as from the RTC or a subset of GPIOs) to wake the system from sleep. Implement infrastructure to support these wake events. Signed-off-by: Thierry Reding --- drivers/soc/tegra/pmc.c | 230 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 230 insertions(+) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index c08f0b942020..eeef5a1f2837 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -29,9 +29,12 @@ #include #include #include +#include +#include #include #include #include +#include #include #include #include @@ -48,6 +51,7 @@ #include #include +#include #include #define PMC_CNTRL 0x0 @@ -126,6 +130,18 @@ #define GPU_RG_CNTRL 0x2d4 /* Tegra186 and later */ +#define WAKE_AOWAKE_CNTRL(x) (0x000 + ((x) << 2)) +#define WAKE_AOWAKE_CNTRL_LEVEL (1 << 3) +#define WAKE_AOWAKE_MASK_W(x) (0x180 + ((x) << 2)) +#define WAKE_AOWAKE_MASK_R(x) (0x300 + ((x) << 2)) +#define WAKE_AOWAKE_STATUS_W(x) (0x30c + ((x) << 2)) +#define WAKE_AOWAKE_STATUS_R(x) (0x48c + ((x) << 2)) +#define WAKE_AOWAKE_TIER1_CTRL 0x4ac +#define WAKE_AOWAKE_TIER2_CTRL 0x4b0 +#define WAKE_AOWAKE_TIER0_ROUTING(x) (0x4b4 + ((x) << 2)) +#define WAKE_AOWAKE_TIER1_ROUTING(x) (0x4c0 + ((x) << 2)) +#define WAKE_AOWAKE_TIER2_ROUTING(x) (0x4cc + ((x) << 2)) + #define WAKE_AOWAKE_CTRL 0x4f4 #define WAKE_AOWAKE_CTRL_INTR_POLARITY BIT(0) @@ -153,6 +169,38 @@ struct tegra_pmc_regs { unsigned int dpd2_status; }; +struct tegra_wake_event { + const char *name; + unsigned int id; + unsigned int irq; + struct { + unsigned int instance; + unsigned int pin; + } gpio; +}; + +#define TEGRA_WAKE_IRQ(_name, _id, _irq) \ + { \ + .name = _name, \ + .id = _id, \ + .irq = _irq, \ + .gpio = { \ + .instance = UINT_MAX, \ + .pin = UINT_MAX, \ + }, \ + } + +#define TEGRA_WAKE_GPIO(_name, _id, _instance, _pin) \ + { \ + .name = _name, \ + .id = _id, \ + .irq = 0, \ + .gpio = { \ + .instance = _instance, \ + .pin = _pin, \ + }, \ + } + struct tegra_pmc_soc { unsigned int num_powergates; const char *const *powergates; @@ -175,6 +223,9 @@ struct tegra_pmc_soc { void (*setup_irq_polarity)(struct tegra_pmc *pmc, struct device_node *np, bool invert); + + const struct tegra_wake_event *wake_events; + unsigned int num_wake_events; }; /** @@ -230,6 +281,9 @@ struct tegra_pmc { struct mutex powergates_lock; struct pinctrl_dev *pctl_dev; + + struct irq_domain *domain; + struct irq_chip irq; }; static struct tegra_pmc *pmc = &(struct tegra_pmc) { @@ -1543,6 +1597,178 @@ static int tegra_pmc_pinctrl_init(struct tegra_pmc *pmc) return err; } +static int tegra_pmc_irq_translate(struct irq_domain *domain, + struct irq_fwspec *fwspec, + unsigned long *hwirq, + unsigned int *type) +{ + if (WARN_ON(fwspec->param_count < 2)) + return -EINVAL; + + *hwirq = fwspec->param[0]; + *type = fwspec->param[1]; + + return 0; +} + +static int tegra_pmc_irq_alloc(struct irq_domain *domain, unsigned int virq, + unsigned int num_irqs, void *data) +{ + struct tegra_pmc *pmc = domain->host_data; + struct irq_fwspec *fwspec = data; + unsigned int i; + int err = 0; + + for (i = 0; i < pmc->soc->num_wake_events; i++) { + const struct tegra_wake_event *event = &pmc->soc->wake_events[i]; + + if (fwspec->param_count == 2) { + struct irq_fwspec spec; + + if (event->id != fwspec->param[0]) + continue; + + err = irq_domain_set_hwirq_and_chip(domain, virq, + event->id, + &pmc->irq, pmc); + if (err < 0) + break; + + spec.fwnode = &pmc->dev->of_node->fwnode; + spec.param_count = 3; + spec.param[0] = GIC_SPI; + spec.param[1] = event->irq; + spec.param[2] = fwspec->param[1]; + + err = irq_domain_alloc_irqs_parent(domain, virq, + num_irqs, &spec); + + break; + } + + if (fwspec->param_count == 3) { + if (event->gpio.instance != fwspec->param[0] || + event->gpio.pin != fwspec->param[1]) + continue; + + err = irq_domain_set_hwirq_and_chip(domain, virq, + event->id, + &pmc->irq, pmc); + + break; + } + } + + if (i == pmc->soc->num_wake_events) + err = irq_domain_set_hwirq_and_chip(domain, virq, ULONG_MAX, + &pmc->irq, pmc); + + return err; +} + +static const struct irq_domain_ops tegra_pmc_irq_domain_ops = { + .translate = tegra_pmc_irq_translate, + .alloc = tegra_pmc_irq_alloc, +}; + +static int tegra_pmc_irq_set_wake(struct irq_data *data, unsigned int on) +{ + struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); + unsigned int offset, bit; + u32 value; + + offset = data->hwirq / 32; + bit = data->hwirq % 32; + + /* clear wake status */ + writel(0x1, pmc->wake + WAKE_AOWAKE_STATUS_W(data->hwirq)); + + /* route wake to tier 2 (XXX conditionally enable this) */ + value = readl(pmc->wake + WAKE_AOWAKE_TIER2_CTRL); + writel(0x1, pmc->wake + WAKE_AOWAKE_TIER2_CTRL); + + value = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset)); + + if (!on) + value &= ~(1 << bit); + else + value |= 1 << bit; + + writel(value, pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset)); + + /* enable wakeup event */ + writel(!!on, pmc->wake + WAKE_AOWAKE_MASK_W(data->hwirq)); + + return 0; +} + +static int tegra_pmc_irq_set_type(struct irq_data *data, unsigned int type) +{ + struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); + u32 value; + + if (data->hwirq == ULONG_MAX) + return 0; + + value = readl(pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq)); + + switch (type) { + case IRQ_TYPE_EDGE_RISING: + case IRQ_TYPE_LEVEL_HIGH: + value |= WAKE_AOWAKE_CNTRL_LEVEL; + break; + + case IRQ_TYPE_EDGE_FALLING: + case IRQ_TYPE_LEVEL_LOW: + value &= ~WAKE_AOWAKE_CNTRL_LEVEL; + break; + + case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING: + value ^= WAKE_AOWAKE_CNTRL_LEVEL; + break; + + default: + return -EINVAL; + } + + writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq)); + + return 0; +} + +static int tegra_pmc_irq_init(struct tegra_pmc *pmc) +{ + struct irq_domain *parent = NULL; + struct device_node *np; + + np = of_irq_find_parent(pmc->dev->of_node); + if (np) { + parent = irq_find_host(np); + of_node_put(np); + } + + if (parent) { + pmc->irq.name = dev_name(pmc->dev); + pmc->irq.irq_mask = irq_chip_mask_parent; + pmc->irq.irq_unmask = irq_chip_unmask_parent; + pmc->irq.irq_eoi = irq_chip_eoi_parent; + pmc->irq.irq_set_affinity = irq_chip_set_affinity_parent; + pmc->irq.irq_set_type = tegra_pmc_irq_set_type; + pmc->irq.irq_set_wake = tegra_pmc_irq_set_wake; + + pmc->domain = irq_domain_add_hierarchy(parent, 0, 96, + pmc->dev->of_node, + &tegra_pmc_irq_domain_ops, + pmc); + if (!pmc->domain) { + dev_err(pmc->dev, "failed to allocate domain\n"); + return -ENOMEM; + } + } + + return 0; +} + static int tegra_pmc_probe(struct platform_device *pdev) { void __iomem *base; @@ -1629,6 +1855,10 @@ static int tegra_pmc_probe(struct platform_device *pdev) if (err) goto cleanup_restart_handler; + err = tegra_pmc_irq_init(pmc); + if (err < 0) + goto cleanup_restart_handler; + mutex_lock(&pmc->powergates_lock); iounmap(pmc->base); pmc->base = base; From patchwork Fri Sep 21 10:25:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 973095 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="bPtt6AzT"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42GqX22TNDz9sCh for ; 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[217.229.21.163]) by smtp.gmail.com with ESMTPSA id h17-v6sm23242580wrq.73.2018.09.21.03.25.54 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 21 Sep 2018 03:25:54 -0700 (PDT) From: Thierry Reding To: Linus Walleij , Thierry Reding Cc: Thomas Gleixner , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/9] soc/tegra: pmc: Add initial Tegra186 wake events Date: Fri, 21 Sep 2018 12:25:41 +0200 Message-Id: <20180921102546.12745-5-thierry.reding@gmail.com> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20180921102546.12745-1-thierry.reding@gmail.com> References: <20180921102546.12745-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding Tegra186 support 96 wake events in total. Many of them are never used, so only the most common ones (RTC alarm and power key) are currently defined. Signed-off-by: Thierry Reding --- drivers/soc/tegra/pmc.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index eeef5a1f2837..42e7deb6de74 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -53,6 +53,7 @@ #include #include +#include #define PMC_CNTRL 0x0 #define PMC_CNTRL_INTR_POLARITY BIT(17) /* inverts INTR polarity */ @@ -2351,6 +2352,11 @@ static void tegra186_pmc_setup_irq_polarity(struct tegra_pmc *pmc, iounmap(wake); } +static const struct tegra_wake_event tegra186_wake_events[] = { + TEGRA_WAKE_GPIO("power", 29, 1, TEGRA_AON_GPIO(FF, 0)), + TEGRA_WAKE_IRQ("rtc", 73, 10), +}; + static const struct tegra_pmc_soc tegra186_pmc_soc = { .num_powergates = 0, .powergates = NULL, @@ -2366,6 +2372,8 @@ static const struct tegra_pmc_soc tegra186_pmc_soc = { .regs = &tegra186_pmc_regs, .init = NULL, .setup_irq_polarity = tegra186_pmc_setup_irq_polarity, + .num_wake_events = ARRAY_SIZE(tegra186_wake_events), + .wake_events = tegra186_wake_events, }; static const struct tegra_io_pad_soc tegra194_io_pads[] = { From patchwork Fri Sep 21 10:25:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 973092 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="VmUlyyQr"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42GqWy4bThz9sCq for ; Fri, 21 Sep 2018 20:26:38 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390397AbeIUQOL (ORCPT ); Fri, 21 Sep 2018 12:14:11 -0400 Received: from mail-wm1-f68.google.com ([209.85.128.68]:36879 "EHLO mail-wm1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389264AbeIUQOK (ORCPT ); Fri, 21 Sep 2018 12:14:10 -0400 Received: by mail-wm1-f68.google.com with SMTP id n11-v6so2656559wmc.2; Fri, 21 Sep 2018 03:25:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=uXDglkcuPDUbyoePYORwBZvkypgLOk81MMzqBdKmW/s=; b=VmUlyyQr30Bb/FaqfVKJsQlHGPGjTGfkG+HU4H7SUB3z2kNuuQM2snYubuzZFI/7iq vq+wSwLehv6H7+3ovlIOCYROSAH4KLKyyXfqpTsBdA/TQ7aQaFmZqcFv4w3f9QKMOuUK QzVZF78T8DprR5yKn53eMpWvrB4GUPHAkLUfXKsbkLSY8moi1BSrpbQZFIOYO8rSCa0p a9Y34NQRS8v5ZY2nHwQNSBH1b9GfqTiLfoG+V65Q0UhtkpPdFC6ks6tcoKWsl6jImaY7 ht1/Jjqw+7KOinvzCvQIQGmkzieo0x9751ZxUmHcFr/VjfrO1PxCNUw8g+McYqVIqaa+ iCdA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uXDglkcuPDUbyoePYORwBZvkypgLOk81MMzqBdKmW/s=; b=Zxsg3zTW9fMI+O3fx/6b01gzorarEY/NDicQlvPgDvMJq2AKTNnyr4Gmtn1crhF1pI iggmn3oyRDXF6VVROkwMR2aP54SUPDFpdUlm+KMtZFzrOh44Xi6vPVqeHHfxb1ddm3JH NKzAPtY5IUS0tzzX2N0YC1SbvSAf1/ImoxyD7qUfE6RPHjv80qLYqPEtg4omqPSyhfWx lRbNevnX2LVzh2bqob2YRI+Q5MWnhwFORXxi1TIk9VpTTqCLjtheRG8iUzQaErn7BnOB KXjCZ0agayAoGoItCSC0m1yv3UnJVhBjX6P00+9dPTs8IxLQ6jm37Ve8yjQuC/I10zP6 hiMA== X-Gm-Message-State: APzg51AXkuvAw2716PR7MlxPAC2EEbV7fL0S9Ve5DHcmflytoqbMLRnI dAN3OvRWUVXQw9BUJuIRihD2rd5N X-Google-Smtp-Source: ANB0VdaumczRe8fKODXGLICAr3wVqz8H8QmJ1OppqbQfy9Qj57RGGjPnV3hJUqBgE04xFJW3s49Scg== X-Received: by 2002:a1c:4c0c:: with SMTP id z12-v6mr6339941wmf.57.1537525556144; Fri, 21 Sep 2018 03:25:56 -0700 (PDT) Received: from localhost (pD9E515A3.dip0.t-ipconnect.de. [217.229.21.163]) by smtp.gmail.com with ESMTPSA id j44-v6sm45674947wre.40.2018.09.21.03.25.55 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 21 Sep 2018 03:25:55 -0700 (PDT) From: Thierry Reding To: Linus Walleij , Thierry Reding Cc: Thomas Gleixner , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 5/9] soc/tegra: pmc: Add initial Tegra194 wake events Date: Fri, 21 Sep 2018 12:25:42 +0200 Message-Id: <20180921102546.12745-6-thierry.reding@gmail.com> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20180921102546.12745-1-thierry.reding@gmail.com> References: <20180921102546.12745-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding Tegra194 supports 96 wake events in total. Many of them are never used, so only the most common ones (RTC alarm and power key) are currently defined. Signed-off-by: Thierry Reding --- drivers/soc/tegra/pmc.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index 42e7deb6de74..efe990985fe6 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -54,6 +54,7 @@ #include #include #include +#include #define PMC_CNTRL 0x0 #define PMC_CNTRL_INTR_POLARITY BIT(17) /* inverts INTR polarity */ @@ -2426,6 +2427,11 @@ static const struct tegra_io_pad_soc tegra194_io_pads[] = { { .id = TEGRA_IO_PAD_AUDIO_HV, .dpd = 61, .voltage = UINT_MAX }, }; +static const struct tegra_wake_event tegra194_wake_events[] = { + TEGRA_WAKE_GPIO("power", 29, 1, TEGRA194_AON_GPIO(EE, 4)), + TEGRA_WAKE_IRQ("rtc", 73, 10), +}; + static const struct tegra_pmc_soc tegra194_pmc_soc = { .num_powergates = 0, .powergates = NULL, @@ -2438,6 +2444,8 @@ static const struct tegra_pmc_soc tegra194_pmc_soc = { .regs = &tegra186_pmc_regs, .init = NULL, .setup_irq_polarity = tegra186_pmc_setup_irq_polarity, + .num_wake_events = ARRAY_SIZE(tegra194_wake_events), + .wake_events = tegra194_wake_events, }; static const struct of_device_id tegra_pmc_match[] = { From patchwork Fri Sep 21 10:25:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 973090 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="KAGNz1Jo"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42GqWr458yz9sCc for ; Fri, 21 Sep 2018 20:26:32 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390416AbeIUQON (ORCPT ); Fri, 21 Sep 2018 12:14:13 -0400 Received: from mail-wm1-f68.google.com ([209.85.128.68]:54830 "EHLO mail-wm1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2390390AbeIUQOM (ORCPT ); Fri, 21 Sep 2018 12:14:12 -0400 Received: by mail-wm1-f68.google.com with SMTP id c14-v6so2493696wmb.4; Fri, 21 Sep 2018 03:25:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5uGioRpmWHw5HmBGBMYla/FtUi6hl7emhEwjHohddII=; b=KAGNz1JotYwpwgKedqzNuJSQpZZabk2WAg1RdGTll1ITafzjPx8xL+1RrPkDNc7vNc erhT6L8fB1A+hab7uAtSQDVyV4uMS0hwJ7lQ57CtZBMTw1Txoan1sf0plCFfykWJOqcT 696kgx25ng6ctz/gTrKoQg8iUsI6jWfcxw1dx0+Zq3lnjRJ7pTL4Zo+eD7tqkFemB6Qe cr3XmAsWaWvrI8Fdg2TMYKgYbeyDuia2GwJ98e5A4JvnieD52cLmk4gbyZ5vrFdvTSXc Fa36TdtSbG5Cd81jboptQ90aKTMoEooj77pJRPIWFsBFCSfu55HKMpsYwa/gdi5Al2mh tk8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5uGioRpmWHw5HmBGBMYla/FtUi6hl7emhEwjHohddII=; b=AvNSIESkslfSRTHBzN5Bg6YqAbFcjw1hKS/UKRknHZWaxTo4JB3vygeiRiADTFcKb8 76R2ZQbNjfmsEtPqV6TqHqMjS/z3TZVRhx8SUcZmsJe1tVhoXcaSqzmwr/AQr3Z61ac8 zKzn60o7RWIvduLbhb2Fk85p8c97TGRcUw8G2XY1Fnx+wNXQQJUTbYUrN4WTqqQKjAOb 4WQUwnRwPVMVU2kdSNPfPVEfkiz8kaprktyfBu6qcIoTJe/2bQH/lGFQQfQzLN0JgUg2 zuPjlzKAPx/a3S6W8Moru/vfH0BN98hn0SC3IJ2XDcS1cEu2vPCxzDVAIYJRc5b0Nizz 0pyQ== X-Gm-Message-State: APzg51C447UqGqpC6tKCq2ysLhNbjScn1SFuzY9MWf9MT0+4bd1gP8nV TzKK04zycdA4HGmW2+gIqnE= X-Google-Smtp-Source: ACcGV63EuhjidxUB6Uv8yfATh85hxgoid0pNzlBZ7CyrdBXFrfCjeK9zqiG064Y8JxRKKdxle1vpYw== X-Received: by 2002:a1c:7704:: with SMTP id t4-v6mr6133479wmi.136.1537525557530; Fri, 21 Sep 2018 03:25:57 -0700 (PDT) Received: from localhost (pD9E515A3.dip0.t-ipconnect.de. [217.229.21.163]) by smtp.gmail.com with ESMTPSA id i125-v6sm6341423wmd.23.2018.09.21.03.25.56 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 21 Sep 2018 03:25:57 -0700 (PDT) From: Thierry Reding To: Linus Walleij , Thierry Reding Cc: Thomas Gleixner , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 6/9] gpio: Add support for hierarchical IRQ domains Date: Fri, 21 Sep 2018 12:25:43 +0200 Message-Id: <20180921102546.12745-7-thierry.reding@gmail.com> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20180921102546.12745-1-thierry.reding@gmail.com> References: <20180921102546.12745-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding Hierarchical IRQ domains can be used to stack different IRQ controllers on top of each other. One specific use-case where this can be useful is if a power management controller has top-level controls for wakeup interrupts. In such cases, the power management controller can be a parent to other interrupt controllers and program additional registers when an IRQ has its wake capability enabled or disabled. Signed-off-by: Thierry Reding --- drivers/gpio/gpiolib.c | 15 +++++++++++---- include/linux/gpio/driver.h | 6 ++++++ 2 files changed, 17 insertions(+), 4 deletions(-) diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c index a53d17745d21..94146093ee95 100644 --- a/drivers/gpio/gpiolib.c +++ b/drivers/gpio/gpiolib.c @@ -1918,7 +1918,9 @@ static int gpiochip_add_irqchip(struct gpio_chip *gpiochip, type = IRQ_TYPE_NONE; } - gpiochip->to_irq = gpiochip_to_irq; + if (!gpiochip->to_irq) + gpiochip->to_irq = gpiochip_to_irq; + gpiochip->irq.default_type = type; gpiochip->irq.lock_key = lock_key; gpiochip->irq.request_key = request_key; @@ -1928,9 +1930,14 @@ static int gpiochip_add_irqchip(struct gpio_chip *gpiochip, else ops = &gpiochip_domain_ops; - gpiochip->irq.domain = irq_domain_add_simple(np, gpiochip->ngpio, - gpiochip->irq.first, - ops, gpiochip); + if (gpiochip->irq.parent_domain) + gpiochip->irq.domain = irq_domain_add_hierarchy(gpiochip->irq.parent_domain, + 0, gpiochip->ngpio, + np, ops, gpiochip); + else + gpiochip->irq.domain = irq_domain_add_simple(np, gpiochip->ngpio, + gpiochip->irq.first, + ops, gpiochip); if (!gpiochip->irq.domain) return -EINVAL; diff --git a/include/linux/gpio/driver.h b/include/linux/gpio/driver.h index d8dcd0e44cab..fcd09a396d76 100644 --- a/include/linux/gpio/driver.h +++ b/include/linux/gpio/driver.h @@ -47,6 +47,12 @@ struct gpio_irq_chip { */ const struct irq_domain_ops *domain_ops; + /** + * @parent_domain: + * + */ + struct irq_domain *parent_domain; + /** * @handler: * From patchwork Fri Sep 21 10:25:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 973082 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="nNOuoybd"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42GqWH5QXtz9sD0 for ; Fri, 21 Sep 2018 20:26:03 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389808AbeIUQOO (ORCPT ); Fri, 21 Sep 2018 12:14:14 -0400 Received: from mail-wm1-f68.google.com ([209.85.128.68]:33111 "EHLO mail-wm1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389264AbeIUQON (ORCPT ); Fri, 21 Sep 2018 12:14:13 -0400 Received: by mail-wm1-f68.google.com with SMTP id r1-v6so3806649wmh.0; Fri, 21 Sep 2018 03:25:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Jr2Guj4IS+KaSpQIhd5X6b3SqJiQa+YzNCwuQumn9r0=; b=nNOuoybduFOKNSwFgG9MWSKog5EthQjw2mp59zTfdsNQOC1S5T0lyx10Cfqd3leIMz 3JHxL3LE/OZjkYq5PeHDgdgZOD1s7LuyeB8kGMpZIUiEszoV6itJda8VZ2h8unsFrLbC iC7jAEyE/kCU3PxOD5DqSVZGZUTAo3f4+zT9HFnbHcsdkYmjOEZ70PkL/23OEGQ0Xc3R cwaVOLa79R78+6jbe9p4Cx/mN3Qb82SSO8d4mNOm+620SOMpZo/VhRTnUq/JVGNK4GfL 4CXset+4j+33Nsxy0qrAoMD8uUfKmLxfL0b5HX2GXJbjdkM7+ImnwLi2EnOpTw0J/O0C ilng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Jr2Guj4IS+KaSpQIhd5X6b3SqJiQa+YzNCwuQumn9r0=; b=sTXp/58XqVVmoQr0pTczfGionG0LxYdcAGw7xIk5X573Nj4Noy2oOb0ZBWOKUKU813 A5AiH/VW0B/UH/Bi4xiHtsngJsatxJq3AAm/rXk/9LepJ0Gk+qLXe82ATYIuW0YbzfX4 tyW+Dvy285P5rPaJ80nl1JGZx4V4BdoCCBdVSh9sKlz1PWAYKWoHu69hTqMlLzmupVqS YCnvjaJ1tLZlPukrpbWjpAF6tF9GEGGTPh8IbO7j5PQyRTavMGmhFLjnw1miCRB6IIFH b4qK9WMi3ZKSOnRt7v3X+42nle/TyH+3XF02cZ91Foy+aZavczoO52kNfUlHBACkMcvZ vdsA== X-Gm-Message-State: APzg51A8AyEN914yuFzm9SR1kD3OB7dxuuA3uqNkZxN6C1z95IwTISAQ 5hwRYYqnNWfRNFYFWSWVnak= X-Google-Smtp-Source: ANB0VdYWn21FZZ+t2W1B4ur7HqFpvtJq51al8+6bCWZ0SVlxPMA6qkV6xHxkbANY1CkmtYongBNx0g== X-Received: by 2002:a1c:e5cf:: with SMTP id c198-v6mr6258019wmh.113.1537525558907; Fri, 21 Sep 2018 03:25:58 -0700 (PDT) Received: from localhost (pD9E515A3.dip0.t-ipconnect.de. [217.229.21.163]) by smtp.gmail.com with ESMTPSA id x65-v6sm5573042wmg.39.2018.09.21.03.25.58 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 21 Sep 2018 03:25:58 -0700 (PDT) From: Thierry Reding To: Linus Walleij , Thierry Reding Cc: Thomas Gleixner , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 7/9] dt-bindings: tegra186-gpio: Add wakeup parent support Date: Fri, 21 Sep 2018 12:25:44 +0200 Message-Id: <20180921102546.12745-8-thierry.reding@gmail.com> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20180921102546.12745-1-thierry.reding@gmail.com> References: <20180921102546.12745-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding Tegra186 and later have some top-level controls for wake events in the power management controller (PMC). In order to enable the system to wake up from low power states, additional registers in the PMC need to be programmed. Add a wakeup-parent property to establish this relationship between the GPIO controller and the PMC. Signed-off-by: Thierry Reding --- .../devicetree/bindings/gpio/nvidia,tegra186-gpio.txt | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.txt b/Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.txt index adff16c71d21..cbb51a8990c3 100644 --- a/Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.txt +++ b/Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.txt @@ -127,6 +127,11 @@ Required properties: - 8: Active low level-sensitive. Valid combinations are 1, 2, 3, 4, 8. +Optional properties: +- wake-parent + A phandle to the Power Management Controller (PMC) that contains top- + level controls to enable the wake-up capabilities of some GPIOs. + Example: #include @@ -148,6 +153,7 @@ gpio@2200000 { #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + wakeup-parent = <&pmc>; }; gpio@c2f0000 { @@ -162,4 +168,5 @@ gpio@c2f0000 { #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + wakeup-parent = <&pmc>; }; From patchwork Fri Sep 21 10:25:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 973087 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="u1H8vUWB"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42GqWj6Dbyz9sCc for ; Fri, 21 Sep 2018 20:26:25 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389971AbeIUQOP (ORCPT ); Fri, 21 Sep 2018 12:14:15 -0400 Received: from mail-wm1-f65.google.com ([209.85.128.65]:53759 "EHLO mail-wm1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2390422AbeIUQOP (ORCPT ); Fri, 21 Sep 2018 12:14:15 -0400 Received: by mail-wm1-f65.google.com with SMTP id b19-v6so2507787wme.3; Fri, 21 Sep 2018 03:26:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fSs5Q2DC8kHvOkkfmRY6o4j+dxlAtNorZ2w89xOGL0M=; b=u1H8vUWBiS9RHPvzqSvc0FOwMIw28n1qg6CW68hmltnFhuRhHRDolMaGRll/7WagOO pc/E68TbTyxhQQ00si0nsbxh6YRp8DCh6EGAV+s3dFc/bB1OTXpDeGJljJrRMWayMXEX G59eMpuJiv2fKOMqnD4abblkANwfcJcUhLwWnLP8tbJa5IPPs4coIO55Q0gi14+42T+i OGGM5dVLdLIaiAOM21viM71n72lsIOXXQHyeZNZuLrRoP5WheTR40Swbx2JRP7rN1W98 DRRzxhSNaoAJlxwXb+vMUcAk+Yw4OOB/z56aPb46+wXiYmyCmHMktIf4h4Dex0xbcgBh DBFQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fSs5Q2DC8kHvOkkfmRY6o4j+dxlAtNorZ2w89xOGL0M=; b=WCPilplo1v1B3IxpP3x8M6yWzeTo0cXOON7nxk0L53yc5hG+wjPU2wTRio4TJ6Bhkh 2eBm/BCBqERMU9QuEwQEWIstCbb2uJAdQJqjgkbSY4YHN6S3pEuVqoWpPQEJwnkcjNUs S6sYiqCv67Y2WCR0IA+alZBaEzefG2jJKbwFJec4OaavAtkURg4xCcQK+L3eNuzmNysU +s7i3d5ORFNzMvfuXOfQwc/M7/VUTWK7XdtQ+OvdXc3sDA28Lzp51cQdXzioTq4n21G8 PO+jSk+H/GwqfcABvOH+OV5iu8dYMohgDA5kToQI8/I4aQ2ngWy7Se6ZYYGM0ZSWJdIR 9rcg== X-Gm-Message-State: APzg51CzsEOzGGkRaIzBMud2OOxxO9v41quLYJc8ZA7gyBc4QfegFMbV FYgm1FhbG3XnmqMtCzSRs0s= X-Google-Smtp-Source: ACcGV60+2GAsREjlGlnO1ySlsS+k0ZrsNFzafwCD2eNH7yM2qLm+ZEuQnn+kC20/nM70u688mVkSyw== X-Received: by 2002:a1c:2dc8:: with SMTP id t191-v6mr6717345wmt.94.1537525560296; Fri, 21 Sep 2018 03:26:00 -0700 (PDT) Received: from localhost (pD9E515A3.dip0.t-ipconnect.de. [217.229.21.163]) by smtp.gmail.com with ESMTPSA id u127-v6sm3432035wmf.48.2018.09.21.03.25.59 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 21 Sep 2018 03:25:59 -0700 (PDT) From: Thierry Reding To: Linus Walleij , Thierry Reding Cc: Thomas Gleixner , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 8/9] gpio: tegra186: Rename flow variable to type Date: Fri, 21 Sep 2018 12:25:45 +0200 Message-Id: <20180921102546.12745-9-thierry.reding@gmail.com> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20180921102546.12745-1-thierry.reding@gmail.com> References: <20180921102546.12745-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The IRQ core code refers to the interrupt type by that name, whereas the term flow is almost never used. Some GPIO controllers use the term flow_type, but it is most consistent to just go with the IRQ core terminology. Signed-off-by: Thierry Reding --- drivers/gpio/gpio-tegra186.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpio/gpio-tegra186.c b/drivers/gpio/gpio-tegra186.c index 9d0292c8a199..66ec38bb7954 100644 --- a/drivers/gpio/gpio-tegra186.c +++ b/drivers/gpio/gpio-tegra186.c @@ -279,7 +279,7 @@ static void tegra186_irq_unmask(struct irq_data *data) writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); } -static int tegra186_irq_set_type(struct irq_data *data, unsigned int flow) +static int tegra186_irq_set_type(struct irq_data *data, unsigned int type) { struct tegra_gpio *gpio = irq_data_get_irq_chip_data(data); void __iomem *base; @@ -293,7 +293,7 @@ static int tegra186_irq_set_type(struct irq_data *data, unsigned int flow) value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK; value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL; - switch (flow & IRQ_TYPE_SENSE_MASK) { + switch (type & IRQ_TYPE_SENSE_MASK) { case IRQ_TYPE_NONE: break; @@ -325,7 +325,7 @@ static int tegra186_irq_set_type(struct irq_data *data, unsigned int flow) writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); - if ((flow & IRQ_TYPE_EDGE_BOTH) == 0) + if ((type & IRQ_TYPE_EDGE_BOTH) == 0) irq_set_handler_locked(data, handle_level_irq); else irq_set_handler_locked(data, handle_edge_irq); From patchwork Fri Sep 21 10:25:46 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 973083 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="snzkqayg"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42GqWS5cyLz9sCc for ; Fri, 21 Sep 2018 20:26:12 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390460AbeIUQOS (ORCPT ); Fri, 21 Sep 2018 12:14:18 -0400 Received: from mail-wm1-f66.google.com ([209.85.128.66]:40552 "EHLO mail-wm1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389264AbeIUQOR (ORCPT ); Fri, 21 Sep 2018 12:14:17 -0400 Received: by mail-wm1-f66.google.com with SMTP id 207-v6so2623425wme.5; Fri, 21 Sep 2018 03:26:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0GzBW6zSdxv8IXZx0dYxoAsvyniuXSIQK+Td08qUum4=; b=snzkqaygXyTWDc+Wjp7vIUxgzRXXr7dslbTSESGcVCC+cPhclBtBTzfCVIKjr/NhQA rF2r1g/qQZHi6FaYcLWiOON4oN7O87+DcQ1ES41PNWZEzHJf1ocDu2ijKtyYP/guWhUd /opHgbkbemEa0NzKERgWuvOwPK54JBQ6ViUWVJWgYvzOea7MBgmIsGiC3SwbFJ7qSGR7 U0HTwaNwClFbyVZFJLzWU0gQEwySqVn15Bpx/TaxHo2vAVDNSglBN292FIu2Hfin+UcR ci579Tr58oC86NB8iHXYb1iplUIcmWMbJRmXe/xAudAw86PGKeX9u/YGoj0igVOhbMm+ Yjjg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0GzBW6zSdxv8IXZx0dYxoAsvyniuXSIQK+Td08qUum4=; b=PdfGNxsqjEAC81eyrx6q8svFHhH8IpueKyZTqJdhxhCp3Aa1dL7u/6R4HbPzFhkaSL 3LrO/pNv3UBtNyYz1b0bBTyMTZKCyqqpfBILvAP8Q/WJDu2W7tGHv3khDNZu8h78OJYR MjDCoRTdOne9Eq0wzoZGzJs7BPiHsn3gILvtWid9xcBOPhN4ixHd8A0PDLo06vQVLADf 8ON+jWPdhht4YcFGrHJ0J0fHERnS7/cEj+SRROLHue31pUERZ1pD5jYYXYu+r2eAmz1x bwjPkJsibmyB0LeY7nYFjdKOkstVaZM76VnRld3mrQJEv3GKDdtiXh4Zz1LlGybCkhA8 IYqg== X-Gm-Message-State: APzg51DrsnG77IB2RXtyptkJ113/kGug7mTZIfPE9OpW7E49gGz2cfft lKHwN3ah2jYtq9EVTexzsTA= X-Google-Smtp-Source: ANB0VdbQnxowX2F+WNmcgGR5Dil56dmOvDrXC7GglOU/gvDkKCUund8zLzeBtK7ivEEwoQyEKcpjqQ== X-Received: by 2002:a1c:2ed4:: with SMTP id u203-v6mr3431379wmu.19.1537525561702; Fri, 21 Sep 2018 03:26:01 -0700 (PDT) Received: from localhost (pD9E515A3.dip0.t-ipconnect.de. [217.229.21.163]) by smtp.gmail.com with ESMTPSA id w94-v6sm20063905wrc.38.2018.09.21.03.26.00 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 21 Sep 2018 03:26:01 -0700 (PDT) From: Thierry Reding To: Linus Walleij , Thierry Reding Cc: Thomas Gleixner , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 9/9] gpio: tegra186: Implement wake event support Date: Fri, 21 Sep 2018 12:25:46 +0200 Message-Id: <20180921102546.12745-10-thierry.reding@gmail.com> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20180921102546.12745-1-thierry.reding@gmail.com> References: <20180921102546.12745-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The GPIO controller doesn't have any controls to enable the system to wake up from low power states based on activity on GPIO pins. An extra hardware block that is part of the power management controller (PMC) contains these controls. In order for the GPIO controller to be able to cooperate with the PMC, obtain a reference to the PMC's IRQ domain and make it a parent to the GPIO controller's IRQ domain. This way the PMC gets an opportunity to program the additional registers required to enable wakeup sources on suspend. Signed-off-by: Thierry Reding --- drivers/gpio/gpio-tegra186.c | 103 ++++++++++++++++++++++++++++++----- 1 file changed, 89 insertions(+), 14 deletions(-) diff --git a/drivers/gpio/gpio-tegra186.c b/drivers/gpio/gpio-tegra186.c index 66ec38bb7954..240a26defe9b 100644 --- a/drivers/gpio/gpio-tegra186.c +++ b/drivers/gpio/gpio-tegra186.c @@ -56,6 +56,7 @@ struct tegra_gpio_soc { const struct tegra_gpio_port *ports; unsigned int num_ports; const char *name; + unsigned int instance; }; struct tegra_gpio { @@ -237,6 +238,38 @@ static int tegra186_gpio_of_xlate(struct gpio_chip *chip, return offset + pin; } +static int tegra186_gpio_to_irq(struct gpio_chip *chip, unsigned int offset) +{ + struct tegra_gpio *gpio = gpiochip_get_data(chip); + struct irq_domain *domain = chip->irq.domain; + + if (!gpiochip_irqchip_irq_valid(chip, offset)) + return -ENXIO; + + if (irq_domain_is_hierarchy(domain)) { + struct irq_fwspec spec; + unsigned int i; + + for (i = 0; i < gpio->soc->num_ports; i++) { + if (offset < gpio->soc->ports[i].pins) + break; + + offset -= gpio->soc->ports[i].pins; + } + + offset += i * 8; + + spec.fwnode = domain->fwnode; + spec.param_count = 2; + spec.param[0] = offset; + spec.param[1] = 0; + + return irq_domain_alloc_irqs(domain, 1, NUMA_NO_NODE, &spec); + } + + return irq_create_mapping(domain, offset); +} + static void tegra186_irq_ack(struct irq_data *data) { struct tegra_gpio *gpio = irq_data_get_irq_chip_data(data); @@ -330,7 +363,7 @@ static int tegra186_irq_set_type(struct irq_data *data, unsigned int type) else irq_set_handler_locked(data, handle_edge_irq); - return 0; + return irq_chip_set_type_parent(data, type); } static void tegra186_gpio_irq(struct irq_desc *desc) @@ -370,39 +403,67 @@ static void tegra186_gpio_irq(struct irq_desc *desc) chained_irq_exit(chip, desc); } -static int tegra186_gpio_irq_domain_xlate(struct irq_domain *domain, - struct device_node *np, - const u32 *spec, unsigned int size, - unsigned long *hwirq, - unsigned int *type) +static int tegra186_gpio_irq_domain_translate(struct irq_domain *domain, + struct irq_fwspec *fwspec, + unsigned long *hwirq, + unsigned int *type) { struct tegra_gpio *gpio = gpiochip_get_data(domain->host_data); unsigned int port, pin, i, offset = 0; - if (size < 2) + if (WARN_ON(gpio->gpio.of_gpio_n_cells < 2)) return -EINVAL; - port = spec[0] / 8; - pin = spec[0] % 8; + if (WARN_ON(fwspec->param_count < gpio->gpio.of_gpio_n_cells)) + return -EINVAL; - if (port >= gpio->soc->num_ports) { - dev_err(gpio->gpio.parent, "invalid port number: %u\n", port); + port = fwspec->param[0] / 8; + pin = fwspec->param[0] % 8; + + if (port >= gpio->soc->num_ports) return -EINVAL; - } for (i = 0; i < port; i++) offset += gpio->soc->ports[i].pins; - *type = spec[1] & IRQ_TYPE_SENSE_MASK; + *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK; *hwirq = offset + pin; return 0; } +static int tegra186_gpio_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, unsigned int num_irqs, void *data) +{ + struct tegra_gpio *gpio = gpiochip_get_data(domain->host_data); + struct irq_fwspec *fwspec = data; + struct irq_fwspec spec; + unsigned long hwirq; + unsigned int type; + int err = 0; + + err = tegra186_gpio_irq_domain_translate(domain, fwspec, &hwirq, &type); + if (err < 0) + return err; + + err = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, &gpio->intc, + gpio); + if (err < 0) + return err; + + spec.fwnode = domain->parent->fwnode; + spec.param_count = 3; + spec.param[0] = gpio->soc->instance; + spec.param[1] = fwspec->param[0]; + spec.param[2] = fwspec->param[1]; + + return irq_domain_alloc_irqs_parent(domain, virq, num_irqs, &spec); +} + static const struct irq_domain_ops tegra186_gpio_irq_domain_ops = { + .translate = tegra186_gpio_irq_domain_translate, + .alloc = tegra186_gpio_irq_domain_alloc, .map = gpiochip_irq_map, .unmap = gpiochip_irq_unmap, - .xlate = tegra186_gpio_irq_domain_xlate, }; static int tegra186_gpio_probe(struct platform_device *pdev) @@ -410,6 +471,7 @@ static int tegra186_gpio_probe(struct platform_device *pdev) unsigned int i, j, offset; struct gpio_irq_chip *irq; struct tegra_gpio *gpio; + struct device_node *np; struct resource *res; char **names; int err; @@ -484,12 +546,14 @@ static int tegra186_gpio_probe(struct platform_device *pdev) gpio->gpio.of_node = pdev->dev.of_node; gpio->gpio.of_gpio_n_cells = 2; gpio->gpio.of_xlate = tegra186_gpio_of_xlate; + gpio->gpio.to_irq = tegra186_gpio_to_irq; gpio->intc.name = pdev->dev.of_node->name; gpio->intc.irq_ack = tegra186_irq_ack; gpio->intc.irq_mask = tegra186_irq_mask; gpio->intc.irq_unmask = tegra186_irq_unmask; gpio->intc.irq_set_type = tegra186_irq_set_type; + gpio->intc.irq_set_wake = irq_chip_set_wake_parent; irq = &gpio->gpio.irq; irq->chip = &gpio->intc; @@ -501,6 +565,15 @@ static int tegra186_gpio_probe(struct platform_device *pdev) irq->num_parents = gpio->num_irq; irq->parents = gpio->irq; + np = of_parse_phandle(pdev->dev.of_node, "wakeup-parent", 0); + if (np) { + irq->parent_domain = irq_find_host(np); + of_node_put(np); + + if (!irq->parent_domain) + return -EPROBE_DEFER; + } + irq->map = devm_kcalloc(&pdev->dev, gpio->gpio.ngpio, sizeof(*irq->map), GFP_KERNEL); if (!irq->map) @@ -637,6 +710,7 @@ static const struct tegra_gpio_soc tegra194_main_soc = { .num_ports = ARRAY_SIZE(tegra194_main_ports), .ports = tegra194_main_ports, .name = "tegra194-gpio", + .instance = 0, }; #define TEGRA194_AON_GPIO_PORT(port, base, count, controller) \ @@ -659,6 +733,7 @@ static const struct tegra_gpio_soc tegra194_aon_soc = { .num_ports = ARRAY_SIZE(tegra194_aon_ports), .ports = tegra194_aon_ports, .name = "tegra194-gpio-aon", + .instance = 1, }; static const struct of_device_id tegra186_gpio_of_match[] = {