From patchwork Mon Sep 10 19:19:46 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Uros Bizjak X-Patchwork-Id: 968200 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-485416-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="XLwhKkyd"; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="mKf344V8"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 428Htx1TqRz9s2P for ; Tue, 11 Sep 2018 05:20:25 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:content-type; q= dns; s=default; b=N6f1RxrIsIh1LQbm29PFYWhj7cPX5CpmFh6o0mUkcFZPDu sphhtgexU/QH6NYmK8tuscKB2pgQWGXljeviW1n9sN20iNPjwmjWiuIRinvMBJdH eG1PybQnIgYFku68dHmzOvo2UHx813aZrEEuI7547zDIwcdI1koKCywxWC1WA= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:content-type; s= default; bh=vgNr7E+hA3PhG4XSewrhVsQ9rwU=; b=XLwhKkydiIhROveL3IML wiWTHlxI1i3NiVeiwEwkzmNg2hHV7fUi3OEVRl1iMVZw47lvODiivsqSdl50+kBb XnrV7y0uYRKIs3mHfwUgQcyFrd+Bt/S9NUGDl+arCRaFh+ASTgWSQIFghuTAOWzq pY9HfwApV393R7toZBsLEd0= Received: (qmail 15712 invoked by alias); 10 Sep 2018 19:19:53 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 15577 invoked by uid 89); 10 Sep 2018 19:19:52 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-11.8 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=cos, tan, H*r:sk:q5-v6so X-HELO: mail-io0-f178.google.com Received: from mail-io0-f178.google.com (HELO mail-io0-f178.google.com) (209.85.223.178) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 10 Sep 2018 19:19:49 +0000 Received: by mail-io0-f178.google.com with SMTP id q5-v6so1604323iop.3 for ; Mon, 10 Sep 2018 12:19:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:from:date:message-id:subject:to; bh=IlEJYsQ5Z7M/ArKT8+TF6Asce62x6kpiABYl+5BxDoc=; b=mKf344V80/AtTP4KY0wRgD+hMNhOn2UBNDheHbHvv3J5TDrOiotJGMAx2N4bDjSRqe h1EghkIiqvka1I7DKsCMyfSADUPH9xAlqw6NRZVkNPCh0cnvd4Q02jt05mFoWn7n3A0R wVxidmSzT8fIIVAn3Sou4unMtnGFbVgdgRIsgAS6hpWGrSrD862Zsowjl1hINUba2CPY bKwKwwKIqUP/dvnwY1FTjZLNiUNDrEixRru9TJfzgJFBvehnehY20+b1hmJT1YfhG3KZ VXOhBuykVu+/aO8VWq9yUYX2DviHi+qtOjXL39pVXqZMtDFbY69VMSxkiqVEBemgwqU4 FmyA== MIME-Version: 1.0 Received: by 2002:a02:56d5:0:0:0:0:0 with HTTP; Mon, 10 Sep 2018 12:19:46 -0700 (PDT) From: Uros Bizjak Date: Mon, 10 Sep 2018 21:19:46 +0200 Message-ID: Subject: [PATCH, i386]: Rewrite x87 trigonometric patterns To: "gcc-patches@gcc.gnu.org" Hello! Attached patch removes a bunch of sincos -> sin, cos splitters. These are not necessary anymore since middle end handles the transformation in a generic way. Additionally, the patch removes unnecessary mixed-mode patters (SFmode/DFmode input operand and XFmode outputs). These are not needed, because all x87 float_extend RTXes degenerate to a plain move (or a no-op move). The patch also includes a couple of cleanups with no functional changes. 2018-09-10 Uros Bizjak * config/i386/i386.md (xf2): Rename from *xf2_i387. (*_extendxf2_i387): Remove insn pattern. (mode2): New expander. (sincos_extendxf3_i387): Remove insn pattern. (sincos -> sin, cos splitters): Remove splitter patterns. (sincos3): Change operand 2 predicate to general_operand. Extend operand 2 to XFmode and generate sincosxf3 insn. (fptanxf4_i387): Change mode of operands 0 and 3 to SFmode. Change operand 3 predicate to const1_operand. (fptan_extendxf4_i387): Remove insn pattern. (tanxf2): Update operands in the call to fptanxf4_i387. (tan2): Change operand 1 predicate to general_operand. Extend operand 1 to XFmode and generate tanxf3 insn. (atan2xf3): Rename from *fpatanxf3_i387. (fpatan_extendxf3_i387): Remove insn pattern. (atan2xf3): Remove expander. (atan22): Change operand 1 predicate to general_operand. Extend operand 1 to XFmode and generate atanxf3 insn. Patch was bootstrapped and regression tested on x86_64-linux-gnu {,-m32}. Committed to mainline SVN. Uros. Index: config/i386/i386.md =================================================================== --- config/i386/i386.md (revision 264185) +++ config/i386/i386.md (working copy) @@ -15375,7 +15375,7 @@ [(UNSPEC_SIN "sin") (UNSPEC_COS "cos")]) -(define_insn "*xf2_i387" +(define_insn "xf2" [(set (match_operand:XF 0 "register_operand" "=f") (unspec:XF [(match_operand:XF 1 "register_operand" "0")] SINCOS))] @@ -15386,25 +15386,23 @@ (set_attr "znver1_decode" "vector") (set_attr "mode" "XF")]) -(define_insn "*_extendxf2_i387" - [(set (match_operand:XF 0 "register_operand" "=f") - (unspec:XF [(float_extend:XF - (match_operand:MODEF 1 "register_operand" "0"))] - SINCOS))] +(define_expand "2" + [(set (match_operand:MODEF 0 "register_operand") + (unspec:MODEF [(match_operand:MODEF 1 "general_operand")] + SINCOS))] "TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) && flag_unsafe_math_optimizations" - "f" - [(set_attr "type" "fpspc") - (set_attr "znver1_decode" "vector") - (set_attr "mode" "XF")]) +{ + rtx op0 = gen_reg_rtx (XFmode); + rtx op1 = gen_reg_rtx (XFmode); -;; When sincos pattern is defined, sin and cos builtin functions will be -;; expanded to sincos pattern with one of its outputs left unused. -;; CSE pass will figure out if two sincos patterns can be combined, -;; otherwise sincos pattern will be split back to sin or cos pattern, -;; depending on the unused output. + emit_insn (gen_extendxf2 (op1, operands[1])); + emit_insn (gen_xf2 (op0, op1)); + emit_insn (gen_truncxf2 (operands[0], op0)); + DONE; +}) (define_insn "sincosxf3" [(set (match_operand:XF 0 "register_operand" "=f") @@ -15419,70 +15417,10 @@ (set_attr "znver1_decode" "vector") (set_attr "mode" "XF")]) -(define_split - [(set (match_operand:XF 0 "register_operand") - (unspec:XF [(match_operand:XF 2 "register_operand")] - UNSPEC_SINCOS_COS)) - (set (match_operand:XF 1 "register_operand") - (unspec:XF [(match_dup 2)] UNSPEC_SINCOS_SIN))] - "find_regno_note (insn, REG_UNUSED, REGNO (operands[0])) - && can_create_pseudo_p ()" - [(set (match_dup 1) (unspec:XF [(match_dup 2)] UNSPEC_SIN))]) - -(define_split - [(set (match_operand:XF 0 "register_operand") - (unspec:XF [(match_operand:XF 2 "register_operand")] - UNSPEC_SINCOS_COS)) - (set (match_operand:XF 1 "register_operand") - (unspec:XF [(match_dup 2)] UNSPEC_SINCOS_SIN))] - "find_regno_note (insn, REG_UNUSED, REGNO (operands[1])) - && can_create_pseudo_p ()" - [(set (match_dup 0) (unspec:XF [(match_dup 2)] UNSPEC_COS))]) - -(define_insn "sincos_extendxf3_i387" - [(set (match_operand:XF 0 "register_operand" "=f") - (unspec:XF [(float_extend:XF - (match_operand:MODEF 2 "register_operand" "0"))] - UNSPEC_SINCOS_COS)) - (set (match_operand:XF 1 "register_operand" "=u") - (unspec:XF [(float_extend:XF (match_dup 2))] UNSPEC_SINCOS_SIN))] - "TARGET_USE_FANCY_MATH_387 - && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) - || TARGET_MIX_SSE_I387) - && flag_unsafe_math_optimizations" - "fsincos" - [(set_attr "type" "fpspc") - (set_attr "znver1_decode" "vector") - (set_attr "mode" "XF")]) - -(define_split - [(set (match_operand:XF 0 "register_operand") - (unspec:XF [(float_extend:XF - (match_operand:MODEF 2 "register_operand"))] - UNSPEC_SINCOS_COS)) - (set (match_operand:XF 1 "register_operand") - (unspec:XF [(float_extend:XF (match_dup 2))] UNSPEC_SINCOS_SIN))] - "find_regno_note (insn, REG_UNUSED, REGNO (operands[0])) - && can_create_pseudo_p ()" - [(set (match_dup 1) - (unspec:XF [(float_extend:XF (match_dup 2))] UNSPEC_SIN))]) - -(define_split - [(set (match_operand:XF 0 "register_operand") - (unspec:XF [(float_extend:XF - (match_operand:MODEF 2 "register_operand"))] - UNSPEC_SINCOS_COS)) - (set (match_operand:XF 1 "register_operand") - (unspec:XF [(float_extend:XF (match_dup 2))] UNSPEC_SINCOS_SIN))] - "find_regno_note (insn, REG_UNUSED, REGNO (operands[1])) - && can_create_pseudo_p ()" - [(set (match_dup 0) - (unspec:XF [(float_extend:XF (match_dup 2))] UNSPEC_COS))]) - (define_expand "sincos3" [(use (match_operand:MODEF 0 "register_operand")) (use (match_operand:MODEF 1 "register_operand")) - (use (match_operand:MODEF 2 "register_operand"))] + (use (match_operand:MODEF 2 "general_operand"))] "TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) @@ -15490,8 +15428,10 @@ { rtx op0 = gen_reg_rtx (XFmode); rtx op1 = gen_reg_rtx (XFmode); + rtx op2 = gen_reg_rtx (XFmode); - emit_insn (gen_sincos_extendxf3_i387 (op0, op1, operands[2])); + emit_insn (gen_extendxf2 (op2, operands[2])); + emit_insn (gen_sincosxf3 (op0, op1, op2)); emit_insn (gen_truncxf2 (operands[0], op0)); emit_insn (gen_truncxf2 (operands[1], op1)); DONE; @@ -15498,36 +15438,18 @@ }) (define_insn "fptanxf4_i387" - [(set (match_operand:XF 0 "register_operand" "=f") - (match_operand:XF 3 "const_double_operand" "F")) + [(set (match_operand:SF 0 "register_operand" "=f") + (match_operand:SF 3 "const1_operand")) (set (match_operand:XF 1 "register_operand" "=u") (unspec:XF [(match_operand:XF 2 "register_operand" "0")] UNSPEC_TAN))] "TARGET_USE_FANCY_MATH_387 - && flag_unsafe_math_optimizations - && standard_80387_constant_p (operands[3]) == 2" + && flag_unsafe_math_optimizations" "fptan" [(set_attr "type" "fpspc") (set_attr "znver1_decode" "vector") (set_attr "mode" "XF")]) -(define_insn "fptan_extendxf4_i387" - [(set (match_operand:MODEF 0 "register_operand" "=f") - (match_operand:MODEF 3 "const_double_operand" "F")) - (set (match_operand:XF 1 "register_operand" "=u") - (unspec:XF [(float_extend:XF - (match_operand:MODEF 2 "register_operand" "0"))] - UNSPEC_TAN))] - "TARGET_USE_FANCY_MATH_387 - && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) - || TARGET_MIX_SSE_I387) - && flag_unsafe_math_optimizations - && standard_80387_constant_p (operands[3]) == 2" - "fptan" - [(set_attr "type" "fpspc") - (set_attr "znver1_decode" "vector") - (set_attr "mode" "XF")]) - (define_expand "tanxf2" [(use (match_operand:XF 0 "register_operand")) (use (match_operand:XF 1 "register_operand"))] @@ -15534,16 +15456,15 @@ "TARGET_USE_FANCY_MATH_387 && flag_unsafe_math_optimizations" { - rtx one = gen_reg_rtx (XFmode); - rtx op2 = CONST1_RTX (XFmode); /* fld1 */ - - emit_insn (gen_fptanxf4_i387 (one, operands[0], operands[1], op2)); + rtx one = gen_reg_rtx (SFmode); + emit_insn (gen_fptanxf4_i387 (one, operands[0], operands[1], + CONST1_RTX (SFmode))); DONE; }) (define_expand "tan2" [(use (match_operand:MODEF 0 "register_operand")) - (use (match_operand:MODEF 1 "register_operand"))] + (use (match_operand:MODEF 1 "general_operand"))] "TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) @@ -15550,17 +15471,15 @@ && flag_unsafe_math_optimizations" { rtx op0 = gen_reg_rtx (XFmode); + rtx op1 = gen_reg_rtx (XFmode); - rtx one = gen_reg_rtx (mode); - rtx op2 = CONST1_RTX (mode); /* fld1 */ - - emit_insn (gen_fptan_extendxf4_i387 (one, op0, - operands[1], op2)); + emit_insn (gen_extendxf2 (op1, operands[1])); + emit_insn (gen_tanxf2 (op0, op1)); emit_insn (gen_truncxf2 (operands[0], op0)); DONE; }) -(define_insn "*fpatanxf3_i387" +(define_insn "atan2xf3" [(set (match_operand:XF 0 "register_operand" "=f") (unspec:XF [(match_operand:XF 1 "register_operand" "0") (match_operand:XF 2 "register_operand" "u")] @@ -15573,36 +15492,10 @@ (set_attr "znver1_decode" "vector") (set_attr "mode" "XF")]) -(define_insn "fpatan_extendxf3_i387" - [(set (match_operand:XF 0 "register_operand" "=f") - (unspec:XF [(float_extend:XF - (match_operand:MODEF 1 "register_operand" "0")) - (float_extend:XF - (match_operand:MODEF 2 "register_operand" "u"))] - UNSPEC_FPATAN)) - (clobber (match_scratch:XF 3 "=2"))] - "TARGET_USE_FANCY_MATH_387 - && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) - || TARGET_MIX_SSE_I387) - && flag_unsafe_math_optimizations" - "fpatan" - [(set_attr "type" "fpspc") - (set_attr "znver1_decode" "vector") - (set_attr "mode" "XF")]) - -(define_expand "atan2xf3" - [(parallel [(set (match_operand:XF 0 "register_operand") - (unspec:XF [(match_operand:XF 2 "register_operand") - (match_operand:XF 1 "register_operand")] - UNSPEC_FPATAN)) - (clobber (match_scratch:XF 3))])] - "TARGET_USE_FANCY_MATH_387 - && flag_unsafe_math_optimizations") - (define_expand "atan23" [(use (match_operand:MODEF 0 "register_operand")) - (use (match_operand:MODEF 1 "register_operand")) - (use (match_operand:MODEF 2 "register_operand"))] + (use (match_operand:MODEF 1 "general_operand")) + (use (match_operand:MODEF 2 "general_operand"))] "TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) @@ -15609,8 +15502,13 @@ && flag_unsafe_math_optimizations" { rtx op0 = gen_reg_rtx (XFmode); + rtx op1 = gen_reg_rtx (XFmode); + rtx op2 = gen_reg_rtx (XFmode); - emit_insn (gen_fpatan_extendxf3_i387 (op0, operands[2], operands[1])); + emit_insn (gen_extendxf2 (op2, operands[2])); + emit_insn (gen_extendxf2 (op1, operands[1])); + + emit_insn (gen_atan2xf3 (op0, op2, op1)); emit_insn (gen_truncxf2 (operands[0], op0)); DONE; }) @@ -15623,14 +15521,11 @@ (clobber (match_scratch:XF 3))])] "TARGET_USE_FANCY_MATH_387 && flag_unsafe_math_optimizations" -{ - operands[2] = gen_reg_rtx (XFmode); - emit_move_insn (operands[2], CONST1_RTX (XFmode)); /* fld1 */ -}) + "operands[2] = force_reg (XFmode, CONST1_RTX (XFmode));") (define_expand "atan2" [(use (match_operand:MODEF 0 "register_operand")) - (use (match_operand:MODEF 1 "register_operand"))] + (use (match_operand:MODEF 1 "general_operand"))] "TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) @@ -15637,11 +15532,10 @@ && flag_unsafe_math_optimizations" { rtx op0 = gen_reg_rtx (XFmode); + rtx op1 = gen_reg_rtx (XFmode); - rtx op2 = gen_reg_rtx (mode); - emit_move_insn (op2, CONST1_RTX (mode)); /* fld1 */ - - emit_insn (gen_fpatan_extendxf3_i387 (op0, op2, operands[1])); + emit_insn (gen_extendxf2 (op1, operands[1])); + emit_insn (gen_atanxf2 (op0, op1)); emit_insn (gen_truncxf2 (operands[0], op0)); DONE; }) @@ -15664,7 +15558,7 @@ for (i = 2; i < 6; i++) operands[i] = gen_reg_rtx (XFmode); - emit_move_insn (operands[3], CONST1_RTX (XFmode)); /* fld1 */ + operands[3] = force_reg (XFmode, CONST1_RTX (XFmode)); }) (define_expand "asin2" @@ -15702,7 +15596,7 @@ for (i = 2; i < 6; i++) operands[i] = gen_reg_rtx (XFmode); - emit_move_insn (operands[3], CONST1_RTX (XFmode)); /* fld1 */ + operands[3] = force_reg (XFmode, CONST1_RTX (XFmode)); }) (define_expand "acos2"