From patchwork Mon Sep 10 02:17:30 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 967840 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=socionext.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=nifty.com header.i=@nifty.com header.b="v8ZQ0c8d"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 427sCZ4Tm9z9s3C for ; Mon, 10 Sep 2018 12:18:14 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 1011BC21E12; Mon, 10 Sep 2018 02:18:10 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 24971C21C50; Mon, 10 Sep 2018 02:18:08 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id E14D6C21C50; Mon, 10 Sep 2018 02:18:06 +0000 (UTC) Received: from conuserg-10.nifty.com (conuserg-10.nifty.com [210.131.2.77]) by lists.denx.de (Postfix) with ESMTPS id 30ECFC21C4A for ; Mon, 10 Sep 2018 02:18:04 +0000 (UTC) Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-10.nifty.com with ESMTP id w8A2HWpf030154; Mon, 10 Sep 2018 11:17:32 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-10.nifty.com w8A2HWpf030154 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1536545853; bh=vO57OPJiASCaxrcoXYQ+KNJCi3cBDHbO5qyVxr1TUuQ=; h=From:To:Cc:Subject:Date:From; b=v8ZQ0c8d18tOWwQIPYMJyH/E6o8IUWj1xAKgqPoLeIJE9gbXxZKro2Vr502+2CFuU 9DJNtXXjiAbbzU4pod/Zam/jrm/+xsjo2RstFIjrIZZHCm0d7y+alqAWBEbsoDcGgV iWLWLPXuUwRhGGVvpky6rn8DLAKSDBIpmMkWuhAiS/qh+yfLKuLXvZPaPnfUY1nBTZ AhGdSvhIA1iw3SubcTr+taOAFx4GR8gWqLVqHK0Tybvw4/O9VaZe20Tc8/C0En0Xfr Ka7J0DQWx8OoWRkiFwSwxl4YKnpjDFLGKKyUMlaUuGAN/8/sYPMUcmegpehj8xaP4e cT4ZSLy8f8MyA== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Mon, 10 Sep 2018 11:17:30 +0900 Message-Id: <1536545850-31998-1-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 Cc: Tom Rini , Marek Vasut Subject: [U-Boot] [PATCH] mtd: nand: denali: fix unaligned cache operation warnings on ARMv7 SoCs X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" If the OOB size is not multiple of the cache line size, the ARMv7 cache operation still warns "Misaligned operation at range". The real cache coherency problem was fixed by commit e3332e1a1a04 ("Make kmalloc'ed memory really DMA-safe"). Now it is the matter of the warning messages. => nand info Device 0: nand0, sector size 256 KiB Page size 4096 b OOB size 224 b Erase size 262144 b subpagesize 4096 b options 0x00104200 bbt options 0x00060000 => nand dump 0 CACHE: Misaligned operation at range [9fb15280, 9fb16360] CACHE: Misaligned operation at range [9fb15280, 9fb16360] CACHE: Misaligned operation at range [9fb15280, 9fb16360] CACHE: Misaligned operation at range [9fb15280, 9fb16360] ... Reported-by: Marek Vasut Signed-off-by: Masahiro Yamada --- drivers/mtd/nand/denali.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c index 7302c37..d1cac06 100644 --- a/drivers/mtd/nand/denali.c +++ b/drivers/mtd/nand/denali.c @@ -21,6 +21,8 @@ static dma_addr_t dma_map_single(void *dev, void *ptr, size_t size, { unsigned long addr = (unsigned long)ptr; + size = ALIGN(size, ARCH_DMA_MINALIGN); + if (dir == DMA_FROM_DEVICE) invalidate_dcache_range(addr, addr + size); else @@ -32,6 +34,8 @@ static dma_addr_t dma_map_single(void *dev, void *ptr, size_t size, static void dma_unmap_single(void *dev, dma_addr_t addr, size_t size, enum dma_data_direction dir) { + size = ALIGN(size, ARCH_DMA_MINALIGN); + if (dir != DMA_TO_DEVICE) invalidate_dcache_range(addr, addr + size); }