From patchwork Wed Oct 4 16:31:10 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Brandt X-Patchwork-Id: 821398 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3y6hHX0h8Dz9t32 for ; Thu, 5 Oct 2017 03:31:36 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751221AbdJDQba (ORCPT ); Wed, 4 Oct 2017 12:31:30 -0400 Received: from relmlor2.renesas.com ([210.160.252.172]:24823 "EHLO relmlie1.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751171AbdJDQb3 (ORCPT ); Wed, 4 Oct 2017 12:31:29 -0400 Received: from unknown (HELO relmlir2.idc.renesas.com) ([10.200.68.152]) by relmlie1.idc.renesas.com with ESMTP; 05 Oct 2017 01:31:27 +0900 Received: from relmlii1.idc.renesas.com (relmlii1.idc.renesas.com [10.200.68.65]) by relmlir2.idc.renesas.com (Postfix) with ESMTP id 113734188A; Thu, 5 Oct 2017 01:31:27 +0900 (JST) X-IronPort-AV: E=Sophos;i="5.42,477,1500908400"; d="scan'208";a="258520791" Received: from unknown (HELO rtamta01.rta.renesas.com) ([143.103.48.75]) by relmlii1.idc.renesas.com with ESMTP; 05 Oct 2017 01:31:25 +0900 Received: from localhost.localdomain (unknown [172.27.49.219]) by rtamta01.rta.renesas.com (Postfix) with ESMTP id 8FF6B1C4; Wed, 4 Oct 2017 16:31:21 +0000 (UTC) From: Chris Brandt To: Linus Walleij , Rob Herring , Mark Rutland , Geert Uytterhoeven Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Simon Horman , Jacopo Mondi , Chris Brandt Subject: [PATCH v2 1/2] pinctrl: rza1: add support for RZ/A1L Date: Wed, 4 Oct 2017 11:31:10 -0500 Message-Id: <20171004163111.54600-2-chris.brandt@renesas.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171004163111.54600-1-chris.brandt@renesas.com> References: <20171004163111.54600-1-chris.brandt@renesas.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Aspects like the number of ports and the location where peripherals are brought out differ between the RZ/A1H and RZ/A1L. Signed-off-by: Chris Brandt Reviewed-by: Jacopo Mondi --- v2: * added Reviewed-by --- drivers/pinctrl/pinctrl-rza1.c | 134 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 134 insertions(+) diff --git a/drivers/pinctrl/pinctrl-rza1.c b/drivers/pinctrl/pinctrl-rza1.c index 04d058706b80..717c0f4449a0 100644 --- a/drivers/pinctrl/pinctrl-rza1.c +++ b/drivers/pinctrl/pinctrl-rza1.c @@ -302,6 +302,134 @@ static const struct rza1_pinmux_conf rza1h_pmx_conf = { .swio_entries = rza1h_swio_entries, }; +/* ---------------------------------------------------------------------------- + * RZ/A1L (r7s72102) pinmux flags + */ + +static const struct rza1_bidir_pin rza1l_bidir_pins_p1[] = { + { .pin = 0, .func = 1 }, + { .pin = 1, .func = 1 }, + { .pin = 2, .func = 1 }, + { .pin = 3, .func = 1 }, + { .pin = 4, .func = 1 }, + { .pin = 5, .func = 1 }, + { .pin = 6, .func = 1 }, + { .pin = 7, .func = 1 }, +}; + +static const struct rza1_bidir_pin rza1l_bidir_pins_p3[] = { + { .pin = 0, .func = 2 }, + { .pin = 1, .func = 2 }, + { .pin = 2, .func = 2 }, + { .pin = 4, .func = 2 }, + { .pin = 5, .func = 2 }, + { .pin = 10, .func = 2 }, + { .pin = 11, .func = 2 }, + { .pin = 12, .func = 2 }, + { .pin = 13, .func = 2 }, +}; + +static const struct rza1_bidir_pin rza1l_bidir_pins_p4[] = { + { .pin = 1, .func = 4 }, + { .pin = 2, .func = 2 }, + { .pin = 3, .func = 2 }, + { .pin = 6, .func = 2 }, + { .pin = 7, .func = 2 }, +}; + +static const struct rza1_bidir_pin rza1l_bidir_pins_p5[] = { + { .pin = 0, .func = 1 }, + { .pin = 1, .func = 1 }, + { .pin = 2, .func = 1 }, + { .pin = 3, .func = 1 }, + { .pin = 4, .func = 1 }, + { .pin = 5, .func = 1 }, + { .pin = 6, .func = 1 }, + { .pin = 7, .func = 1 }, + { .pin = 8, .func = 1 }, + { .pin = 9, .func = 1 }, + { .pin = 10, .func = 1 }, + { .pin = 11, .func = 1 }, + { .pin = 12, .func = 1 }, + { .pin = 13, .func = 1 }, + { .pin = 14, .func = 1 }, + { .pin = 15, .func = 1 }, + { .pin = 0, .func = 2 }, + { .pin = 1, .func = 2 }, + { .pin = 2, .func = 2 }, + { .pin = 3, .func = 2 }, +}; + +static const struct rza1_bidir_pin rza1l_bidir_pins_p6[] = { + { .pin = 0, .func = 1 }, + { .pin = 1, .func = 1 }, + { .pin = 2, .func = 1 }, + { .pin = 3, .func = 1 }, + { .pin = 4, .func = 1 }, + { .pin = 5, .func = 1 }, + { .pin = 6, .func = 1 }, + { .pin = 7, .func = 1 }, + { .pin = 8, .func = 1 }, + { .pin = 9, .func = 1 }, + { .pin = 10, .func = 1 }, + { .pin = 11, .func = 1 }, + { .pin = 12, .func = 1 }, + { .pin = 13, .func = 1 }, + { .pin = 14, .func = 1 }, + { .pin = 15, .func = 1 }, +}; + +static const struct rza1_bidir_pin rza1l_bidir_pins_p7[] = { + { .pin = 2, .func = 2 }, + { .pin = 3, .func = 2 }, + { .pin = 5, .func = 2 }, + { .pin = 6, .func = 2 }, + { .pin = 7, .func = 2 }, + { .pin = 2, .func = 3 }, + { .pin = 3, .func = 3 }, + { .pin = 5, .func = 3 }, + { .pin = 6, .func = 3 }, + { .pin = 7, .func = 3 }, +}; + +static const struct rza1_bidir_pin rza1l_bidir_pins_p9[] = { + { .pin = 1, .func = 2 }, + { .pin = 0, .func = 3 }, + { .pin = 1, .func = 3 }, + { .pin = 3, .func = 3 }, + { .pin = 4, .func = 3 }, + { .pin = 5, .func = 3 }, +}; + +static const struct rza1_swio_pin rza1l_swio_pins[] = { + { .port = 2, .pin = 8, .func = 2, .input = 0 }, + { .port = 5, .pin = 6, .func = 3, .input = 0 }, + { .port = 6, .pin = 6, .func = 3, .input = 0 }, + { .port = 6, .pin = 10, .func = 3, .input = 0 }, + { .port = 7, .pin = 10, .func = 2, .input = 0 }, + { .port = 8, .pin = 2, .func = 3, .input = 0 }, +}; + +static const struct rza1_bidir_entry rza1l_bidir_entries[RZA1_NPORTS] = { + [1] = { ARRAY_SIZE(rza1l_bidir_pins_p1), rza1l_bidir_pins_p1 }, + [3] = { ARRAY_SIZE(rza1l_bidir_pins_p3), rza1l_bidir_pins_p3 }, + [4] = { ARRAY_SIZE(rza1l_bidir_pins_p4), rza1l_bidir_pins_p4 }, + [5] = { ARRAY_SIZE(rza1l_bidir_pins_p4), rza1l_bidir_pins_p5 }, + [6] = { ARRAY_SIZE(rza1l_bidir_pins_p6), rza1l_bidir_pins_p6 }, + [7] = { ARRAY_SIZE(rza1l_bidir_pins_p7), rza1l_bidir_pins_p7 }, + [9] = { ARRAY_SIZE(rza1l_bidir_pins_p9), rza1l_bidir_pins_p9 }, +}; + +static const struct rza1_swio_entry rza1l_swio_entries[] = { + [0] = { ARRAY_SIZE(rza1h_swio_pins), rza1h_swio_pins }, +}; + +/* RZ/A1L (r7s72102x) pinmux flags table */ +static const struct rza1_pinmux_conf rza1l_pmx_conf = { + .bidir_entries = rza1l_bidir_entries, + .swio_entries = rza1l_swio_entries, +}; + /* ---------------------------------------------------------------------------- * RZ/A1 types */ @@ -1283,9 +1411,15 @@ static int rza1_pinctrl_probe(struct platform_device *pdev) static const struct of_device_id rza1_pinctrl_of_match[] = { { + /* RZ/A1H, RZ/A1M */ .compatible = "renesas,r7s72100-ports", .data = &rza1h_pmx_conf, }, + { + /* RZ/A1L */ + .compatible = "renesas,r7s72102-ports", + .data = &rza1l_pmx_conf, + }, { } }; From patchwork Wed Oct 4 16:31:11 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Brandt X-Patchwork-Id: 821396 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3y6hHT6tDLz9t2l for ; Thu, 5 Oct 2017 03:31:33 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751234AbdJDQbc (ORCPT ); Wed, 4 Oct 2017 12:31:32 -0400 Received: from relmlor2.renesas.com ([210.160.252.172]:24823 "EHLO relmlie1.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1750966AbdJDQba (ORCPT ); Wed, 4 Oct 2017 12:31:30 -0400 Received: from unknown (HELO relmlir2.idc.renesas.com) ([10.200.68.152]) by relmlie1.idc.renesas.com with ESMTP; 05 Oct 2017 01:31:29 +0900 Received: from relmlii2.idc.renesas.com (relmlii2.idc.renesas.com [10.200.68.66]) by relmlir2.idc.renesas.com (Postfix) with ESMTP id 43E604188E; Thu, 5 Oct 2017 01:31:29 +0900 (JST) X-IronPort-AV: E=Sophos;i="5.42,477,1500908400"; d="scan'208";a="259655655" Received: from unknown (HELO rtamta01.rta.renesas.com) ([143.103.48.75]) by relmlii2.idc.renesas.com with ESMTP; 05 Oct 2017 01:31:27 +0900 Received: from localhost.localdomain (unknown [172.27.49.219]) by rtamta01.rta.renesas.com (Postfix) with ESMTP id 95F341DB; Wed, 4 Oct 2017 16:31:22 +0000 (UTC) From: Chris Brandt To: Linus Walleij , Rob Herring , Mark Rutland , Geert Uytterhoeven Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Simon Horman , Jacopo Mondi , Chris Brandt Subject: [PATCH v2 2/2] dt-bindings: pinctrl: add support for RZ/A1M and RZ/A1L Date: Wed, 4 Oct 2017 11:31:11 -0500 Message-Id: <20171004163111.54600-3-chris.brandt@renesas.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171004163111.54600-1-chris.brandt@renesas.com> References: <20171004163111.54600-1-chris.brandt@renesas.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Describe how to specify RZ/A1M and RZ/A1L devices. Signed-off-by: Chris Brandt Reviewed-by: Geert Uytterhoeven --- v2: * Added description for RZ/A1M --- Documentation/devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt index 43e21474528a..f2fc86f8dbab 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt @@ -13,7 +13,9 @@ Pin controller node Required properties: - compatible - this shall be "renesas,r7s72100-ports". + this shall be "renesas,r7s72100-ports" for RZ/A1H, "renesas,r7s72101-ports" + with a fallback of "renesas,r7s72100-ports" for RZ/A1M (as A1M is compatible + with A1H), or "renesas,r7s72102-ports" for RZ/A1L - reg address base and length of the memory area where the pin controller