From patchwork Tue Aug 28 06:24:59 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Janine Hagemann X-Patchwork-Id: 962733 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=phytec.de Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 41zzJj2jPxz9s2P for ; Tue, 28 Aug 2018 16:25:25 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id C5B32C21DCA; Tue, 28 Aug 2018 06:25:15 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id C3D9AC21C3F; Tue, 28 Aug 2018 06:25:12 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 49B28C21C57; Tue, 28 Aug 2018 06:25:11 +0000 (UTC) Received: from root.phytec.de (mail.x-arc.co.uk [217.6.246.34]) by lists.denx.de (Postfix) with ESMTP id 05215C21C29 for ; Tue, 28 Aug 2018 06:25:11 +0000 (UTC) Received: from idefix.phytec.de (idefix.phytec.de [172.16.0.10]) by root.phytec.de (Postfix) with ESMTP id 89049A003D5; Tue, 28 Aug 2018 08:25:48 +0200 (CEST) Received: from augenblix.phytec.de ([172.16.0.56]) by idefix.phytec.de (IBM Domino Release 9.0.1FP7) with ESMTP id 2018082808251043-807287 ; Tue, 28 Aug 2018 08:25:10 +0200 From: Janine Hagemann To: u-boot@lists.denx.de, grygorii.strashko@ti.com, albert.u.boot@aribaud.net, sjg@chromium.org, philipp.tomisch@theobram-systems.com, w.egorov@phytec.de, joe.hershberger@ni.com Date: Tue, 28 Aug 2018 08:24:59 +0200 Message-Id: <1535437505-32297-2-git-send-email-j.hagemann@phytec.de> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1535437505-32297-1-git-send-email-j.hagemann@phytec.de> References: <1535437505-32297-1-git-send-email-j.hagemann@phytec.de> X-MIMETrack: Itemize by SMTP Server on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 28.08.2018 08:25:10, Serialize by Router on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 28.08.2018 08:25:10, Serialize complete at 28.08.2018 08:25:10 X-TNEFEvaluated: 1 Subject: [U-Boot] [PATCH v4 1/7] arch: arm: mach-rockchip: rk3288: Enable regulators in board_init X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Use regulators_enable_boot_on() to init all the regulators with regulator-boot-on property. This is relevant for all rk3288-boards. Signed-off-by: Wadim Egorov Signed-off-by: Janine Hagemann --- v4: No changes --- arch/arm/mach-rockchip/rk3288-board.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-rockchip/rk3288-board.c b/arch/arm/mach-rockchip/rk3288-board.c index 9c4f7f2..067b988 100644 --- a/arch/arm/mach-rockchip/rk3288-board.c +++ b/arch/arm/mach-rockchip/rk3288-board.c @@ -132,12 +132,6 @@ static int veyron_init(void) if (ret) return ret; - ret = regulators_enable_boot_on(false); - if (ret) { - debug("%s: Cannot enable boot on regulators\n", __func__); - return ret; - } - return 0; } #endif @@ -175,6 +169,12 @@ err: #else int ret; + ret = regulators_enable_boot_on(false); + if (ret) { + debug("%s: Cannot enable boot on regulator\n", __func__); + return ret; + } + /* We do some SoC one time setting here */ if (!fdt_node_check_compatible(gd->fdt_blob, 0, "google,veyron")) { ret = veyron_init(); From patchwork Tue Aug 28 06:25:00 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Janine Hagemann X-Patchwork-Id: 962736 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=phytec.de Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 41zzMh0wK8z9s2P for ; Tue, 28 Aug 2018 16:28:00 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id C16ADC21D56; Tue, 28 Aug 2018 06:25:53 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 0737AC21DD4; Tue, 28 Aug 2018 06:25:14 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 70C53C21C3F; Tue, 28 Aug 2018 06:25:11 +0000 (UTC) Received: from root.phytec.de (mail.visioncatalog.de [217.6.246.34]) by lists.denx.de (Postfix) with ESMTP id 1ECB2C21C3F for ; Tue, 28 Aug 2018 06:25:11 +0000 (UTC) Received: from idefix.phytec.de (idefix.phytec.de [172.16.0.10]) by root.phytec.de (Postfix) with ESMTP id BFA75A00653; Tue, 28 Aug 2018 08:25:48 +0200 (CEST) Received: from augenblix.phytec.de ([172.16.0.56]) by idefix.phytec.de (IBM Domino Release 9.0.1FP7) with ESMTP id 2018082808251066-807288 ; Tue, 28 Aug 2018 08:25:10 +0200 From: Janine Hagemann To: u-boot@lists.denx.de, grygorii.strashko@ti.com, albert.u.boot@aribaud.net, sjg@chromium.org, philipp.tomisch@theobram-systems.com, w.egorov@phytec.de, joe.hershberger@ni.com Date: Tue, 28 Aug 2018 08:25:00 +0200 Message-Id: <1535437505-32297-3-git-send-email-j.hagemann@phytec.de> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1535437505-32297-1-git-send-email-j.hagemann@phytec.de> References: <1535437505-32297-1-git-send-email-j.hagemann@phytec.de> X-MIMETrack: Itemize by SMTP Server on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 28.08.2018 08:25:10, Serialize by Router on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 28.08.2018 08:25:10, Serialize complete at 28.08.2018 08:25:10 X-TNEFEvaluated: 1 Subject: [U-Boot] [PATCH v4 2/7] config: phycore-rk3288_defconfig: add PHY_TI X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" add PHY_TI to support dp83867 Signed-off-by: Janine Hagemann --- v4: No changes --- configs/phycore-rk3288_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/phycore-rk3288_defconfig b/configs/phycore-rk3288_defconfig index b81b5e6..340ba5d 100644 --- a/configs/phycore-rk3288_defconfig +++ b/configs/phycore-rk3288_defconfig @@ -54,6 +54,7 @@ CONFIG_MISC=y CONFIG_I2C_EEPROM=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_PHY_TI=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y From patchwork Tue Aug 28 06:25:01 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Janine Hagemann X-Patchwork-Id: 962742 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=phytec.de Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 41zzQZ1vqLz9s2P for ; Tue, 28 Aug 2018 16:30:30 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id E5C40C21C3F; Tue, 28 Aug 2018 06:26:10 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id B5F31C21C29; Tue, 28 Aug 2018 06:25:14 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id C202FC21C57; Tue, 28 Aug 2018 06:25:11 +0000 (UTC) Received: from root.phytec.de (mail.visioncatalog.de [217.6.246.34]) by lists.denx.de (Postfix) with ESMTP id 6D8B9C21C29 for ; Tue, 28 Aug 2018 06:25:11 +0000 (UTC) Received: from idefix.phytec.de (idefix.phytec.de [172.16.0.10]) by root.phytec.de (Postfix) with ESMTP id 1B86DA006D7; Tue, 28 Aug 2018 08:25:49 +0200 (CEST) Received: from augenblix.phytec.de ([172.16.0.56]) by idefix.phytec.de (IBM Domino Release 9.0.1FP7) with ESMTP id 2018082808251093-807289 ; Tue, 28 Aug 2018 08:25:10 +0200 From: Janine Hagemann To: u-boot@lists.denx.de, grygorii.strashko@ti.com, albert.u.boot@aribaud.net, sjg@chromium.org, philipp.tomisch@theobram-systems.com, w.egorov@phytec.de, joe.hershberger@ni.com Date: Tue, 28 Aug 2018 08:25:01 +0200 Message-Id: <1535437505-32297-4-git-send-email-j.hagemann@phytec.de> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1535437505-32297-1-git-send-email-j.hagemann@phytec.de> References: <1535437505-32297-1-git-send-email-j.hagemann@phytec.de> X-MIMETrack: Itemize by SMTP Server on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 28.08.2018 08:25:11, Serialize by Router on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 28.08.2018 08:25:11, Serialize complete at 28.08.2018 08:25:11 X-TNEFEvaluated: 1 Subject: [U-Boot] [PATCH v4 3/7] drivers: net: designware: Add reading of DT phy-handle node X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add the ability to read the phy-handle node of the gmac. Upon reading this handle the phy-id can be stored based on the reg node in the DT. The phy-handle also needs to be stored and passed to the phy to access any phy data that is available. Signed-off-by: Janine Hagemann Acked-by: Joe Hershberger --- v4: Change used function from dev_set_of_offset( ) to offset_to_ofnode( ) --- drivers/net/designware.c | 11 ++++++++++- drivers/net/designware.h | 1 + 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/net/designware.c b/drivers/net/designware.c index 19db0a8..bba12f2 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -477,7 +477,7 @@ static int dw_phy_init(struct dw_eth_dev *priv, void *dev) { struct phy_device *phydev; int mask = 0xffffffff, ret; - + struct dw_eth_pdata *dw_pdata = dev_get_platdata(dev); #ifdef CONFIG_PHY_ADDR mask = 1 << CONFIG_PHY_ADDR; #endif @@ -496,6 +496,11 @@ static int dw_phy_init(struct dw_eth_dev *priv, void *dev) } phydev->advertising = phydev->supported; +#ifdef CONFIG_DM_ETH + if (dw_pdata->phy_of_handle) + phydev->node = offset_to_ofnode(dw_pdata->phy_of_handle); +#endif + priv->phydev = phydev; phy_config(phydev); @@ -803,6 +808,7 @@ int designware_eth_ofdata_to_platdata(struct udevice *dev) int reset_flags = GPIOD_IS_OUT; #endif int ret = 0; + int node = dev_of_offset(dev); pdata->iobase = dev_read_addr(dev); pdata->phy_interface = -1; @@ -814,6 +820,9 @@ int designware_eth_ofdata_to_platdata(struct udevice *dev) return -EINVAL; } + dw_pdata->phy_of_handle = fdtdec_lookup_phandle(gd->fdt_blob, node, + "phy-handle"); + pdata->max_speed = dev_read_u32_default(dev, "max-speed", 0); #ifdef CONFIG_DM_GPIO diff --git a/drivers/net/designware.h b/drivers/net/designware.h index dea12b7..a6b0443 100644 --- a/drivers/net/designware.h +++ b/drivers/net/designware.h @@ -255,6 +255,7 @@ extern const struct eth_ops designware_eth_ops; struct dw_eth_pdata { struct eth_pdata eth_pdata; u32 reset_delays[3]; + int phy_of_handle; }; int designware_eth_init(struct dw_eth_dev *priv, u8 *enetaddr); From patchwork Tue Aug 28 06:25:02 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Janine Hagemann X-Patchwork-Id: 962737 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=phytec.de Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 41zzN56nkpz9s2P for ; Tue, 28 Aug 2018 16:28:21 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 80677C21DFA; Tue, 28 Aug 2018 06:26:49 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 85614C21DAF; Tue, 28 Aug 2018 06:25:16 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 14F9BC21C3F; Tue, 28 Aug 2018 06:25:11 +0000 (UTC) Received: from root.phytec.de (mail.phycard.de [217.6.246.34]) by lists.denx.de (Postfix) with ESMTP id B07AFC21C3F for ; Tue, 28 Aug 2018 06:25:11 +0000 (UTC) Received: from idefix.phytec.de (idefix.phytec.de [172.16.0.10]) by root.phytec.de (Postfix) with ESMTP id 5B0C0A006ED; Tue, 28 Aug 2018 08:25:49 +0200 (CEST) Received: from augenblix.phytec.de ([172.16.0.56]) by idefix.phytec.de (IBM Domino Release 9.0.1FP7) with ESMTP id 2018082808251118-807290 ; Tue, 28 Aug 2018 08:25:11 +0200 From: Janine Hagemann To: u-boot@lists.denx.de, grygorii.strashko@ti.com, albert.u.boot@aribaud.net, sjg@chromium.org, philipp.tomisch@theobram-systems.com, w.egorov@phytec.de, joe.hershberger@ni.com Date: Tue, 28 Aug 2018 08:25:02 +0200 Message-Id: <1535437505-32297-5-git-send-email-j.hagemann@phytec.de> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1535437505-32297-1-git-send-email-j.hagemann@phytec.de> References: <1535437505-32297-1-git-send-email-j.hagemann@phytec.de> X-MIMETrack: Itemize by SMTP Server on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 28.08.2018 08:25:11, Serialize by Router on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 28.08.2018 08:25:11, Serialize complete at 28.08.2018 08:25:11 X-TNEFEvaluated: 1 Subject: [U-Boot] [PATCH v4 4/7] ARM: dts: rockchip: ADD dp83867 CLK_OUT muxing X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The CLK_O_SEL default is synchronus to XI input clock, which is 25 MHz. Set CLK_O_SEL to channel A transmit clock so we have 125 MHz on CLK_OUT. Signed-off-by: Janine Hagemann --- v4: No changes --- arch/arm/dts/rk3288-phycore-som.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/dts/rk3288-phycore-som.dtsi b/arch/arm/dts/rk3288-phycore-som.dtsi index 02d1196..2dba0aa 100644 --- a/arch/arm/dts/rk3288-phycore-som.dtsi +++ b/arch/arm/dts/rk3288-phycore-som.dtsi @@ -191,6 +191,7 @@ ti,tx-internal-delay = ; ti,fifo-depth = ; enet-phy-lane-no-swap; + ti,clk-output-sel = ; }; }; }; From patchwork Tue Aug 28 06:25:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Janine Hagemann X-Patchwork-Id: 962735 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=phytec.de Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 41zzLc6mMgz9s2P for ; Tue, 28 Aug 2018 16:27:04 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 973F8C21D8E; Tue, 28 Aug 2018 06:26:30 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: ** X-Spam-Status: No, score=2.5 required=5.0 tests=DRUGS_MUSCLE autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id A681CC21DED; Tue, 28 Aug 2018 06:25:15 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id F3FB4C21C29; Tue, 28 Aug 2018 06:25:11 +0000 (UTC) Received: from root.phytec.de (mail.phycard.co.uk [217.6.246.34]) by lists.denx.de (Postfix) with ESMTP id A7A80C21C27 for ; Tue, 28 Aug 2018 06:25:11 +0000 (UTC) Received: from idefix.phytec.de (idefix.phytec.de [172.16.0.10]) by root.phytec.de (Postfix) with ESMTP id 5383AA006EC; Tue, 28 Aug 2018 08:25:49 +0200 (CEST) Received: from augenblix.phytec.de ([172.16.0.56]) by idefix.phytec.de (IBM Domino Release 9.0.1FP7) with ESMTP id 2018082808251143-807291 ; Tue, 28 Aug 2018 08:25:11 +0200 From: Janine Hagemann To: u-boot@lists.denx.de, grygorii.strashko@ti.com, albert.u.boot@aribaud.net, sjg@chromium.org, philipp.tomisch@theobram-systems.com, w.egorov@phytec.de, joe.hershberger@ni.com Date: Tue, 28 Aug 2018 08:25:03 +0200 Message-Id: <1535437505-32297-6-git-send-email-j.hagemann@phytec.de> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1535437505-32297-1-git-send-email-j.hagemann@phytec.de> References: <1535437505-32297-1-git-send-email-j.hagemann@phytec.de> X-MIMETrack: Itemize by SMTP Server on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 28.08.2018 08:25:11, Serialize by Router on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 28.08.2018 08:25:11, Serialize complete at 28.08.2018 08:25:11 X-TNEFEvaluated: 1 Subject: [U-Boot] [PATCH v4 5/7] rockchip: rk3288-phycore: set flash1 iodomain to 1.8V X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This pin is supplied by 1.8V, but the default iodomain setting is 3.3V. Signed-off-by: Janine Hagemann --- v4: No changes --- board/phytec/phycore_rk3288/phycore-rk3288.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/board/phytec/phycore_rk3288/phycore-rk3288.c b/board/phytec/phycore_rk3288/phycore-rk3288.c index ffe1833..8c1844a 100644 --- a/board/phytec/phycore_rk3288/phycore-rk3288.c +++ b/board/phytec/phycore_rk3288/phycore-rk3288.c @@ -11,6 +11,11 @@ #include #include #include +#include +#include +#include +#include +#include #include "som.h" static int valid_rk3288_som(struct rk3288_som *som) @@ -27,6 +32,15 @@ static int valid_rk3288_som(struct rk3288_som *som) return hw == som->bs; } +static void setup_iodomain(void) +{ + const u32 GRF_IO_VSEL_FLASH1_SHIFT = 3; + struct rk3288_grf *grf = + syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + + rk_setreg(&grf->io_vsel, 1 << GRF_IO_VSEL_FLASH1_SHIFT); +} + int rk_board_late_init(void) { int ret; @@ -34,6 +48,8 @@ int rk_board_late_init(void) struct rk3288_som opt; int off; + setup_iodomain(); + /* Get the identificatioin page of M24C32-D EEPROM */ off = fdt_path_offset(gd->fdt_blob, "eeprom0"); if (off < 0) { From patchwork Tue Aug 28 06:25:04 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Janine Hagemann X-Patchwork-Id: 962745 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=phytec.de Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 41zzRQ2bXTz9s2P for ; Tue, 28 Aug 2018 16:31:14 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 031C3C21E18; Tue, 28 Aug 2018 06:27:07 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 7D80FC21C27; Tue, 28 Aug 2018 06:25:17 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 50641C21C29; Tue, 28 Aug 2018 06:25:12 +0000 (UTC) Received: from root.phytec.de (mail.rapiddevelopmentkit.de [217.6.246.34]) by lists.denx.de (Postfix) with ESMTP id 08ED3C21C27 for ; Tue, 28 Aug 2018 06:25:12 +0000 (UTC) Received: from idefix.phytec.de (idefix.phytec.de [172.16.0.10]) by root.phytec.de (Postfix) with ESMTP id A368EA0076F; Tue, 28 Aug 2018 08:25:49 +0200 (CEST) Received: from augenblix.phytec.de ([172.16.0.56]) by idefix.phytec.de (IBM Domino Release 9.0.1FP7) with ESMTP id 2018082808251146-807292 ; Tue, 28 Aug 2018 08:25:11 +0200 From: Janine Hagemann To: u-boot@lists.denx.de, grygorii.strashko@ti.com, albert.u.boot@aribaud.net, sjg@chromium.org, philipp.tomisch@theobram-systems.com, w.egorov@phytec.de, joe.hershberger@ni.com Date: Tue, 28 Aug 2018 08:25:04 +0200 Message-Id: <1535437505-32297-7-git-send-email-j.hagemann@phytec.de> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1535437505-32297-1-git-send-email-j.hagemann@phytec.de> References: <1535437505-32297-1-git-send-email-j.hagemann@phytec.de> X-MIMETrack: Itemize by SMTP Server on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 28.08.2018 08:25:11, Serialize by Router on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 28.08.2018 08:25:11, Serialize complete at 28.08.2018 08:25:11 X-TNEFEvaluated: 1 Subject: [U-Boot] [PATCH v4 6/7] net: gmac_rockchip: Fix a register write in rk3328_gmac_set_to_rgmii X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" We have to use RK3328_RXCLK_DLY_ENA_GMAC_ENABLE instead of RK3328_RXCLK_DLY_ENA_GMAC_MASK in rk3328_gmac_set_to_rgmii() to enable the RX delay. The MASK was used in a wrong way. Signed-off-by: Janine Hagemann Reviewed-by: Philipp Tomisch Acked-by: Joe Hershberger --- v4: No changes --- drivers/net/gmac_rockchip.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c index 30a24d1..0f91731 100644 --- a/drivers/net/gmac_rockchip.c +++ b/drivers/net/gmac_rockchip.c @@ -350,7 +350,7 @@ static void rk3328_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) RK3328_RXCLK_DLY_ENA_GMAC_MASK | RK3328_TXCLK_DLY_ENA_GMAC_MASK, RK3328_GMAC_PHY_INTF_SEL_RGMII | - RK3328_RXCLK_DLY_ENA_GMAC_MASK | + RK3328_RXCLK_DLY_ENA_GMAC_ENABLE | RK3328_TXCLK_DLY_ENA_GMAC_ENABLE); rk_clrsetreg(&grf->mac_con[0], From patchwork Tue Aug 28 06:25:05 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Janine Hagemann X-Patchwork-Id: 962747 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=phytec.de Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 41zzT06hmTz9s2P for ; Tue, 28 Aug 2018 16:32:36 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id A03B3C21E2C; Tue, 28 Aug 2018 06:27:25 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 62DC5C21E2B; Tue, 28 Aug 2018 06:25:18 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 87364C21C27; Tue, 28 Aug 2018 06:25:12 +0000 (UTC) Received: from root.phytec.de (mail.tricorecenter.de [217.6.246.34]) by lists.denx.de (Postfix) with ESMTP id 370E6C21C57 for ; Tue, 28 Aug 2018 06:25:12 +0000 (UTC) Received: from idefix.phytec.de (idefix.phytec.de [172.16.0.10]) by root.phytec.de (Postfix) with ESMTP id D8BABA00832; Tue, 28 Aug 2018 08:25:49 +0200 (CEST) Received: from augenblix.phytec.de ([172.16.0.56]) by idefix.phytec.de (IBM Domino Release 9.0.1FP7) with ESMTP id 2018082808251171-807293 ; Tue, 28 Aug 2018 08:25:11 +0200 From: Janine Hagemann To: u-boot@lists.denx.de, grygorii.strashko@ti.com, albert.u.boot@aribaud.net, sjg@chromium.org, philipp.tomisch@theobram-systems.com, w.egorov@phytec.de, joe.hershberger@ni.com Date: Tue, 28 Aug 2018 08:25:05 +0200 Message-Id: <1535437505-32297-8-git-send-email-j.hagemann@phytec.de> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1535437505-32297-1-git-send-email-j.hagemann@phytec.de> References: <1535437505-32297-1-git-send-email-j.hagemann@phytec.de> X-MIMETrack: Itemize by SMTP Server on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 28.08.2018 08:25:11, Serialize by Router on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 28.08.2018 08:25:12, Serialize complete at 28.08.2018 08:25:12 X-TNEFEvaluated: 1 Subject: [U-Boot] [PATCH v4 7/7] net: gmac_rockchip: Add handeling for RGMII_ID/RXID/TXID X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Using PHY internal delays in combination with the phy-mode rgmii-id/rxid/txid was not possible. Only rgmii was supported. Now we can disable rockchip's gmac delay lines and also use rgmii-id/rxid/txid. Based on commit eaf70ad14cbb ("net: stmmac: dwmac-rk: Add handling for RGMII_ID/RXID/TXID") for mainline linux kernel. Signed-off-by: Janine Hagemann Acked-by: Joe Hershberger Reviewed-by: David Wu --- v4: No changes --- drivers/net/gmac_rockchip.c | 80 +++++++++++++++++++++++++++++++++++---------- 1 file changed, 63 insertions(+), 17 deletions(-) diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c index 0f91731..c01ae75 100644 --- a/drivers/net/gmac_rockchip.c +++ b/drivers/net/gmac_rockchip.c @@ -24,6 +24,11 @@ #include #include "designware.h" +DECLARE_GLOBAL_DATA_PTR; +#define DELAY_ENABLE(soc, tx, rx) \ + (((tx) ? soc##_TXCLK_DLY_ENA_GMAC_ENABLE : soc##_TXCLK_DLY_ENA_GMAC_DISABLE) | \ + ((rx) ? soc##_RXCLK_DLY_ENA_GMAC_ENABLE : soc##_RXCLK_DLY_ENA_GMAC_DISABLE)) + /* * Platform data for the gmac * @@ -286,8 +291,7 @@ static void rk3228_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) RK3228_RXCLK_DLY_ENA_GMAC_MASK | RK3228_TXCLK_DLY_ENA_GMAC_MASK, RK3228_GMAC_PHY_INTF_SEL_RGMII | - RK3228_RXCLK_DLY_ENA_GMAC_ENABLE | - RK3228_TXCLK_DLY_ENA_GMAC_ENABLE); + DELAY_ENABLE(RK3228, pdata->tx_delay, pdata->rx_delay)); rk_clrsetreg(&grf->mac_con[0], RK3228_CLK_RX_DL_CFG_GMAC_MASK | @@ -310,8 +314,7 @@ static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) RK3288_TXCLK_DLY_ENA_GMAC_MASK | RK3288_CLK_RX_DL_CFG_GMAC_MASK | RK3288_CLK_TX_DL_CFG_GMAC_MASK, - RK3288_RXCLK_DLY_ENA_GMAC_ENABLE | - RK3288_TXCLK_DLY_ENA_GMAC_ENABLE | + DELAY_ENABLE(RK3288, pdata->rx_delay, pdata->tx_delay) | pdata->rx_delay << RK3288_CLK_RX_DL_CFG_GMAC_SHIFT | pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT); } @@ -350,8 +353,7 @@ static void rk3328_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) RK3328_RXCLK_DLY_ENA_GMAC_MASK | RK3328_TXCLK_DLY_ENA_GMAC_MASK, RK3328_GMAC_PHY_INTF_SEL_RGMII | - RK3328_RXCLK_DLY_ENA_GMAC_ENABLE | - RK3328_TXCLK_DLY_ENA_GMAC_ENABLE); + DELAY_ENABLE(RK3328, pdata->tx_delay, pdata->rx_delay)); rk_clrsetreg(&grf->mac_con[0], RK3328_CLK_RX_DL_CFG_GMAC_MASK | @@ -392,8 +394,7 @@ static void rk3368_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) RK3368_TXCLK_DLY_ENA_GMAC_MASK | RK3368_CLK_RX_DL_CFG_GMAC_MASK | RK3368_CLK_TX_DL_CFG_GMAC_MASK, - RK3368_RXCLK_DLY_ENA_GMAC_ENABLE | - RK3368_TXCLK_DLY_ENA_GMAC_ENABLE | + DELAY_ENABLE(RK3368, pdata->tx_delay, pdata->rx_delay) | pdata->rx_delay << RK3368_CLK_RX_DL_CFG_GMAC_SHIFT | pdata->tx_delay << RK3368_CLK_TX_DL_CFG_GMAC_SHIFT); } @@ -413,8 +414,7 @@ static void rk3399_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) RK3399_TXCLK_DLY_ENA_GMAC_MASK | RK3399_CLK_RX_DL_CFG_GMAC_MASK | RK3399_CLK_TX_DL_CFG_GMAC_MASK, - RK3399_RXCLK_DLY_ENA_GMAC_ENABLE | - RK3399_TXCLK_DLY_ENA_GMAC_ENABLE | + DELAY_ENABLE(RK3399, pdata->tx_delay, pdata->rx_delay) | pdata->rx_delay << RK3399_CLK_RX_DL_CFG_GMAC_SHIFT | pdata->tx_delay << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT); } @@ -451,40 +451,86 @@ static int gmac_rockchip_probe(struct udevice *dev) switch (eth_pdata->phy_interface) { case PHY_INTERFACE_MODE_RGMII: + /* Set to RGMII mode */ + if (ops->set_to_rgmii) + ops->set_to_rgmii(pdata); + else + return -EPERM; + /* * If the gmac clock is from internal pll, need to set and * check the return value for gmac clock at RGMII mode. If * the gmac clock is from external source, the clock rate * is not set, because of it is bypassed. */ + if (!pdata->clock_input) { rate = clk_set_rate(&clk, 125000000); if (rate != 125000000) return -EINVAL; } + break; + case PHY_INTERFACE_MODE_RGMII_ID: /* Set to RGMII mode */ - if (ops->set_to_rgmii) + if (ops->set_to_rgmii) { + pdata->tx_delay = 0; + pdata->rx_delay = 0; ops->set_to_rgmii(pdata); - else + } else return -EPERM; - break; - case PHY_INTERFACE_MODE_RMII: - /* The commet is the same as RGMII mode */ if (!pdata->clock_input) { - rate = clk_set_rate(&clk, 50000000); - if (rate != 50000000) + rate = clk_set_rate(&clk, 125000000); + if (rate != 125000000) return -EINVAL; } + break; + case PHY_INTERFACE_MODE_RMII: /* Set to RMII mode */ if (ops->set_to_rmii) ops->set_to_rmii(pdata); else return -EPERM; + if (!pdata->clock_input) { + rate = clk_set_rate(&clk, 50000000); + if (rate != 50000000) + return -EINVAL; + } + break; + + case PHY_INTERFACE_MODE_RGMII_RXID: + /* Set to RGMII_RXID mode */ + if (ops->set_to_rgmii) { + pdata->tx_delay = 0; + ops->set_to_rgmii(pdata); + } else + return -EPERM; + + if (!pdata->clock_input) { + rate = clk_set_rate(&clk, 125000000); + if (rate != 125000000) + return -EINVAL; + } break; + + case PHY_INTERFACE_MODE_RGMII_TXID: + /* Set to RGMII_TXID mode */ + if (ops->set_to_rgmii) { + pdata->rx_delay = 0; + ops->set_to_rgmii(pdata); + } else + return -EPERM; + + if (!pdata->clock_input) { + rate = clk_set_rate(&clk, 125000000); + if (rate != 125000000) + return -EINVAL; + } + break; + default: debug("NO interface defined!\n"); return -ENXIO;