From patchwork Tue Aug 21 14:38:52 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?TWljaGFsIFZva8OhxI0=?= X-Patchwork-Id: 960433 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=ysoft.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ysoft.com header.i=@ysoft.com header.b="eO5RyS1F"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 41vtfd57kJz9s5b for ; Wed, 22 Aug 2018 00:41:45 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727538AbeHUSCJ (ORCPT ); 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This can caue issues when inverted PWM polarity is needed. With inverted polarity a duty cycle = 0% corresponds to solid high level on the output. If the PWM is dissabled its output instantly goes to solid zero which corresponds to duty cycle = 100%. To have a trully inverted PWM output configure the PWM pad as a GPIO with pull-up. Then switch the pad to PWM output whenever non-zero duty cycle is needed. Signed-off-by: Michal Vokáč --- Documentation/devicetree/bindings/pwm/imx-pwm.txt | 44 +++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/Documentation/devicetree/bindings/pwm/imx-pwm.txt b/Documentation/devicetree/bindings/pwm/imx-pwm.txt index c61bdf8..3b1bc4c 100644 --- a/Documentation/devicetree/bindings/pwm/imx-pwm.txt +++ b/Documentation/devicetree/bindings/pwm/imx-pwm.txt @@ -14,6 +14,12 @@ See the clock consumer binding, Documentation/devicetree/bindings/clock/clock-bindings.txt - interrupts: The interrupt for the pwm controller +Optional properties: +- pinctrl: For i.MX27 and newer SoCs. Add extra pinctrl to configure the PWM + pin to gpio function. It allows control over the pin output level when the + PWM block is disabled. This is meant to be used if inverted polarity of the + PWM signal is required. See "Inverted PWM output" section bellow. + Example: pwm1: pwm@53fb4000 { @@ -25,3 +31,41 @@ pwm1: pwm@53fb4000 { clock-names = "ipg", "per"; interrupts = <61>; }; + +Inverted PWM output +------------------- + +The i.MX SoC has such limitation that whenever a pad is configured as a PWM +output, the output level is always zero volts when the PWM block is disabled. +The zero output level is actively driven by the output stage of the PWM block +and can not be overridden by pull-up. It also does not matter what PWM polarity +a PWM client (e.g. backlight) requested. + +To gain control of the PWM output level in disabled state two pinctrl states +can be used. The "default" state and the "pwm" state. In the default state the +PWM output is configured as a GPIO with pull-up. In the "pwm" state the output +is configured as a PWM output. This setup assures that the PWM output is at +the required level that corresponds to duty cycle = 0 when PWM is disabled. +E.g. at boot. + +Example: + +&pwm1 { + pinctrl-names = "default", "pwm"; + pinctrl-0 = <&pinctrl_backlight_gpio>; + pinctrl-1 = <&pinctrl_backlight_pwm>; +} + +pinctrl_backlight_gpio: pwm1grp-gpio { + fsl,pins = < + /* GPIO with 22kOhm pull-up */ + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0xF008 + >; +}; + +pinctrl_backlight_pwm: pwm1grp-pwm { + fsl,pins = < + /* PWM output */ + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x8 + >; +}; From patchwork Tue Aug 21 14:38:53 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?TWljaGFsIFZva8OhxI0=?= X-Patchwork-Id: 960437 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; 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b=edwEKXR4NGulil5x4upzFyjOoFN4hX3WQab8k6p71kzy7FgKuE/oc6IigjECcqunowoQzVYJSE8hYEVFC51RCV1neKAjA/VtXkrRUzcMXGvVvFe6E2qx1MtCuS2PWX10NFfn1djhqZLpPJkYE+eNCjw9yKygarAevSQpoZpUTJA= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Michal.Vokac@ysoft.com; Received: from iota-build.ysoft.local (89.24.100.190) by AM6PR04MB4661.eurprd04.prod.outlook.com (2603:10a6:20b:1b::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1059.21; Tue, 21 Aug 2018 14:41:07 +0000 From: =?utf-8?b?TWljaGFsIFZva8OhxI0=?= To: Thierry Reding , Rob Herring Cc: Mark Rutland , devicetree@vger.kernel.org, linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org, Lukasz Majewski , Fabio Estevam , =?utf-8?q?Lothar_Wa?= =?utf-8?b?w59tYW5u?= , =?utf-8?b?TWljaGFsIFZva8OhxI0=?= Subject: [RFC PATCH 2/2] pmw: imx: Configure output to GPIO in disabled state Date: Tue, 21 Aug 2018 16:38:53 +0200 Message-Id: <1534862333-27950-3-git-send-email-michal.vokac@ysoft.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1534862333-27950-1-git-send-email-michal.vokac@ysoft.com> References: <1534862333-27950-1-git-send-email-michal.vokac@ysoft.com> MIME-Version: 1.0 X-Originating-IP: [89.24.100.190] X-ClientProxiedBy: HE1PR0301CA0012.eurprd03.prod.outlook.com (2603:10a6:3:76::22) To AM6PR04MB4661.eurprd04.prod.outlook.com (2603:10a6:20b:1b::20) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 5c32565a-cafe-4227-b6c1-08d607742478 X-Microsoft-Antispam: BCL:0; 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This can cause issues when inverted PWM signal polarity is needed. Allow users to set a "default" pinctrl state that will be used when PWM is disabled and a "pwm" pinctrl state that will be used when PWM output is needed. As an example, with this a PWM controlled backlight with inversed signal polarity can be used in full brightness range. Without this the backlight could not be turned off as brightness = 0 disables the PWM and that in turn set output to 0V, that is full brightness. When the pinctrl states are not correctly specifid in DT the logic will work as before. Signed-off-by: Michal Vokáč --- drivers/pwm/pwm-imx.c | 56 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/drivers/pwm/pwm-imx.c b/drivers/pwm/pwm-imx.c index 1d5242c..6212c98 100644 --- a/drivers/pwm/pwm-imx.c +++ b/drivers/pwm/pwm-imx.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -52,10 +53,39 @@ struct imx_chip { void __iomem *mmio_base; struct pwm_chip chip; + + struct pinctrl *pinctrl; + struct pinctrl_state *pinctrl_pins_default; + struct pinctrl_state *pinctrl_pins_pwm; }; + #define to_imx_chip(chip) container_of(chip, struct imx_chip, chip) +static int imx_pwm_init_pinctrl_info(struct imx_chip *imx_chip, + struct platform_device *pdev) +{ + imx_chip->pinctrl = devm_pinctrl_get(&pdev->dev); + if (!imx_chip->pinctrl || IS_ERR(imx_chip->pinctrl)) { + dev_info(&pdev->dev, "can not get pinctrl\n"); + return PTR_ERR(imx_chip->pinctrl); + } + + imx_chip->pinctrl_pins_default = pinctrl_lookup_state(imx_chip->pinctrl, + PINCTRL_STATE_DEFAULT); + imx_chip->pinctrl_pins_pwm = pinctrl_lookup_state(imx_chip->pinctrl, + "pwm"); + + if (IS_ERR(imx_chip->pinctrl_pins_default) || + IS_ERR(imx_chip->pinctrl_pins_pwm)) { + dev_info(&pdev->dev, "PWM output mux information incomplete\n"); + devm_pinctrl_put(imx_chip->pinctrl); + imx_chip->pinctrl = NULL; + } + + return 0; +} + static int imx_pwm_config_v1(struct pwm_chip *chip, struct pwm_device *pwm, int duty_ns, int period_ns) { @@ -216,7 +246,29 @@ static int imx_pwm_apply_v2(struct pwm_chip *chip, struct pwm_device *pwm, cr |= MX3_PWMCR_POUTC; writel(cr, imx->mmio_base + MX3_PWMCR); + + /* + * If we are in charge of pinctrl then switch output to + * the PWM signal. + */ + if (imx->pinctrl) + pinctrl_select_state(imx->pinctrl, + imx->pinctrl_pins_pwm); } else if (cstate.enabled) { + /* + * PWM block will be disabled. Normally its output will go + * to 0 no matter what polarity is set. In case reversed PWM + * polarity is required reconfigure the output pin to GPIO to + * keep the output at the same level as for duty-cycle = 0. + * + * First switch the muxing and then disable the PWM. In that + * order we do not get unwanted logic level changes on the + * output. + */ + if (imx->pinctrl) + pinctrl_select_state(imx->pinctrl, + imx->pinctrl_pins_default); + writel(0, imx->mmio_base + MX3_PWMCR); clk_disable_unprepare(imx->clk_per); @@ -294,6 +346,10 @@ static int imx_pwm_probe(struct platform_device *pdev) imx->chip.of_pwm_n_cells = 3; } + ret = imx_pwm_init_pinctrl_info(imx, pdev); + if (ret) + return ret; + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); imx->mmio_base = devm_ioremap_resource(&pdev->dev, r); if (IS_ERR(imx->mmio_base))