From patchwork Sun Aug 12 18:46:23 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Ravnborg X-Patchwork-Id: 956708 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=ravnborg.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="p80Of31i"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 41pVzv5T5xz9sCD for ; Mon, 13 Aug 2018 06:38:03 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727883AbeHLVZj (ORCPT ); Sun, 12 Aug 2018 17:25:39 -0400 Received: from mail-ed1-f65.google.com ([209.85.208.65]:33607 "EHLO mail-ed1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727822AbeHLVZj (ORCPT ); Sun, 12 Aug 2018 17:25:39 -0400 Received: by mail-ed1-f65.google.com with SMTP id x5-v6so7188105edr.0; Sun, 12 Aug 2018 11:46:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=fZzCfApWbUHVLHbCuu+sUhX9ko7ThVKQdeTqUXMjBWk=; b=p80Of31iJ7KwpN1G69fn5qhruoZr8ieO6szjMd3QEsd6rKp0Y/X4hkHcxcRNTU3sNg NjBcJQ9OX/Ed0NgnRWbxfHQaA6FvUNty3EXEaDWFrYOpClt5W3zcgEJMjv5EpKwDE2hI SrbI+UFWqizPk3YHsv6fJQYOkpq0DX6IK4ucgAu70pFtI/UVOx4R+Dir3R42MJ2x/9tz P2AUBecpm0Z9GBflCNwwzswSzsZ9lMYR/A6nhFaGoee4CddRjmXjUv8aRxtsnhZAdfWD yHE0gjg7by8gqGBWxTnQWDDKc3FQ9XMcMhkZMDFCA2kTDPg2g0cyMg8rqIJBIwOYLazh yn7w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=fZzCfApWbUHVLHbCuu+sUhX9ko7ThVKQdeTqUXMjBWk=; b=GzVkp8tSl7SK1fsphN05Rs7uoFNKeU+CRv1HycYYl+jlEg6Jnp8fHnAxPgKlLCAHK9 967LGTI+mPpsM0K6kiBA2OdLJbZKa3pw8ZTNxkZQIXSlTDdqB+uHehW89nt+BfkLBxQ3 iQzLCCvHKGtYLzK7XIck9QEAWDxLcBu1sa90JQ31gB+n+oijwWWjvYCPzTD8ZTdGtCQU RJb68+XOY0qM7kd6SiLFWwc6YjH29CTXD10zkvPtieo7RgT+YROqxuso+2ppbtPslwL+ u214CFlC8xTlyhm467XcPBv6zbY4MaD8e23GxtNP5j1P1taVb/uM6wTFlDwlnZtVen5j wceg== X-Gm-Message-State: AOUpUlE6CJ68NYVYOzIyVfA2N7ovZJ1WF3aeV31yteoh/v419uAAothW 9t/drt0PTvYq56FzI+Scp9/bDsal7/w= X-Google-Smtp-Source: AA+uWPyEeQAVkxg1MKDXzkbn6kfqzlMKkMeq3QC/+qTCjPtwyh4uds/caV5ZFJ9AxUtyUONYtKcHww== X-Received: by 2002:a50:9356:: with SMTP id n22-v6mr18574793eda.206.1534099601539; Sun, 12 Aug 2018 11:46:41 -0700 (PDT) Received: from jupiter.lan (126.158-248-196.customer.lyse.net. [158.248.196.126]) by smtp.gmail.com with ESMTPSA id g14-v6sm5897941edm.25.2018.08.12.11.46.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 12 Aug 2018 11:46:40 -0700 (PDT) From: Sam Ravnborg To: Boris Brezillon , Rob Herring , Mark Rutland , Lee Jones , Nicolas Ferre , Alexandre Belloni Cc: Sam Ravnborg , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pwm@vger.kernel.org Subject: [PATCH v1 1/7] atmel-hlcdc: renamed directory to drm/atmel/ Date: Sun, 12 Aug 2018 20:46:23 +0200 Message-Id: <20180812184629.3808-1-sam@ravnborg.org> X-Mailer: git-send-email 2.12.0 In-Reply-To: <20180812184152.GA22343@ravnborg.org> References: <20180812184152.GA22343@ravnborg.org> Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org Use vendor name for directory, adding a suitable place for more atmel DRM drivers. Signed-off-by: Sam Ravnborg Cc: Boris Brezillon --- MAINTAINERS | 2 +- drivers/gpu/drm/Kconfig | 2 +- drivers/gpu/drm/Makefile | 2 +- drivers/gpu/drm/{atmel-hlcdc => atmel}/Kconfig | 6 ++++++ drivers/gpu/drm/{atmel-hlcdc => atmel}/Makefile | 0 drivers/gpu/drm/{atmel-hlcdc => atmel}/atmel_hlcdc_crtc.c | 0 drivers/gpu/drm/{atmel-hlcdc => atmel}/atmel_hlcdc_dc.c | 0 drivers/gpu/drm/{atmel-hlcdc => atmel}/atmel_hlcdc_dc.h | 0 drivers/gpu/drm/{atmel-hlcdc => atmel}/atmel_hlcdc_output.c | 0 drivers/gpu/drm/{atmel-hlcdc => atmel}/atmel_hlcdc_plane.c | 0 10 files changed, 9 insertions(+), 3 deletions(-) rename drivers/gpu/drm/{atmel-hlcdc => atmel}/Kconfig (83%) rename drivers/gpu/drm/{atmel-hlcdc => atmel}/Makefile (100%) rename drivers/gpu/drm/{atmel-hlcdc => atmel}/atmel_hlcdc_crtc.c (100%) rename drivers/gpu/drm/{atmel-hlcdc => atmel}/atmel_hlcdc_dc.c (100%) rename drivers/gpu/drm/{atmel-hlcdc => atmel}/atmel_hlcdc_dc.h (100%) rename drivers/gpu/drm/{atmel-hlcdc => atmel}/atmel_hlcdc_output.c (100%) rename drivers/gpu/drm/{atmel-hlcdc => atmel}/atmel_hlcdc_plane.c (100%) diff --git a/MAINTAINERS b/MAINTAINERS index 96e98e206b0d..09ce76a9a1dc 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4681,7 +4681,7 @@ DRM DRIVERS FOR ATMEL HLCDC M: Boris Brezillon L: dri-devel@lists.freedesktop.org S: Supported -F: drivers/gpu/drm/atmel-hlcdc/ +F: drivers/gpu/drm/atmel/atmel-hlcdc* F: Documentation/devicetree/bindings/display/atmel/ T: git git://anongit.freedesktop.org/drm/drm-misc diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig index 2a72d2feb76d..4130df0c0dba 100644 --- a/drivers/gpu/drm/Kconfig +++ b/drivers/gpu/drm/Kconfig @@ -232,7 +232,7 @@ source "drivers/gpu/drm/cirrus/Kconfig" source "drivers/gpu/drm/armada/Kconfig" -source "drivers/gpu/drm/atmel-hlcdc/Kconfig" +source "drivers/gpu/drm/atmel/Kconfig" source "drivers/gpu/drm/rcar-du/Kconfig" diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile index ef9f3dab287f..ce9829967128 100644 --- a/drivers/gpu/drm/Makefile +++ b/drivers/gpu/drm/Makefile @@ -76,7 +76,7 @@ obj-$(CONFIG_DRM_GMA500) += gma500/ obj-$(CONFIG_DRM_UDL) += udl/ obj-$(CONFIG_DRM_AST) += ast/ obj-$(CONFIG_DRM_ARMADA) += armada/ -obj-$(CONFIG_DRM_ATMEL_HLCDC) += atmel-hlcdc/ +obj-$(CONFIG_DRM_ATMEL) += atmel/ obj-$(CONFIG_DRM_RCAR_DU) += rcar-du/ obj-$(CONFIG_DRM_SHMOBILE) +=shmobile/ obj-y += omapdrm/ diff --git a/drivers/gpu/drm/atmel-hlcdc/Kconfig b/drivers/gpu/drm/atmel/Kconfig similarity index 83% rename from drivers/gpu/drm/atmel-hlcdc/Kconfig rename to drivers/gpu/drm/atmel/Kconfig index 32bcc4bad06a..7cd3862f9d18 100644 --- a/drivers/gpu/drm/atmel-hlcdc/Kconfig +++ b/drivers/gpu/drm/atmel/Kconfig @@ -1,6 +1,12 @@ +config DRM_ATMEL + bool + help + Enable Atmel DRM support + config DRM_ATMEL_HLCDC tristate "DRM Support for ATMEL HLCDC Display Controller" depends on DRM && OF && COMMON_CLK && MFD_ATMEL_HLCDC && ARM + select DRM_ATMEL select DRM_GEM_CMA_HELPER select DRM_KMS_HELPER select DRM_KMS_CMA_HELPER diff --git a/drivers/gpu/drm/atmel-hlcdc/Makefile b/drivers/gpu/drm/atmel/Makefile similarity index 100% rename from drivers/gpu/drm/atmel-hlcdc/Makefile rename to drivers/gpu/drm/atmel/Makefile diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c b/drivers/gpu/drm/atmel/atmel_hlcdc_crtc.c similarity index 100% rename from drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c rename to drivers/gpu/drm/atmel/atmel_hlcdc_crtc.c diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c b/drivers/gpu/drm/atmel/atmel_hlcdc_dc.c similarity index 100% rename from drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c rename to drivers/gpu/drm/atmel/atmel_hlcdc_dc.c diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h b/drivers/gpu/drm/atmel/atmel_hlcdc_dc.h similarity index 100% rename from drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h rename to drivers/gpu/drm/atmel/atmel_hlcdc_dc.h diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_output.c b/drivers/gpu/drm/atmel/atmel_hlcdc_output.c similarity index 100% rename from drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_output.c rename to drivers/gpu/drm/atmel/atmel_hlcdc_output.c diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c b/drivers/gpu/drm/atmel/atmel_hlcdc_plane.c similarity index 100% rename from drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c rename to drivers/gpu/drm/atmel/atmel_hlcdc_plane.c From patchwork Sun Aug 12 18:46:24 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Ravnborg X-Patchwork-Id: 956709 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=ravnborg.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="OcIkzFOR"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 41pVzx6XTdz9sCW for ; Mon, 13 Aug 2018 06:38:05 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727948AbeHLVZr (ORCPT ); Sun, 12 Aug 2018 17:25:47 -0400 Received: from mail-ed1-f67.google.com ([209.85.208.67]:45499 "EHLO mail-ed1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727822AbeHLVZr (ORCPT ); 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[158.248.196.126]) by smtp.gmail.com with ESMTPSA id g14-v6sm5897941edm.25.2018.08.12.11.46.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 12 Aug 2018 11:46:49 -0700 (PDT) From: Sam Ravnborg To: Boris Brezillon , Rob Herring , Mark Rutland , Lee Jones , Nicolas Ferre , Alexandre Belloni Cc: Sam Ravnborg , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pwm@vger.kernel.org, Boris Brezillon Subject: [PATCH v1 2/7] dt-binding: add bindings for Atmel LCDC mfd Date: Sun, 12 Aug 2018 20:46:24 +0200 Message-Id: <20180812184629.3808-2-sam@ravnborg.org> X-Mailer: git-send-email 2.12.0 In-Reply-To: <20180812184152.GA22343@ravnborg.org> References: <20180812184152.GA22343@ravnborg.org> Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org The LCDC IP used by some Atmel SOC's have a multifunction device that include two sub-devices: - pwm - display controller This binding describe the multi function device that act as root for the sub-devices The Atmel SOC's are at91sam9 etc. The compatible name is intentionally prefixed with -mfd to avoid clash with existing compatible entries. Signed-off-by: Sam Ravnborg Cc: Lee Jones Cc: Boris Brezillon --- .../devicetree/bindings/mfd/atmel-lcdc.txt | 75 ++++++++++++++++++++++ 1 file changed, 75 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/atmel-lcdc.txt diff --git a/Documentation/devicetree/bindings/mfd/atmel-lcdc.txt b/Documentation/devicetree/bindings/mfd/atmel-lcdc.txt new file mode 100644 index 000000000000..70e9b7bda6c7 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/atmel-lcdc.txt @@ -0,0 +1,75 @@ +Device-Tree bindings for Atmel's LCDC (LCD Controller) MFD driver + +Required properties: + - compatible: value should be one of the following: + "atmel,at91sam9261-lcdc-mfd" + "atmel,at91sam9263-lcdc-mfd" + "atmel,at91sam9g10-lcdc-mfd" + "atmel,at91sam9g45-lcdc-mfd" + "atmel,at91sam9g46-lcdc-mfd" + "atmel,at91sam9m10-lcdc-mfd" + "atmel,at91sam9m11-lcdc-mfd" + "atmel,at91sam9rl-lcdc-mfd" + - reg: base address and size of the LCDC device registers. + - clock-names: the name of the 2 clocks requested by the LCDC device. + Should contain "lcdc_clk", and "hclk". + - clocks: should contain the 2 clocks requested by the LCDC device. + May specify the same clock twice is there is no need to enable + "hclk" to use the display. + - interrupts: should contain the description of the LCDC interrupt line + +The LCDC IP exposes two subdevices: + - a PWM chip: see ../pwm/atmel-lcdc-pwm.txt + - a Display Controller: see ../display/atmel/lcdc-display-controller.txt + +Example: + lcdc0: lcdc@700000 { + compatible = "atmel,at91sam9263-lcdc-mfd"; + reg = <0x700000 0x1000>; + interrupts = <26 IRQ_TYPE_LEVEL_HIGH 3>; + clocks = <&lcd_clk>, <&lcd_clk>; + clock-names = "lcdc_clk", "hclk"; + + lcdc-display-controller { + compatible = "atmel,lcdc-display-controller"; + lcd-supply = <&lcdc_reg>; + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + lcdc_panel_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_input>; + }; + }; + }; + + lcdc_pwm: lcdc-pwm { + compatible = "atmel,lcdc-pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdc_pwm>; + #pwm-cells = <3>; + }; + + }; + + panel: panel { + compatible = "logictechnologies,lttd800480070-l2rt", "simple-panel"; + backlight = <&backlight>; + power-supply = <&panel_reg>; + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + + panel_input: endpoint@0 { + reg = <0>; + remote-endpoint = <&lcdc_panel_output>; + }; + }; + }; From patchwork Sun Aug 12 18:46:25 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Ravnborg X-Patchwork-Id: 956711 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=ravnborg.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Hd50dBvt"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 41pVzz6Pv1z9sCD for ; Mon, 13 Aug 2018 06:38:07 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727966AbeHLVZt (ORCPT ); Sun, 12 Aug 2018 17:25:49 -0400 Received: from mail-ed1-f66.google.com ([209.85.208.66]:41568 "EHLO mail-ed1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727946AbeHLVZt (ORCPT ); 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[158.248.196.126]) by smtp.gmail.com with ESMTPSA id g14-v6sm5897941edm.25.2018.08.12.11.46.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 12 Aug 2018 11:46:50 -0700 (PDT) From: Sam Ravnborg To: Boris Brezillon , Rob Herring , Mark Rutland , Lee Jones , Nicolas Ferre , Alexandre Belloni Cc: Sam Ravnborg , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pwm@vger.kernel.org, Boris Brezillon Subject: [PATCH v1 3/7] mfd: add atmel-lcdc driver Date: Sun, 12 Aug 2018 20:46:25 +0200 Message-Id: <20180812184629.3808-3-sam@ravnborg.org> X-Mailer: git-send-email 2.12.0 In-Reply-To: <20180812184152.GA22343@ravnborg.org> References: <20180812184152.GA22343@ravnborg.org> Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org The LCDC IP used by some Atmel SOC's have a multifunction device that include two sub-devices: - pwm - display controller This mfd device provide a regmap that can be used by the sub-devices to safely access the registers. The mfd device also support the clock used by the LCDC IP + a bus clock that in some cases are required. The driver is based on the atmel-hlcdc driver. The Atmel SOC's are at91sam9261, at91sam9263 etc. Signed-off-by: Sam Ravnborg Cc: Lee Jones Cc: Boris Brezillon --- drivers/mfd/Kconfig | 10 +++ drivers/mfd/Makefile | 1 + drivers/mfd/atmel-lcdc.c | 158 +++++++++++++++++++++++++++++++++++ include/linux/mfd/atmel-lcdc.h | 184 +++++++++++++++++++++++++++++++++++++++++ 4 files changed, 353 insertions(+) create mode 100644 drivers/mfd/atmel-lcdc.c create mode 100644 include/linux/mfd/atmel-lcdc.h diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index b860eb5aa194..f4851f0f033f 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -121,6 +121,16 @@ config MFD_ATMEL_HLCDC additional drivers must be enabled in order to use the functionality of the device. +config MFD_ATMEL_LCDC + tristate "Atmel LCDC (LCD Controller)" + select MFD_CORE + depends on OF + help + If you say yes here you get support for the LCDC block. + This driver provides common support for accessing the device, + additional drivers must be enabled in order to use the + functionality of the device. + config MFD_ATMEL_SMC bool select MFD_SYSCON diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index e9fd20dba18d..dba8465e0d96 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -186,6 +186,7 @@ obj-$(CONFIG_MFD_TPS65090) += tps65090.o obj-$(CONFIG_MFD_AAT2870_CORE) += aat2870-core.o obj-$(CONFIG_MFD_ATMEL_FLEXCOM) += atmel-flexcom.o obj-$(CONFIG_MFD_ATMEL_HLCDC) += atmel-hlcdc.o +obj-$(CONFIG_MFD_ATMEL_LCDC) += atmel-lcdc.o obj-$(CONFIG_MFD_ATMEL_SMC) += atmel-smc.o obj-$(CONFIG_MFD_INTEL_LPSS) += intel-lpss.o obj-$(CONFIG_MFD_INTEL_LPSS_PCI) += intel-lpss-pci.o diff --git a/drivers/mfd/atmel-lcdc.c b/drivers/mfd/atmel-lcdc.c new file mode 100644 index 000000000000..8928976bafca --- /dev/null +++ b/drivers/mfd/atmel-lcdc.c @@ -0,0 +1,158 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 Sam Ravnborg + * + * Author: Sam Ravnborg + * + * Based on atmel-hlcdc.c wich is: + * Copyright (C) 2014 Free Electrons + * Copyright (C) 2014 Atmel + * Author: Boris BREZILLON + */ + +#include +#include +#include +#include +#include +#include + +#define ATMEL_LCDC_REG_MAX (0x1000 - 0x4) + +struct lcdc_regmap { + void __iomem *regs; +}; + +static const struct mfd_cell lcdc_cells[] = { + { + .name = "atmel-lcdc-pwm", + .of_compatible = "atmel,lcdc-pwm", + }, + { + .name = "atmel-lcdc-dc", + .of_compatible = "atmel,lcdc-display-controller", + }, +}; + +static int regmap_lcdc_reg_write(void *context, unsigned int reg, + unsigned int val) +{ + struct lcdc_regmap *regmap = context; + + writel(val, regmap->regs + reg); + + return 0; +} + +static int regmap_lcdc_reg_read(void *context, unsigned int reg, + unsigned int *val) +{ + struct lcdc_regmap *regmap = context; + + *val = readl(regmap->regs + reg); + + return 0; +} + +static const struct regmap_config lcdc_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .max_register = ATMEL_LCDC_REG_MAX, + .reg_write = regmap_lcdc_reg_write, + .reg_read = regmap_lcdc_reg_read, + .fast_io = true, +}; + +static int lcdc_probe(struct platform_device *pdev) +{ + struct atmel_mfd_lcdc *lcdc; + struct lcdc_regmap *regmap; + struct resource *res; + struct device *dev; + int ret; + + dev = &pdev->dev; + + regmap = devm_kzalloc(dev, sizeof(*regmap), GFP_KERNEL); + if (!regmap) + return -ENOMEM; + + lcdc = devm_kzalloc(dev, sizeof(*lcdc), GFP_KERNEL); + if (!lcdc) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + regmap->regs = devm_ioremap_resource(dev, res); + if (IS_ERR(regmap->regs)) { + dev_err(dev, "Failed to allocate IO mem (%ld)\n", + PTR_ERR(regmap->regs)); + return PTR_ERR(regmap->regs); + } + + lcdc->irq = platform_get_irq(pdev, 0); + if (lcdc->irq < 0) { + dev_err(dev, "Failed to get irq (%d)\n", lcdc->irq); + return lcdc->irq; + } + + lcdc->lcdc_clk = devm_clk_get(dev, "lcdc_clk"); + if (IS_ERR(lcdc->lcdc_clk)) { + dev_err(dev, "failed to get lcdc clock (%ld)\n", + PTR_ERR(lcdc->lcdc_clk)); + return PTR_ERR(lcdc->lcdc_clk); + } + + lcdc->bus_clk = devm_clk_get(dev, "hclk"); + if (IS_ERR(lcdc->bus_clk)) { + dev_err(dev, "failed to get bus clock (%ld)\n", + PTR_ERR(lcdc->bus_clk)); + return PTR_ERR(lcdc->bus_clk); + } + + lcdc->regmap = devm_regmap_init(dev, NULL, regmap, + &lcdc_regmap_config); + if (IS_ERR(lcdc->regmap)) { + dev_err(dev, "Failed to init regmap (%ld)\n", + PTR_ERR(lcdc->regmap)); + return PTR_ERR(lcdc->regmap); + } + + dev_set_drvdata(dev, lcdc); + + ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE, + lcdc_cells, ARRAY_SIZE(lcdc_cells), + NULL, 0, NULL); + if (ret < 0) + dev_err(dev, "Failed to add %d mfd devices (%d)\n", + ARRAY_SIZE(lcdc_cells), ret); + + return ret; +} + +static const struct of_device_id lcdc_match[] = { + { .compatible = "atmel,at91sam9261-lcdc-mfd" }, + { .compatible = "atmel,at91sam9263-lcdc-mfd" }, + { .compatible = "atmel,at91sam9g10-lcdc-mfd" }, + { .compatible = "atmel,at91sam9g45-lcdc-mfd" }, + { .compatible = "atmel,at91sam9g46-lcdc-mfd" }, + { .compatible = "atmel,at91sam9m10-lcdc-mfd" }, + { .compatible = "atmel,at91sam9m11-lcdc-mfd" }, + { .compatible = "atmel,at91sam9rl-lcdc-mfd" }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, lcdc_match); + +static struct platform_driver lcdc_driver = { + .probe = lcdc_probe, + .driver = { + .name = "atmel-lcdc", + .of_match_table = lcdc_match, + }, +}; +module_platform_driver(lcdc_driver); + +MODULE_ALIAS("platform:atmel-lcdc"); +MODULE_AUTHOR("Sam Ravnborg "); +MODULE_DESCRIPTION("Atmel LCDC mfd driver"); +MODULE_LICENSE("GPL v2"); diff --git a/include/linux/mfd/atmel-lcdc.h b/include/linux/mfd/atmel-lcdc.h new file mode 100644 index 000000000000..fdab269baa8e --- /dev/null +++ b/include/linux/mfd/atmel-lcdc.h @@ -0,0 +1,184 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 Sam Ravnborg + * + * Author: Sam Ravnborg + */ + +#ifndef __LINUX_MFD_LCDC_H +#define __LINUX_MFD_LCDC_H + +#include +#include + +/** + * Structure shared by the Atmel LCD Controller device and its sub-devices. + * + * @regmap: register map used to access LCDC IP registers + * @lcdc_clk: the lcd controller peripheral clock + * @bus_clk: the bus clock clock (often the same as lcdc_clk) + * @irq: the lcdc irq + */ +struct atmel_mfd_lcdc { + struct regmap *regmap; + struct clk *lcdc_clk; + struct clk *bus_clk; + int irq; +}; + +#define ATMEL_LCDC_DMABADDR1 0x00 +#define ATMEL_LCDC_DMABADDR2 0x04 +#define ATMEL_LCDC_DMAFRMPT1 0x08 +#define ATMEL_LCDC_DMAFRMPT2 0x0c +#define ATMEL_LCDC_DMAFRMADD1 0x10 +#define ATMEL_LCDC_DMAFRMADD2 0x14 + +#define ATMEL_LCDC_DMAFRMCFG 0x18 +#define ATMEL_LCDC_FRSIZE (0x7fffff << 0) +#define ATMEL_LCDC_BLENGTH_OFFSET 24 +#define ATMEL_LCDC_BLENGTH (0x7f << ATMEL_LCDC_BLENGTH_OFFSET) + +#define ATMEL_LCDC_DMACON 0x1c +#define ATMEL_LCDC_DMAEN (0x1 << 0) +#define ATMEL_LCDC_DMARST (0x1 << 1) +#define ATMEL_LCDC_DMABUSY (0x1 << 2) +#define ATMEL_LCDC_DMAUPDT (0x1 << 3) +#define ATMEL_LCDC_DMA2DEN (0x1 << 4) + +#define ATMEL_LCDC_DMA2DCFG 0x20 +#define ATMEL_LCDC_ADDRINC_OFFSET 0 +#define ATMEL_LCDC_ADDRINC (0xffff) +#define ATMEL_LCDC_PIXELOFF_OFFSET 24 +#define ATMEL_LCDC_PIXELOFF (0x1f << 24) + +#define ATMEL_LCDC_LCDCON1 0x0800 +#define ATMEL_LCDC_BYPASS (1 << 0) +#define ATMEL_LCDC_CLKVAL_OFFSET 12 +#define ATMEL_LCDC_CLKVAL (0x1ff << ATMEL_LCDC_CLKVAL_OFFSET) +#define ATMEL_LCDC_LINCNT (0x7ff << 21) + +#define ATMEL_LCDC_LCDCON2 0x0804 +#define ATMEL_LCDC_DISTYPE (3 << 0) +#define ATMEL_LCDC_DISTYPE_STNMONO (0 << 0) +#define ATMEL_LCDC_DISTYPE_STNCOLOR (1 << 0) +#define ATMEL_LCDC_DISTYPE_TFT (2 << 0) +#define ATMEL_LCDC_SCANMOD (1 << 2) +#define ATMEL_LCDC_SCANMOD_SINGLE (0 << 2) +#define ATMEL_LCDC_SCANMOD_DUAL (1 << 2) +#define ATMEL_LCDC_IFWIDTH (3 << 3) +#define ATMEL_LCDC_IFWIDTH_4 (0 << 3) +#define ATMEL_LCDC_IFWIDTH_8 (1 << 3) +#define ATMEL_LCDC_IFWIDTH_16 (2 << 3) +#define ATMEL_LCDC_PIXELSIZE (7 << 5) +#define ATMEL_LCDC_PIXELSIZE_1 (0 << 5) +#define ATMEL_LCDC_PIXELSIZE_2 (1 << 5) +#define ATMEL_LCDC_PIXELSIZE_4 (2 << 5) +#define ATMEL_LCDC_PIXELSIZE_8 (3 << 5) +#define ATMEL_LCDC_PIXELSIZE_16 (4 << 5) +#define ATMEL_LCDC_PIXELSIZE_24 (5 << 5) +#define ATMEL_LCDC_PIXELSIZE_32 (6 << 5) +#define ATMEL_LCDC_INVVD (1 << 8) +#define ATMEL_LCDC_INVVD_NORMAL (0 << 8) +#define ATMEL_LCDC_INVVD_INVERTED (1 << 8) +#define ATMEL_LCDC_INVFRAME (1 << 9) +#define ATMEL_LCDC_INVFRAME_NORMAL (0 << 9) +#define ATMEL_LCDC_INVFRAME_INVERTED (1 << 9) +#define ATMEL_LCDC_INVLINE (1 << 10) +#define ATMEL_LCDC_INVLINE_NORMAL (0 << 10) +#define ATMEL_LCDC_INVLINE_INVERTED (1 << 10) +#define ATMEL_LCDC_INVCLK (1 << 11) +#define ATMEL_LCDC_INVCLK_NORMAL (0 << 11) +#define ATMEL_LCDC_INVCLK_INVERTED (1 << 11) +#define ATMEL_LCDC_INVDVAL (1 << 12) +#define ATMEL_LCDC_INVDVAL_NORMAL (0 << 12) +#define ATMEL_LCDC_INVDVAL_INVERTED (1 << 12) +#define ATMEL_LCDC_CLKMOD (1 << 15) +#define ATMEL_LCDC_CLKMOD_ACTIVEDISPLAY (0 << 15) +#define ATMEL_LCDC_CLKMOD_ALWAYSACTIVE (1 << 15) +#define ATMEL_LCDC_MEMOR (1 << 31) +#define ATMEL_LCDC_MEMOR_BIG (0 << 31) +#define ATMEL_LCDC_MEMOR_LITTLE (1 << 31) + +#define ATMEL_LCDC_TIM1 0x0808 +#define ATMEL_LCDC_VFP_OFFSET 0 +#define ATMEL_LCDC_VFP (0xffU << 0) +#define ATMEL_LCDC_VBP_OFFSET 8 +#define ATMEL_LCDC_VBP (0xffU << ATMEL_LCDC_VBP_OFFSET) +#define ATMEL_LCDC_VPW_OFFSET 16 +#define ATMEL_LCDC_VPW (0x3fU << ATMEL_LCDC_VPW_OFFSET) +#define ATMEL_LCDC_VHDLY_OFFSET 24 +#define ATMEL_LCDC_VHDLY (0xfU << ATMEL_LCDC_VHDLY_OFFSET) + +#define ATMEL_LCDC_TIM2 0x080c +#define ATMEL_LCDC_HBP_OFFSET 0 +#define ATMEL_LCDC_HBP (0xffU << 0) +#define ATMEL_LCDC_HPW_OFFSET 8 +#define ATMEL_LCDC_HPW (0x3fU << ATMEL_LCDC_HPW_OFFSET) +#define ATMEL_LCDC_HFP_OFFSET 21 +#define ATMEL_LCDC_HFP (0x7ffU << ATMEL_LCDC_HFP_OFFSET) + +#define ATMEL_LCDC_LCDFRMCFG 0x0810 +#define ATMEL_LCDC_LINEVAL (0x7ff << 0) +#define ATMEL_LCDC_HOZVAL_OFFSET 21 +#define ATMEL_LCDC_HOZVAL (0x7ff << ATMEL_LCDC_HOZVAL_OFFSET) + +#define ATMEL_LCDC_FIFO 0x0814 +#define ATMEL_LCDC_FIFOTH (0xffff) + +#define ATMEL_LCDC_MVAL 0x0818 + +#define ATMEL_LCDC_DP1_2 0x081c +#define ATMEL_LCDC_DP4_7 0x0820 +#define ATMEL_LCDC_DP3_5 0x0824 +#define ATMEL_LCDC_DP2_3 0x0828 +#define ATMEL_LCDC_DP5_7 0x082c +#define ATMEL_LCDC_DP3_4 0x0830 +#define ATMEL_LCDC_DP4_5 0x0834 +#define ATMEL_LCDC_DP6_7 0x0838 +#define ATMEL_LCDC_DP1_2_VAL (0xff) +#define ATMEL_LCDC_DP4_7_VAL (0xfffffff) +#define ATMEL_LCDC_DP3_5_VAL (0xfffff) +#define ATMEL_LCDC_DP2_3_VAL (0xfff) +#define ATMEL_LCDC_DP5_7_VAL (0xfffffff) +#define ATMEL_LCDC_DP3_4_VAL (0xffff) +#define ATMEL_LCDC_DP4_5_VAL (0xfffff) +#define ATMEL_LCDC_DP6_7_VAL (0xfffffff) + +#define ATMEL_LCDC_PWRCON 0x083c +#define ATMEL_LCDC_PWR (1 << 0) +#define ATMEL_LCDC_GUARDT_OFFSET 1 +#define ATMEL_LCDC_GUARDT (0x7f << ATMEL_LCDC_GUARDT_OFFSET) +#define ATMEL_LCDC_BUSY (1 << 31) + +#define ATMEL_LCDC_CONTRAST_CTR 0x0840 +#define ATMEL_LCDC_PS (3 << 0) +#define ATMEL_LCDC_PS_DIV1 (0 << 0) +#define ATMEL_LCDC_PS_DIV2 (1 << 0) +#define ATMEL_LCDC_PS_DIV4 (2 << 0) +#define ATMEL_LCDC_PS_DIV8 (3 << 0) +#define ATMEL_LCDC_POL (1 << 2) +#define ATMEL_LCDC_POL_NEGATIVE (0 << 2) +#define ATMEL_LCDC_POL_POSITIVE (1 << 2) +#define ATMEL_LCDC_ENA (1 << 3) +#define ATMEL_LCDC_ENA_PWMDISABLE (0 << 3) +#define ATMEL_LCDC_ENA_PWMENABLE (1 << 3) + +#define ATMEL_LCDC_CONTRAST_VAL 0x0844 +#define ATMEL_LCDC_CVAL (0xff) + +#define ATMEL_LCDC_IER 0x0848 +#define ATMEL_LCDC_IDR 0x084c +#define ATMEL_LCDC_IMR 0x0850 +#define ATMEL_LCDC_ISR 0x0854 +#define ATMEL_LCDC_ICR 0x0858 +#define ATMEL_LCDC_LNI (1 << 0) +#define ATMEL_LCDC_LSTLNI (1 << 1) +#define ATMEL_LCDC_EOFI (1 << 2) +#define ATMEL_LCDC_UFLWI (1 << 4) +#define ATMEL_LCDC_OWRI (1 << 5) +#define ATMEL_LCDC_MERI (1 << 6) + +#define ATMEL_LCDC_LUT(n) (0x0c00 + ((n)*4)) +#define ATMEL_LCDC_LUT_SIZE 256 + +#endif /* __LINUX_MFD_LCDC_H */ From patchwork Sun Aug 12 18:46:26 2018 Content-Type: text/plain; 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[158.248.196.126]) by smtp.gmail.com with ESMTPSA id g14-v6sm5897941edm.25.2018.08.12.11.46.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 12 Aug 2018 11:46:51 -0700 (PDT) From: Sam Ravnborg To: Boris Brezillon , Rob Herring , Mark Rutland , Lee Jones , Nicolas Ferre , Alexandre Belloni Cc: Sam Ravnborg , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pwm@vger.kernel.org, Thierry Reding , Boris Brezillon Subject: [PATCH v1 4/7] dt-bindings: add bindings for Atmel LCDC pwm Date: Sun, 12 Aug 2018 20:46:26 +0200 Message-Id: <20180812184629.3808-4-sam@ravnborg.org> X-Mailer: git-send-email 2.12.0 In-Reply-To: <20180812184152.GA22343@ravnborg.org> References: <20180812184152.GA22343@ravnborg.org> Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org The LCDC IP used by some Atmel SOC's have a multifunction device that include two sub-devices: - pwm - display controller This binding describe the pwm binding and refer back to the mfd device that this must be a child node of. Signed-off-by: Sam Ravnborg Cc: Thierry Reding Cc: Boris Brezillon --- .../devicetree/bindings/pwm/atmel-lcdc-pwm.txt | 30 ++++++++++++++++++++++ 1 file changed, 30 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/atmel-lcdc-pwm.txt diff --git a/Documentation/devicetree/bindings/pwm/atmel-lcdc-pwm.txt b/Documentation/devicetree/bindings/pwm/atmel-lcdc-pwm.txt new file mode 100644 index 000000000000..a7f11ac6972a --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/atmel-lcdc-pwm.txt @@ -0,0 +1,30 @@ +Device-Tree bindings for Atmel's LCDC (LCD Controller) PWM driver + +The Atmel LCDC PWM is subdevice of the LCDC MFD device. +See ../mfd/atmel-lcdc.txt for more details. + +Required properties: + - compatible: value should be one of the following: + "atmel,lcdc-pwm" + - pinctr-names: the pin control state names. Should contain "default". + - pinctrl-0: should contain the pinctrl states described by pinctrl + default. + - #pwm-cells: should be set to 3. This PWM chip use the default 3 cells + bindings defined in pwm.txt in this directory. + +Example: + lcdc0: lcdc@700000 { + compatible = "atmel,at91sam9263-lcdc-mfd"; + reg = <0x700000 0x1000>; + interrupts = <26 IRQ_TYPE_LEVEL_HIGH 3>; + clocks = <&lcd_clk>, <&lcd_clk>; + clock-names = "lcdc_clk", "hclk"; + + lcdc_pwm: lcdc-pwm { + compatible = "atmel,lcdc-pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdc_pwm>; + #pwm-cells = <3>; + }; + + }; From patchwork Sun Aug 12 18:46:27 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Ravnborg X-Patchwork-Id: 956714 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=ravnborg.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="DqhqnApE"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 41pW060vKNz9sCW for ; Mon, 13 Aug 2018 06:38:14 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728058AbeHLVZv (ORCPT ); Sun, 12 Aug 2018 17:25:51 -0400 Received: from mail-ed1-f65.google.com ([209.85.208.65]:36359 "EHLO mail-ed1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727956AbeHLVZv (ORCPT ); Sun, 12 Aug 2018 17:25:51 -0400 Received: by mail-ed1-f65.google.com with SMTP id k15-v6so7176702edr.3; Sun, 12 Aug 2018 11:46:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=6JwetyMLjsWz/3MzOUHvBwz7zC4maJn7BP7lHyHO9jA=; b=DqhqnApECfvw6U/0S6reQfmJDgsW0l8CvCwHP7tT1Bht8GShcXAXNHUzWqc0Ch/IGt ItyFOyfB6gJXd/cotW74ULuOhYof5VzcKZTe985TsR7Q+JbLDoFZlEnghKGHbRVLvQE8 aCx0gP8kPvvPUs7qOCH6uESSbuy4hbdilj5aOwSJiA/qp6u/agj0T5RTgjiEiMY01zZX LGG5pzMrMLHKqh0yiSurxydNA5LCSroIXgJJcn7oVoIy5yqOINfoxPWI98W9vcN6V+Sr 4cN3elBvpXx1RKQo0Gd7xo2ImN3xasFDJKDxP+jxcLW+wVUQf4a6NJdD62CkSQzF16kM s3rw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=6JwetyMLjsWz/3MzOUHvBwz7zC4maJn7BP7lHyHO9jA=; b=ZGV2zFL33hI9Ldw3Uk+A1YvZzZoRadWity+F5uTCRHbC+4N0LvY0ph4YILECqPWb0h 2t8MIFU7HRlZNv2fS53lgb2n5ejcvK5UqfCbE3CFAtYoyr3aK1IFALMxf7maKkt06o8n dC5TwsslL0p9RZ9emFQe14/7f0P1Js8sHqfmqypgp0t4CY6VSBdgVMwDnIpkCKxu5bcu BA0UJ9mNxnGlul3LzgbcSU1xLQsN+Bx9LHodRE3+Gnm2lBvyvoZvovwXFZSwh/tbAOof UUDwCw1WTh+hGxyFLkhUT0VxdivMosTPunGjq6BI8ubtCGZD3+tr7tggf4XD36+UYmG4 j4Rg== X-Gm-Message-State: AOUpUlGI4pLLS4netPnaIKaAd6KNHAXNcWB2nVIOz/d1eF1oXHMEB0XP 0DcXwa3bJ5nhNmaMJnrdalM= X-Google-Smtp-Source: AA+uWPyACBg0b7g68LHt8hDFnZlJyZoFGA8ImTgUaX7isJIEVH4y4JN9NdIQlxyQxW9L26MYThn/Og== X-Received: by 2002:a50:9e2f:: with SMTP id z44-v6mr18492269ede.303.1534099613488; Sun, 12 Aug 2018 11:46:53 -0700 (PDT) Received: from jupiter.lan (126.158-248-196.customer.lyse.net. [158.248.196.126]) by smtp.gmail.com with ESMTPSA id g14-v6sm5897941edm.25.2018.08.12.11.46.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 12 Aug 2018 11:46:53 -0700 (PDT) From: Sam Ravnborg To: Boris Brezillon , Rob Herring , Mark Rutland , Lee Jones , Nicolas Ferre , Alexandre Belloni Cc: Sam Ravnborg , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pwm@vger.kernel.org, Thierry Reding , Boris Brezillon Subject: [PATCH v1 5/7] pwm: add pwm-atmel-lcdc driver Date: Sun, 12 Aug 2018 20:46:27 +0200 Message-Id: <20180812184629.3808-5-sam@ravnborg.org> X-Mailer: git-send-email 2.12.0 In-Reply-To: <20180812184152.GA22343@ravnborg.org> References: <20180812184152.GA22343@ravnborg.org> Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org The LCDC IP used by some Atmel SOC's have a multifunction device that include two sub-devices: - pwm - display controller This driver add support for the pwm sub-device exposing a single PWM device that can be used for backlight. The driver is based on the pwm-atmel-hlcdc driver. Signed-off-by: Sam Ravnborg Cc: Thierry Reding Cc: Boris Brezillon --- drivers/pwm/Kconfig | 13 ++++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-atmel-lcdc.c | 178 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 192 insertions(+) create mode 100644 drivers/pwm/pwm-atmel-lcdc.c diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index a4d262db9945..3976c1840778 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -62,6 +62,19 @@ config PWM_ATMEL_HLCDC_PWM To compile this driver as a module, choose M here: the module will be called pwm-atmel-hlcdc. +config PWM_ATMEL_LCDC_PWM + tristate "Atmel LCDC PWM support" + depends on MFD_ATMEL_LCDC + depends on HAVE_CLK + help + Generic PWM framework driver for the PWM output of the LCDC + (Atmel LCD Controller). This PWM output is mainly used + to control the LCD backlight. + The Atmel LCD Controller is found in the at91sam9x family. + + To compile this driver as a module, choose M here: the module + will be called pwm-atmel-lcdc. + config PWM_ATMEL_TCB tristate "Atmel TC Block PWM support" depends on ATMEL_TCLIB && OF diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 9c676a0dadf5..85d884cb0977 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -4,6 +4,7 @@ obj-$(CONFIG_PWM_SYSFS) += sysfs.o obj-$(CONFIG_PWM_AB8500) += pwm-ab8500.o obj-$(CONFIG_PWM_ATMEL) += pwm-atmel.o obj-$(CONFIG_PWM_ATMEL_HLCDC_PWM) += pwm-atmel-hlcdc.o +obj-$(CONFIG_PWM_ATMEL_LCDC_PWM) += pwm-atmel-lcdc.o obj-$(CONFIG_PWM_ATMEL_TCB) += pwm-atmel-tcb.o obj-$(CONFIG_PWM_BCM_IPROC) += pwm-bcm-iproc.o obj-$(CONFIG_PWM_BCM_KONA) += pwm-bcm-kona.o diff --git a/drivers/pwm/pwm-atmel-lcdc.c b/drivers/pwm/pwm-atmel-lcdc.c new file mode 100644 index 000000000000..3d528e75cf9f --- /dev/null +++ b/drivers/pwm/pwm-atmel-lcdc.c @@ -0,0 +1,178 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 Sam Ravnborg + * + * Author: Sam Ravnborg + * + * PWM embedded in the LCD Controller. + * A sub-device of the Atmel LCDC driver. + * + * Based on pwm-atmel-hlcdc which is: + * Copyright (C) 2014 Free Electrons + * Copyright (C) 2014 Atmel + * Author: Boris BREZILLON + */ + +#include +#include +#include +#include + +#include +#include + +struct lcdc_pwm { + struct pwm_chip chip; + struct atmel_mfd_lcdc *mfd_lcdc; +}; + +static inline struct lcdc_pwm *to_lcdc_pwm(struct pwm_chip *chip) +{ + return container_of(chip, struct lcdc_pwm, chip); +} + +static int lcdc_pwm_apply(struct pwm_chip *pwm_chip, struct pwm_device *pwm, + struct pwm_state *state) +{ + struct lcdc_pwm *chip; + int contrast_ctr; + int contrast_val; + int ret; + + chip = to_lcdc_pwm(pwm_chip); + + if (state->enabled) { + contrast_val = pwm_get_relative_duty_cycle(state, + ATMEL_LCDC_CVAL); + ret = regmap_write(chip->mfd_lcdc->regmap, + ATMEL_LCDC_CONTRAST_VAL, contrast_val); + if (ret) + return ret; + + contrast_ctr = ATMEL_LCDC_ENA_PWMENABLE | ATMEL_LCDC_PS_DIV8; + if (state->polarity == PWM_POLARITY_NORMAL) + contrast_ctr |= ATMEL_LCDC_POL_POSITIVE; + else + contrast_ctr |= ATMEL_LCDC_POL_NEGATIVE; + + ret = regmap_write(chip->mfd_lcdc->regmap, + ATMEL_LCDC_CONTRAST_CTR, contrast_ctr); + } else { + contrast_ctr = ATMEL_LCDC_ENA_PWMDISABLE; + ret = regmap_write(chip->mfd_lcdc->regmap, + ATMEL_LCDC_CONTRAST_CTR, contrast_ctr); + } + + return ret; +} + +static const struct pwm_ops lcdc_pwm_ops = { + .apply = lcdc_pwm_apply, + .owner = THIS_MODULE, +}; + +#ifdef CONFIG_PM_SLEEP +static int lcdc_pwm_suspend(struct device *dev) +{ + struct lcdc_pwm *chip = dev_get_drvdata(dev); + + /* Keep the lcdc clock enabled if the PWM is still running. */ + if (pwm_is_enabled(&chip->chip.pwms[0])) + clk_disable_unprepare(chip->mfd_lcdc->lcdc_clk); + + return 0; +} + +static int lcdc_pwm_resume(struct device *dev) +{ + struct lcdc_pwm *chip = dev_get_drvdata(dev); + struct pwm_state state; + int ret; + + pwm_get_state(&chip->chip.pwms[0], &state); + + /* Re-enable the lcdc clock if it was stopped during suspend. */ + if (!state.enabled) { + ret = clk_prepare_enable(chip->mfd_lcdc->lcdc_clk); + if (ret) + return ret; + } + + return lcdc_pwm_apply(&chip->chip, &chip->chip.pwms[0], &state); +} +#endif + +static SIMPLE_DEV_PM_OPS(lcdc_pwm_pm_ops, + lcdc_pwm_suspend, lcdc_pwm_resume); + +static int lcdc_pwm_probe(struct platform_device *pdev) +{ + struct atmel_mfd_lcdc *mfd_lcdc; + struct lcdc_pwm *chip; + struct device *dev; + int ret; + + dev = &pdev->dev; + mfd_lcdc = dev_get_drvdata(dev->parent); + + chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); + if (!chip) + return -ENOMEM; + + ret = clk_prepare_enable(mfd_lcdc->lcdc_clk); + if (ret) + return ret; + + chip->mfd_lcdc = mfd_lcdc; + chip->chip.ops = &lcdc_pwm_ops; + chip->chip.dev = dev; + chip->chip.base = -1; + chip->chip.npwm = 1; + chip->chip.of_xlate = of_pwm_xlate_with_flags; + chip->chip.of_pwm_n_cells = 3; + + ret = pwmchip_add_with_polarity(&chip->chip, PWM_POLARITY_INVERSED); + if (ret) { + clk_disable_unprepare(mfd_lcdc->lcdc_clk); + return ret; + } + + platform_set_drvdata(pdev, chip); + + return 0; +} + +static int lcdc_pwm_remove(struct platform_device *pdev) +{ + struct lcdc_pwm *chip = platform_get_drvdata(pdev); + int ret; + + ret = pwmchip_remove(&chip->chip); + if (ret) + return ret; + + clk_disable_unprepare(chip->mfd_lcdc->lcdc_clk); + + return 0; +} + +static const struct of_device_id lcdc_pwm_dt_ids[] = { + { .compatible = "atmel,lcdc-pwm" }, + { /* sentinel */ }, +}; + +static struct platform_driver lcdc_pwm_driver = { + .driver = { + .name = "atmel-lcdc-pwm", + .of_match_table = lcdc_pwm_dt_ids, + .pm = &lcdc_pwm_pm_ops, + }, + .probe = lcdc_pwm_probe, + .remove = lcdc_pwm_remove, +}; +module_platform_driver(lcdc_pwm_driver); + +MODULE_ALIAS("platform:pwm-atmel-lcdc"); +MODULE_AUTHOR("Sam Ravnborg "); +MODULE_DESCRIPTION("Atmel LCDC PWM driver"); +MODULE_LICENSE("GPL v2"); From patchwork Sun Aug 12 18:46:28 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Ravnborg X-Patchwork-Id: 956715 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=ravnborg.org Authentication-Results: ozlabs.org; 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[158.248.196.126]) by smtp.gmail.com with ESMTPSA id g14-v6sm5897941edm.25.2018.08.12.11.46.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 12 Aug 2018 11:46:54 -0700 (PDT) From: Sam Ravnborg To: Boris Brezillon , Rob Herring , Mark Rutland , Lee Jones , Nicolas Ferre , Alexandre Belloni Cc: Sam Ravnborg , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pwm@vger.kernel.org, Boris Brezillon Subject: [PATCH v1 6/7] dt-bindings: add bindings for Atmel lcdc-display-controller Date: Sun, 12 Aug 2018 20:46:28 +0200 Message-Id: <20180812184629.3808-6-sam@ravnborg.org> X-Mailer: git-send-email 2.12.0 In-Reply-To: <20180812184152.GA22343@ravnborg.org> References: <20180812184152.GA22343@ravnborg.org> Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org The LCDC IP used by some Atmel SOC's have a multifunction device that include two sub-devices: - pwm - display controller This binding describe the lcdc display controller and refer back to the mfd device that this must be a child node of. Signed-off-by: Sam Ravnborg Cc: Boris Brezillon --- .../display/atmel/lcdc-display-controller.txt | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/atmel/lcdc-display-controller.txt diff --git a/Documentation/devicetree/bindings/display/atmel/lcdc-display-controller.txt b/Documentation/devicetree/bindings/display/atmel/lcdc-display-controller.txt new file mode 100644 index 000000000000..508a49b5d8b7 --- /dev/null +++ b/Documentation/devicetree/bindings/display/atmel/lcdc-display-controller.txt @@ -0,0 +1,40 @@ +Atmel LCD Controller (LCDC) Display Controller + +Required properties: + - compatible: value should be one of the following: + "atmel,lcdc-display-controller" + +Optional properties: +- lcd-supply: phandle to a regulator that supply the display + +Required children nodes: + One child node that references the panel connected. + (See ../graph.txt) + At least one port node is required. + + +Example: + lcdc0: lcdc@700000 { + compatible = "atmel,at91sam9263-lcdc-mfd"; + reg = <0x700000 0x1000>; + interrupts = <26 IRQ_TYPE_LEVEL_HIGH 3>; + clocks = <&lcd_clk>, <&lcd_clk>; + clock-names = "lcdc_clk", "hclk"; + + lcdc-display-controller { + compatible = "atmel,lcdc-display-controller"; + lcd-supply = <&lcdc_reg>; + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + lcdc_panel_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_input>; + }; + }; + }; + }; From patchwork Sun Aug 12 18:46:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Ravnborg X-Patchwork-Id: 956717 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=ravnborg.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="cTztyJUx"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 41pW0B4j53z9sCm for ; Mon, 13 Aug 2018 06:38:18 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727822AbeHLVZy (ORCPT ); Sun, 12 Aug 2018 17:25:54 -0400 Received: from mail-ed1-f66.google.com ([209.85.208.66]:39578 "EHLO mail-ed1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727956AbeHLVZy (ORCPT ); Sun, 12 Aug 2018 17:25:54 -0400 Received: by mail-ed1-f66.google.com with SMTP id h4-v6so7168524edi.6; Sun, 12 Aug 2018 11:46:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=B4gnshzq36eoM3BArIKPQbGHhYbNwIeR9BEMTz8Ph74=; b=cTztyJUxdwgzJahMC8mPKCEW9Xre+qkH3Upt4ETOifaSoAfSUFAJZlI9LWbEPimAGj N7fAA/17W3JvbXs+9xzMHjHAw5+cmdNwuio8Vl3maQgFmFM04B9jHBAAQ5l0aKJoutqo XcneczdOLjkOa7XoPBaD7I7M78tf58kIHM/PC9D3QRBHVJ/Ov4uUb0B3M0VShCW/h5uH 03grSKnXbAXmBiXdOJbEx1XPpLLLCeZIaFQMASstdViV6Rb8pWXZaCdU7bUGuqLXg6le 1f3/1hu53M2GNTCeHf2GsZjbGO4D8Crl61LGt6u4D6UneRRS//moO/6ayncaVmSpv9Nc BXGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=B4gnshzq36eoM3BArIKPQbGHhYbNwIeR9BEMTz8Ph74=; b=XcD3Kq/QE1LZ1ozAhCxyuDmq32FxXfIvutw05p6UH/M2oxn0y8+W2SLl5J4bWqwozW dWe8KOt+tdtGNmAsnCoGsce6dU/rKy7Myj+NOEeldwXDJQGdGjDPdBzXerfWmvJvCYVB kLuj/pSbL+pCxhh0qLr5NB82O2/heAc3O/3ZqJ0mJAJkHE57CSzE+dlpC543/obvDgl4 /iHfgxskOEcRt/htXNdKV6xt3SnKHn7HMuRInjauPW9T/TpN83rOj+Wt9brkH6nXxgwd gx4dg6JlP2itDKqk0vHnUHKNm0J2qnsMg4vBqepSaPxyhCFGJtbWfHKTxBhsDl4k44Ki Jvxg== X-Gm-Message-State: AOUpUlFstFZSYvpMm09ubbNyJIYj6kStdtphb5DsdpYeP1m4bJCF/Osx DnSblEenqG9LcWSoywUfhEg= X-Google-Smtp-Source: AA+uWPyF+JA81PEFFYtERLuOZ75os+sCsgXB5F5pXxmA6O3EvtwXpkzPvYIjc2LRumrYME/vadvSaw== X-Received: by 2002:a50:9662:: with SMTP id y89-v6mr19527914eda.32.1534099615744; Sun, 12 Aug 2018 11:46:55 -0700 (PDT) Received: from jupiter.lan (126.158-248-196.customer.lyse.net. [158.248.196.126]) by smtp.gmail.com with ESMTPSA id g14-v6sm5897941edm.25.2018.08.12.11.46.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 12 Aug 2018 11:46:55 -0700 (PDT) From: Sam Ravnborg To: Boris Brezillon , Rob Herring , Mark Rutland , Lee Jones , Nicolas Ferre , Alexandre Belloni Cc: Sam Ravnborg , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pwm@vger.kernel.org, Nicolas Ferre , Boris Brezillon Subject: [PATCH v1 7/7] drm: add Atmel LCDC display controller support Date: Sun, 12 Aug 2018 20:46:29 +0200 Message-Id: <20180812184629.3808-7-sam@ravnborg.org> X-Mailer: git-send-email 2.12.0 In-Reply-To: <20180812184152.GA22343@ravnborg.org> References: <20180812184152.GA22343@ravnborg.org> Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org This is a DRM based driver for the Atmel LCDC IP. There exist today a framebuffer based driver and this is a re-implmentation of the same on top of DRM. The rewrite was based on the original fbdev driver but the driver has also seen inspiration from the atmel-hlcdc_dc driver and others. The driver is not a full replacement: - STN displays are not supported Binding support is missing but most of the STN specific functionality is otherwise ported from the fbdev driver. - gamma support is missing The driver utilises drm_simple_kms_helper and this helper lacks support for settting up gamma - modesetting is not checked (see TODO in file) - support for extra modes as applicable (and lcd-wiring-mode) - support for AVR32 (is it relevant?) Signed-off-by: Sam Ravnborg Cc: Nicolas Ferre Cc: Boris Brezillon Cc: Alexandre Belloni --- MAINTAINERS | 7 + drivers/gpu/drm/atmel/Kconfig | 12 + drivers/gpu/drm/atmel/Makefile | 2 + drivers/gpu/drm/atmel/atmel_lcdc-dc.c | 1094 +++++++++++++++++++++++++++++++++ 4 files changed, 1115 insertions(+) create mode 100644 drivers/gpu/drm/atmel/atmel_lcdc-dc.c diff --git a/MAINTAINERS b/MAINTAINERS index 09ce76a9a1dc..0a594d02a7c0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4685,6 +4685,13 @@ F: drivers/gpu/drm/atmel/atmel-hlcdc* F: Documentation/devicetree/bindings/display/atmel/ T: git git://anongit.freedesktop.org/drm/drm-misc +DRM DRIVERS FOR ATMEL LCDC +M: Sam Ravnborg +L: dri-devel@lists.freedesktop.org +S: Maintained +F: drivers/gpu/drm/atmel/atmel-lcdc* +F: Documentation/devicetree/bindings/display/atmel/ + DRM DRIVERS FOR BRIDGE CHIPS M: Archit Taneja M: Andrzej Hajda diff --git a/drivers/gpu/drm/atmel/Kconfig b/drivers/gpu/drm/atmel/Kconfig index 7cd3862f9d18..c4c6150f271a 100644 --- a/drivers/gpu/drm/atmel/Kconfig +++ b/drivers/gpu/drm/atmel/Kconfig @@ -14,3 +14,15 @@ config DRM_ATMEL_HLCDC help Choose this option if you have an ATMEL SoC with an HLCDC display controller (i.e. at91sam9n12, at91sam9x5 family or sama5d3 family). + +config DRM_ATMEL_LCDC + tristate "DRM Support for ATMEL LCDC Display Controller" + depends on DRM && OF && COMMON_CLK && MFD_ATMEL_LCDC && ARM + select DRM_ATMEL + select DRM_GEM_CMA_HELPER + select DRM_KMS_HELPER + select DRM_KMS_CMA_HELPER + select DRM_PANEL + help + Choose this option if you have an ATMEL SoC with an LCDC display + controller (only at91sam9263 or at91sam9rl). diff --git a/drivers/gpu/drm/atmel/Makefile b/drivers/gpu/drm/atmel/Makefile index 49dc89f36b73..9fdfada613d2 100644 --- a/drivers/gpu/drm/atmel/Makefile +++ b/drivers/gpu/drm/atmel/Makefile @@ -5,3 +5,5 @@ atmel-hlcdc-dc-y := atmel_hlcdc_crtc.o \ atmel_hlcdc_plane.o obj-$(CONFIG_DRM_ATMEL_HLCDC) += atmel-hlcdc-dc.o + +obj-$(CONFIG_DRM_ATMEL_LCDC) += atmel_lcdc-dc.o diff --git a/drivers/gpu/drm/atmel/atmel_lcdc-dc.c b/drivers/gpu/drm/atmel/atmel_lcdc-dc.c new file mode 100644 index 000000000000..275a09e2e100 --- /dev/null +++ b/drivers/gpu/drm/atmel/atmel_lcdc-dc.c @@ -0,0 +1,1094 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 Sam Ravnborg + * + * The driver is based on atmel_lcdfb which is: + * Copyright (C) 2007 Atmel Corporation + * + * Atmel LCD Controller Display Controller. + * A sub-device of the Atmel LCDC IP. + * + * The Atmel LCD Controller supports in the following configuration: + * - TFT only, with BGR565, 8 bits/pixel + * - Resolution up to 2048x2048 + * - Single plane, crtc, one fixed output + * + * Features not (yet) ported from atmel_lcdfb: + * - Support for extra modes (and configurable intensify bit) + * - Check modesetting support - lcdc_dc_display_check() + * - set color / palette handling + * - support for STN displays (partly implemented) + * - AVR32 support (relevant?) + */ + +#include +#include +#include +#include +#include +#include +#include + +#include