From patchwork Tue Jul 24 09:36:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Donnellan X-Patchwork-Id: 948269 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41ZYD24KGGz9s2M for ; Tue, 24 Jul 2018 19:37:06 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=au1.ibm.com Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 41ZYD233K9zDr0d for ; Tue, 24 Jul 2018 19:37:06 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=au1.ibm.com X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=au1.ibm.com (client-ip=148.163.156.1; helo=mx0a-001b2d01.pphosted.com; envelope-from=andrew.donnellan@au1.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=au1.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 41ZYCt6kvwzDqCG for ; Tue, 24 Jul 2018 19:36:58 +1000 (AEST) Received: from pps.filterd (m0098399.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.22/8.16.0.22) with SMTP id w6O9TFLG028581 for ; Tue, 24 Jul 2018 05:36:56 -0400 Received: from e06smtp03.uk.ibm.com (e06smtp03.uk.ibm.com [195.75.94.99]) by mx0a-001b2d01.pphosted.com with ESMTP id 2kdyetxyrb-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Tue, 24 Jul 2018 05:36:55 -0400 Received: from localhost by e06smtp03.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Tue, 24 Jul 2018 10:36:52 +0100 Received: from d06av21.portsmouth.uk.ibm.com (d06av21.portsmouth.uk.ibm.com [9.149.105.232]) by b06cxnps3075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id w6O9apYQ36110410 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 24 Jul 2018 09:36:51 GMT Received: from d06av21.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id E511352063; Tue, 24 Jul 2018 12:37:05 +0100 (BST) Received: from ozlabs.au.ibm.com (unknown [9.192.253.14]) by d06av21.portsmouth.uk.ibm.com (Postfix) with ESMTP id 4C1AE52052; Tue, 24 Jul 2018 12:37:05 +0100 (BST) Received: from intelligence.ozlabs.ibm.com (haven.au.ibm.com [9.192.254.114]) (using TLSv1.2 with cipher DHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ozlabs.au.ibm.com (Postfix) with ESMTPSA id CBF6FA01D6; Tue, 24 Jul 2018 19:36:47 +1000 (AEST) From: Andrew Donnellan To: skiboot@lists.ozlabs.org Date: Tue, 24 Jul 2018 19:36:41 +1000 X-Mailer: git-send-email 2.11.0 X-TM-AS-GCONF: 00 x-cbid: 18072409-0012-0000-0000-0000028E03E3 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18072409-0013-0000-0000-000020BFE458 Message-Id: <20180724093641.3430-1-andrew.donnellan@au1.ibm.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2018-07-24_03:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1806210000 definitions=main-1807240101 Subject: [Skiboot] [PATCH] hw/phb4: Fix unused value/parameter warnings X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Remove the phb4.c-specific CFLAGS that disable the unused value and unused parameter warnings, and cleanup the ensuing warnings. Signed-off-by: Andrew Donnellan --- hw/Makefile.inc | 3 --- hw/phb4.c | 47 +++++++++++++++++++++++++++-------------------- 2 files changed, 27 insertions(+), 23 deletions(-) diff --git a/hw/Makefile.inc b/hw/Makefile.inc index 4dec98670426..005772a5f5d2 100644 --- a/hw/Makefile.inc +++ b/hw/Makefile.inc @@ -12,9 +12,6 @@ HW_OBJS += npu2-common.o npu2-opencapi.o phys-map.o sbe-p9.o capp.o occ-sensor.o HW_OBJS += vas.o sbe-p8.o HW=hw/built-in.a -# FIXME hack this for now -CFLAGS_hw/phb4.o = -Wno-unused-value -Wno-unused-parameter - include $(SRC)/hw/fsp/Makefile.inc include $(SRC)/hw/ec/Makefile.inc include $(SRC)/hw/ast-bmc/Makefile.inc diff --git a/hw/phb4.c b/hw/phb4.c index f2b92409d1a9..1c1a719ee7b2 100644 --- a/hw/phb4.c +++ b/hw/phb4.c @@ -128,7 +128,7 @@ /* Enable this to disable error interrupts for debug purposes */ #define DISABLE_ERR_INTS -static void phb4_init_hw(struct phb4 *p, bool first_init); +static void phb4_init_hw(struct phb4 *p); #define PHBDBG(p, fmt, a...) prlog(PR_DEBUG, "PHB#%04x[%d:%d]: " fmt, \ (p)->phb.opal_id, (p)->chip_id, \ @@ -800,10 +800,10 @@ static void phb4_endpoint_init(struct phb *phb, pci_cfg_write32(phb, bdfn, aercap + PCIECAP_AER_CAPCTL, val32); } -static int64_t phb4_pcicfg_no_dstate(void *dev, +static int64_t phb4_pcicfg_no_dstate(void *dev __unused, struct pci_cfg_reg_filter *pcrf, - uint32_t offset, uint32_t len, - uint32_t *data, bool write) + uint32_t offset, uint32_t len __unused, + uint32_t *data __unused, bool write) { uint32_t loff = offset - pcrf->start; @@ -816,7 +816,7 @@ static int64_t phb4_pcicfg_no_dstate(void *dev, return OPAL_PARTIAL; } -static void phb4_check_device_quirks(struct phb *phb, struct pci_device *dev) +static void phb4_check_device_quirks(struct pci_device *dev) { /* Some special adapter tweaks for devices directly under the PHB */ if (dev->primary_bus != 1) @@ -838,7 +838,7 @@ static int phb4_device_init(struct phb *phb, struct pci_device *dev, int ecap, aercap; /* Setup special device quirks */ - phb4_check_device_quirks(phb, dev); + phb4_check_device_quirks(dev); /* Common initialization for the device */ pci_device_init(phb, dev); @@ -1209,7 +1209,7 @@ static int64_t phb4_set_phb_mem_window(struct phb *phb, uint16_t window_type, uint16_t window_num, uint64_t addr, - uint64_t pci_addr, + uint64_t pci_addr __unused, uint64_t size) { struct phb4 *p = phb_to_phb4(phb); @@ -3043,7 +3043,7 @@ static int64_t phb4_creset(struct pci_slot *slot) p->flags &= ~PHB4_AIB_FENCED; p->flags &= ~PHB4_CAPP_RECOVERY; p->flags &= ~PHB4_CFG_USE_ASB; - phb4_init_hw(p, false); + phb4_init_hw(p); pci_slot_set_state(slot, PHB4_SLOT_CRESET_FRESET); return pci_slot_set_sm_timeout(slot, msecs_to_tb(100)); case PHB4_SLOT_CRESET_FRESET: @@ -3444,16 +3444,20 @@ static int64_t phb4_err_inject_finalize(struct phb4 *phb, uint64_t addr, return OPAL_SUCCESS; } -static int64_t phb4_err_inject_mem32(struct phb4 *phb, uint64_t pe_number, - uint64_t addr, uint64_t mask, - bool is_write) +static int64_t phb4_err_inject_mem32(struct phb4 *phb __unused, + uint64_t pe_number __unused, + uint64_t addr __unused, + uint64_t mask __unused, + bool is_write __unused) { return OPAL_UNSUPPORTED; } -static int64_t phb4_err_inject_mem64(struct phb4 *phb, uint64_t pe_number, - uint64_t addr, uint64_t mask, - bool is_write) +static int64_t phb4_err_inject_mem64(struct phb4 *phb __unused, + uint64_t pe_number __unused, + uint64_t addr __unused, + uint64_t mask __unused, + bool is_write __unused) { return OPAL_UNSUPPORTED; } @@ -3519,9 +3523,12 @@ static int64_t phb4_err_inject_cfg(struct phb4 *phb, uint64_t pe_number, return phb4_err_inject_finalize(phb, a, m, ctrl, is_write); } -static int64_t phb4_err_inject_dma(struct phb4 *phb, uint64_t pe_number, - uint64_t addr, uint64_t mask, - bool is_write, bool is_64bits) +static int64_t phb4_err_inject_dma(struct phb4 *phb __unused, + uint64_t pe_number __unused, + uint64_t addr __unused, + uint64_t mask __unused, + bool is_write __unused, + bool is_64bits __unused) { return OPAL_UNSUPPORTED; } @@ -4655,7 +4662,7 @@ static bool phb4_wait_dlp_reset(struct phb4 *p) } return true; } -static void phb4_init_hw(struct phb4 *p, bool first_init) +static void phb4_init_hw(struct phb4 *p) { uint64_t val, creset; @@ -5105,7 +5112,7 @@ static uint64_t phb4_lsi_attributes(struct irq_source *is __unused, } static int64_t phb4_ndd1_lsi_set_xive(struct irq_source *is, uint32_t isn, - uint16_t server, uint8_t priority) + uint16_t server __unused, uint8_t priority) { struct phb4 *p = is->data; uint32_t idx = isn - p->base_lsi; @@ -5326,7 +5333,7 @@ static void phb4_create(struct dt_node *np) phb4_init_ioda_cache(p); /* Get the HW up and running */ - phb4_init_hw(p, true); + phb4_init_hw(p); /* Load capp microcode into capp unit */ load_capp_ucode(p);