From patchwork Sat Jul 21 00:43:49 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Geis X-Patchwork-Id: 947258 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="SiAmkIyv"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 41XTX9620pz9s3N for ; Sat, 21 Jul 2018 10:43:53 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728189AbeGUBec (ORCPT ); Fri, 20 Jul 2018 21:34:32 -0400 Received: from mail-qt0-f193.google.com ([209.85.216.193]:45873 "EHLO mail-qt0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726179AbeGUBec (ORCPT ); Fri, 20 Jul 2018 21:34:32 -0400 Received: by mail-qt0-f193.google.com with SMTP id y5-v6so11832027qti.12; Fri, 20 Jul 2018 17:43:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:subject:to:cc:message-id:date:user-agent:mime-version :content-language:content-transfer-encoding; bh=jNHEmiMUbgsxbbOM3eVQNH1BY1k6Ym3TZHXCOd81D74=; b=SiAmkIyvrCFIqcseAF7kmU5Sl/iXVwbAd1mBXYOPBFL3/fwqdopsh3uwt7klruNlU2 5OsETtaeNKFyEcOrrxigsUIOx814LQpuOVfbEbKCQsCnXYwopW9ftqdI6G80IXFsQ397 kkBDlcS3d1UL6QyDGWz95d1xnzqo6GbET3LjG47nv5oDkSfNQL+3yLjdTNnlBsb8kJZL 6NX8c82ULZuNWHHvCdszEW0dtGxKiVaJn7NwoK2bBBe/1p7D8SDMFXjkp6ICJxNou27S iYxmO1aoONImEnohqHpakZsHhZu10YeznTSO+atI580YlZz2uF6bs4cD/JQNHyFnvpdW JIww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:subject:to:cc:message-id:date:user-agent :mime-version:content-language:content-transfer-encoding; bh=jNHEmiMUbgsxbbOM3eVQNH1BY1k6Ym3TZHXCOd81D74=; b=DmlZhuO5nmVb/zuXsfqBNGMMKXiIKALheT3VaDLD9XxWxnVW+ZuSBpRKkYEYg3+Ueb RN/edZnYAP6W481aRChS4hCXKcUl34KoHmDwnW8Knc0DcnscEdXTwGfKHtiQer0hMV4+ O8ny0KFHlaLQkoMC80uVFkae/pwQsuNv1QNc++iADvtSvdOGfhfSKb7womH42NWiHz0/ s2IopWoyv4HbUxcXaU/j73GC7qnXQoJ1MdLBC5N3/nJDVeUsKqbOlkMuSHDfpegVAljt NhMnWTPq31VY7Byg82eyDCpjrfnrSkHYniQ/WFEFZyZfaPLZ7RfoTVfuBvZjqeU0QaEv YiAg== X-Gm-Message-State: AOUpUlF/n71fmMzX2VnWBUiYxcbDPilWQngSJtBaGp1Y6mFAPbteua40 CiTN8mWRQckSJkfF+Th6IVNSCD19S8SOYg== X-Google-Smtp-Source: AAOMgpecuSw0Re2Ad9R0LPWjt1jrVAvzMxdoPm6U/tcZU5A2+AS0dn1Ph4KzH3hMktA3eK8PzwDA6w== X-Received: by 2002:a0c:a991:: with SMTP id a17-v6mr3772432qvb.83.1532133830664; Fri, 20 Jul 2018 17:43:50 -0700 (PDT) Received: from ?IPv6:2601:153:601:7d2a::100b? ([2601:153:601:7d2a::100b]) by smtp.gmail.com with ESMTPSA id e21-v6sm2159567qtc.67.2018.07.20.17.43.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 20 Jul 2018 17:43:50 -0700 (PDT) From: Peter Geis Subject: [PATCH 1/2] Add sw2_sw4 voltage table to cpcap regulator. To: girdwood@gmail.com Cc: broonie@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org Message-ID: Date: Fri, 20 Jul 2018 20:43:49 -0400 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.9.1 MIME-Version: 1.0 Content-Language: en-US Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org SW2 and SW4 use a shared table to provide voltage to the cpu core and devices on Tegra hardware. Added this table to the cpcap regulator driver as the first step to supporting this device on Tegra. Signed-off-by: Peter Geis --- drivers/regulator/cpcap-regulator.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) 2900000, }; diff --git a/drivers/regulator/cpcap-regulator.c b/drivers/regulator/cpcap-regulator.c index bd910fe123d9..c0b1e04bd90f 100644 --- a/drivers/regulator/cpcap-regulator.c +++ b/drivers/regulator/cpcap-regulator.c @@ -271,6 +271,29 @@ static struct regulator_ops cpcap_regulator_ops = { }; static const unsigned int unknown_val_tbl[] = { 0, }; +static const unsigned int sw2_sw4_val_tbl[] = { 612500, 625000, 637500, + 650000, 662500, 675000, + 687500, 700000, 712500, + 725000, 737500, 750000, + 762500, 775000, 787500, + 800000, 812500, 825000, + 837500, 850000, 862500, + 875000, 887500, 900000, + 912500, 925000, 937500, + 950000, 962500, 975000, + 987500, 1000000, 1012500, + 1025000, 1037500, 1050000, + 1062500, 1075000, 1087500, + 1100000, 1112500, 1125000, + 1137500, 1150000, 1162500, + 1175000, 1187500, 1200000, + 1212500, 1225000, 1237500, + 1250000, 1262500, 1275000, + 1287500, 1300000, 1312500, + 1325000, 1337500, 1350000, + 1362500, 1375000, 1387500, + 1400000, 1412500, 1425000, + 1437500, 1450000, 1462500, }; static const unsigned int sw5_val_tbl[] = { 0, 5050000, }; static const unsigned int vcam_val_tbl[] = { 2600000, 2700000, 2800000, From patchwork Sat Jul 21 00:43:56 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Geis X-Patchwork-Id: 947259 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Y2sRS3vW"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 41XTXJ5GK3z9s3N for ; Sat, 21 Jul 2018 10:44:00 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729832AbeGUBej (ORCPT ); Fri, 20 Jul 2018 21:34:39 -0400 Received: from mail-qk0-f195.google.com ([209.85.220.195]:43990 "EHLO mail-qk0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726179AbeGUBej (ORCPT ); Fri, 20 Jul 2018 21:34:39 -0400 Received: by mail-qk0-f195.google.com with SMTP id z74-v6so7204469qkb.10; Fri, 20 Jul 2018 17:43:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:subject:to:cc:message-id:date:user-agent:mime-version :content-language:content-transfer-encoding; bh=mpJ1mwYdG3spUJpFRcQNOD+Cy19KhT8VB8ZpKqxBsCs=; b=Y2sRS3vWaFR39tlPpAiW7VpWg423XiSe2/PJo9d//GwiF1Stq3kQMlnXmY24fgi5X2 WqjipCBAT/BSkSum76rGigWgsqkMl9i9nnZJnT9liR1pPWXywy8mSErb0ePK3x1q5ibu ZSkv0ttB1iLAdsUasCEq13XsmNFZcNE6bMruLix+k8O4Xea+DXF3iUGJi3gPJCbEv8Z8 9RQzC3+Oi3yWF6FUAwPS8mvML3ipT6Eg7+MLflR+j1iaYPiueActJ/7JDwFR6s7I+mQS ZHNszqh05i80MSECg53IlOrGP5l0wFiRSOVgec8DlpZpO7wqhw1NUNFJTgt0K1emmbC/ RtHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:subject:to:cc:message-id:date:user-agent :mime-version:content-language:content-transfer-encoding; bh=mpJ1mwYdG3spUJpFRcQNOD+Cy19KhT8VB8ZpKqxBsCs=; b=aB25eLdX2kktCA7NVBvpPX/qxQsFiU/jtezHx0cRTF9mEReZcX8yKDFmKK9FyVrZ6n 6YA/9P1HNDzsAYEdF/s4lm/MSfpo9KWRJnG7rAb09ttLTexj/waZ92Twb5T6XOQVDIex 7j8U8EBUAw0Ota2czeZ9jsZowe4PRRsT4mN6zbSSLotOYEWe/ZZmQxFn7K3a3iYmEzvp hY7QePmfsil1SHmPvbypya84TxAf6XEAxIbEkFLJkW1hmNz32vJybUWSUmuUQGz3/6Xy t7fJa83c5IVzo9qq1teGSJb9b7NswnaVq147rtKlIG97SrvBI5v0qWBatUosheWoCvlj wEMQ== X-Gm-Message-State: AOUpUlG8OFIMgs3zQ5kPnkkJ+Z7/wxzFFEJN/2RbSRfMEXft/z/vJkKh C1ydHHOFG2V+XoCZ8ZaEyPgyCte0WSS02g== X-Google-Smtp-Source: AAOMgpcnb/ylx2GiAJpxwGX7X/TCqlJOTfn4wuOGI8Mmzu5pLbZsZHiO/biNJQKoyd1LjugLtN62NQ== X-Received: by 2002:ae9:ed82:: with SMTP id c124-v6mr3905487qkg.303.1532133837854; Fri, 20 Jul 2018 17:43:57 -0700 (PDT) Received: from ?IPv6:2601:153:601:7d2a::100b? ([2601:153:601:7d2a::100b]) by smtp.gmail.com with ESMTPSA id i24-v6sm2407180qti.28.2018.07.20.17.43.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 20 Jul 2018 17:43:57 -0700 (PDT) From: Peter Geis Subject: [PATCH 2/2] Add support for CPCAP regulators on Tegra devices. To: lgirdwood@gmail.com Cc: broonie@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org Message-ID: <1abd663a-7f3f-d7cd-2329-e59b301aef6f@gmail.com> Date: Fri, 20 Jul 2018 20:43:56 -0400 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.9.1 MIME-Version: 1.0 Content-Language: en-US Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Added support for the CPCAP power management regulator functions on Tegra devices. Added sw2_sw4 value tables, which provide power to the Tegra core and aux devices. Added the Tegra init tables and device tree compatibility match. Signed-off-by: Peter Geis --- .../bindings/regulator/cpcap-regulator.txt | 1 + drivers/regulator/cpcap-regulator.c | 80 +++++++++++++++++++ 2 files changed, 81 insertions(+) MODULE_DEVICE_TABLE(of, cpcap_regulator_id_table); diff --git a/Documentation/devicetree/bindings/regulator/cpcap-regulator.txt b/Documentation/devicetree/bindings/regulator/cpcap-regulator.txt index 675f4437ce92..3e2d33ab1731 100644 --- a/Documentation/devicetree/bindings/regulator/cpcap-regulator.txt +++ b/Documentation/devicetree/bindings/regulator/cpcap-regulator.txt @@ -4,6 +4,7 @@ Motorola CPCAP PMIC voltage regulators Requires node properties: - "compatible" value one of: "motorola,cpcap-regulator" + "motorola,tegra-cpcap-regulator" "motorola,mapphone-cpcap-regulator" Required regulator properties: diff --git a/drivers/regulator/cpcap-regulator.c b/drivers/regulator/cpcap-regulator.c index c0b1e04bd90f..cb3774be445d 100644 --- a/drivers/regulator/cpcap-regulator.c +++ b/drivers/regulator/cpcap-regulator.c @@ -412,6 +412,82 @@ static struct cpcap_regulator omap4_regulators[] = { { /* sentinel */ }, }; +static struct cpcap_regulator tegra_regulators[] = { + CPCAP_REG(SW1, CPCAP_REG_S1C1, CPCAP_REG_ASSIGN2, + CPCAP_BIT_SW1_SEL, unknown_val_tbl, + 0, 0, 0, 0, 0, 0), + CPCAP_REG(SW2, CPCAP_REG_S2C1, CPCAP_REG_ASSIGN2, + CPCAP_BIT_SW2_SEL, sw2_sw4_val_tbl, + 0xf00, 0x7f, 0, 0x800, 0, 120), + CPCAP_REG(SW3, CPCAP_REG_S3C, CPCAP_REG_ASSIGN2, + CPCAP_BIT_SW3_SEL, unknown_val_tbl, + 0, 0, 0, 0, 0, 0), + CPCAP_REG(SW4, CPCAP_REG_S4C1, CPCAP_REG_ASSIGN2, + CPCAP_BIT_SW4_SEL, sw2_sw4_val_tbl, + 0xf00, 0x7f, 0, 0x900, 0, 100), + CPCAP_REG(SW5, CPCAP_REG_S5C, CPCAP_REG_ASSIGN2, + CPCAP_BIT_SW5_SEL, sw5_val_tbl, + 0x2a, 0, 0, 0x22, 0, 0), + CPCAP_REG(SW6, CPCAP_REG_S6C, CPCAP_REG_ASSIGN2, + CPCAP_BIT_SW6_SEL, unknown_val_tbl, + 0, 0, 0, 0, 0, 0), + CPCAP_REG(VCAM, CPCAP_REG_VCAMC, CPCAP_REG_ASSIGN2, + CPCAP_BIT_VCAM_SEL, vcam_val_tbl, + 0x87, 0x30, 4, 0x7, 0, 420), + CPCAP_REG(VCSI, CPCAP_REG_VCSIC, CPCAP_REG_ASSIGN3, + CPCAP_BIT_VCSI_SEL, vcsi_val_tbl, + 0x47, 0x10, 4, 0x7, 0, 350), + CPCAP_REG(VDAC, CPCAP_REG_VDACC, CPCAP_REG_ASSIGN3, + CPCAP_BIT_VDAC_SEL, vdac_val_tbl, + 0x87, 0x30, 4, 0x3, 0, 420), + CPCAP_REG(VDIG, CPCAP_REG_VDIGC, CPCAP_REG_ASSIGN2, + CPCAP_BIT_VDIG_SEL, vdig_val_tbl, + 0x87, 0x30, 4, 0x5, 0, 420), + CPCAP_REG(VFUSE, CPCAP_REG_VFUSEC, CPCAP_REG_ASSIGN3, + CPCAP_BIT_VFUSE_SEL, vfuse_val_tbl, + 0x80, 0xf, 0, 0x80, 0, 420), + CPCAP_REG(VHVIO, CPCAP_REG_VHVIOC, CPCAP_REG_ASSIGN3, + CPCAP_BIT_VHVIO_SEL, vhvio_val_tbl, + 0x17, 0, 0, 0x2, 0, 0), + CPCAP_REG(VSDIO, CPCAP_REG_VSDIOC, CPCAP_REG_ASSIGN2, + CPCAP_BIT_VSDIO_SEL, vsdio_val_tbl, + 0x87, 0x38, 3, 0x2, 0, 420), + CPCAP_REG(VPLL, CPCAP_REG_VPLLC, CPCAP_REG_ASSIGN3, + CPCAP_BIT_VPLL_SEL, vpll_val_tbl, + 0x43, 0x18, 3, 0x1, 0, 420), + CPCAP_REG(VRF1, CPCAP_REG_VRF1C, CPCAP_REG_ASSIGN3, + CPCAP_BIT_VRF1_SEL, vrf1_val_tbl, + 0xac, 0x2, 1, 0xc, 0, 10), + CPCAP_REG(VRF2, CPCAP_REG_VRF2C, CPCAP_REG_ASSIGN3, + CPCAP_BIT_VRF2_SEL, vrf2_val_tbl, + 0x23, 0x8, 3, 0x3, 0, 10), + CPCAP_REG(VRFREF, CPCAP_REG_VRFREFC, CPCAP_REG_ASSIGN3, + CPCAP_BIT_VRFREF_SEL, vrfref_val_tbl, + 0x23, 0x8, 3, 0x3, 0, 420), + CPCAP_REG(VWLAN1, CPCAP_REG_VWLAN1C, CPCAP_REG_ASSIGN3, + CPCAP_BIT_VWLAN1_SEL, vwlan1_val_tbl, + 0x47, 0x10, 4, 0x5, 0, 420), + CPCAP_REG(VWLAN2, CPCAP_REG_VWLAN2C, CPCAP_REG_ASSIGN3, + CPCAP_BIT_VWLAN2_SEL, vwlan2_val_tbl, + 0x20c, 0xc0, 6, 0x8, 0, 420), + CPCAP_REG(VSIM, CPCAP_REG_VSIMC, CPCAP_REG_ASSIGN3, + 0xffff, vsim_val_tbl, + 0x23, 0x8, 3, 0x3, 0, 420), + CPCAP_REG(VSIMCARD, CPCAP_REG_VSIMC, CPCAP_REG_ASSIGN3, + 0xffff, vsimcard_val_tbl, + 0x1e80, 0x8, 3, 0x1e00, 0, 420), + CPCAP_REG(VVIB, CPCAP_REG_VVIBC, CPCAP_REG_ASSIGN3, + CPCAP_BIT_VVIB_SEL, vvib_val_tbl, + 0x1, 0xc, 2, 0, 0x1, 500), + CPCAP_REG(VUSB, CPCAP_REG_VUSBC, CPCAP_REG_ASSIGN3, + CPCAP_BIT_VUSB_SEL, vusb_val_tbl, + 0x11c, 0x40, 6, 0xc, 0, 0), + CPCAP_REG(VAUDIO, CPCAP_REG_VAUDIOC, CPCAP_REG_ASSIGN4, + CPCAP_BIT_VAUDIO_SEL, vaudio_val_tbl, + 0x16, 0x1, 0, 0x4, 0, 0), + { /* sentinel */ }, +}; + static const struct of_device_id cpcap_regulator_id_table[] = { { .compatible = "motorola,cpcap-regulator", @@ -420,6 +496,10 @@ static const struct of_device_id cpcap_regulator_id_table[] = { .compatible = "motorola,mapphone-cpcap-regulator", .data = omap4_regulators, }, + { + .compatible = "motorola,tegra-cpcap-regulator", + .data = tegra_regulators, + }, {}, };