From patchwork Thu Jul 19 13:21:25 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 946303 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="EAHerfIF"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 41WZTG59T4z9s4s for ; Thu, 19 Jul 2018 23:23:14 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731811AbeGSOFp (ORCPT ); Thu, 19 Jul 2018 10:05:45 -0400 Received: from mail-lj1-f196.google.com ([209.85.208.196]:46592 "EHLO mail-lj1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731126AbeGSOFn (ORCPT ); Thu, 19 Jul 2018 10:05:43 -0400 Received: by mail-lj1-f196.google.com with SMTP id 203-v6so7429951ljj.13; Thu, 19 Jul 2018 06:22:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=9w9JS9k45Mkm5m6z6QbcilGriIHYUaz9xF/Kh7/wMsg=; b=EAHerfIFmDkA4tYulL8XOj7zSQ/Tj5C9ju7Rz0va8KSfSrWFzC4ZcgcllmTOujnfca ZUBE28NQ/q3xnoxlixGXAomAq3892SYnNp3FgpQxQTL7dbivnpf+y5NhRs4VgDzEP2rW gzWs0S9iYoFCfrl5hUlYxknRl0axXRiYC/+7c693cUZ0G62cKBYsLFoDGSyJi46Z6VFT sew2kvNHc/qbWx4uf8+YIP/OkxrlevkDmPfO4jNIHFig9NcHKCEnG/zAEzyEl3SoHW3P jFnfjUdGQ9V/bWrvd5S8JBG5PH3W0VYBNGT/vF2BwCvikJzYr+h1YAJQiBklwLxesPCq 5M7g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=9w9JS9k45Mkm5m6z6QbcilGriIHYUaz9xF/Kh7/wMsg=; b=Bymxq2hZMT0+OWf75kuXZfKm3ynGm0WNzn499mr7R1l93CgQMnxVrWHvVi5RvTCo2+ ldMRnSDuZ4yiVJa6Sg8nUugGZPxs+WQ7JexbYqCpfm+shsdZ+jc6JjovcQ/+SWwdMzu1 ZF3LPWNpRxE+VOjIn7FpIP9x/S3hx2suhLOtuKXn/CTZtKKNbsKzkBIRyOwljRfMzrHw J4xAqPHolGfsfs6nsIdcBCFNbtS+Wtr7z4EExjDNRn5Tw2qUaDpQe/ERzwRUjLLSJuyK 0Dq1sNjlmpM88bKQfj1SjPwgxtHNk5eGOwUunYHX9a8pT8ZpjG1zRfZr5pFzXiC/AB+0 X+wg== X-Gm-Message-State: AOUpUlGk+hC0fZPBTEl5JYaoaZV54qUZ8GikpSc9y9Dgl6cFd8buMep7 yfFNyj36KQxPrfq46a7Ws0o= X-Google-Smtp-Source: AAOMgpeUJj0VElUl7eydUGd2K1JU6oGOLSPyPgADmuSi2b4wZult1THA8Th28ZC341I3ndOsxedX/A== X-Received: by 2002:a2e:5c4:: with SMTP id 187-v6mr7444933ljf.28.1532006552285; Thu, 19 Jul 2018 06:22:32 -0700 (PDT) Received: from localhost.localdomain ([109.252.91.91]) by smtp.gmail.com with ESMTPSA id o4-v6sm1109592ljc.67.2018.07.19.06.22.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 19 Jul 2018 06:22:31 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Peter De Schrijver , Jonathan Hunter , Prashant Gaikwad , Michael Turquette , Stephen Boyd Cc: Rob Herring , linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 1/8] dt: bindings: tegra20-emc: Document interrupt property Date: Thu, 19 Jul 2018 16:21:25 +0300 Message-Id: <20180719132132.16153-2-digetx@gmail.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180719132132.16153-1-digetx@gmail.com> References: <20180719132132.16153-1-digetx@gmail.com> Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org EMC has a dedicated interrupt that is used to notify about completion of HW operations. Document the interrupt property. Signed-off-by: Dmitry Osipenko Acked-by: Rob Herring Acked-by: Peter De Schrijver --- .../devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt index 4c33b29dc660..a6fe401d0d48 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt @@ -10,6 +10,7 @@ Properties: and chosen using the ramcode board selector. If omitted, only one set of tables can be present and said tables will be used irrespective of ram-code configuration. +- interrupts : Should contain EMC General interrupt. Child device nodes describe the memory settings for different configurations and clock rates. @@ -20,6 +21,7 @@ Example: #size-cells = < 0 >; compatible = "nvidia,tegra20-emc"; reg = <0x7000f4000 0x200>; + interrupts = <0 78 0x04>; } From patchwork Thu Jul 19 13:21:26 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 946306 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="ppGlSjsk"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 41WZTc29W7z9s9l for ; Thu, 19 Jul 2018 23:23:32 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731773AbeGSOFp (ORCPT ); Thu, 19 Jul 2018 10:05:45 -0400 Received: from mail-lj1-f195.google.com ([209.85.208.195]:33695 "EHLO mail-lj1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727367AbeGSOFo (ORCPT ); Thu, 19 Jul 2018 10:05:44 -0400 Received: by mail-lj1-f195.google.com with SMTP id s12-v6so7475224ljj.0; Thu, 19 Jul 2018 06:22:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=hdPussaMOwx5eq9zggMvF7xXCLAv98sIlWjHG9vkK3o=; b=ppGlSjskJZzjWU6zHPqMGhG+mbxVT6Z+6i9CqgyWopPwDXTZNOYsa0chjjJIJv4N3/ f3sTwPC3k5/7Rt9vSf3toMFc8ti8eTd/il1YvvKXhu+UIXmP33M1D7SBguMPQMIjasC/ akIoFQYHrYPXk2kblCsw43s5nuK3gTwvjjlwzFCnipX30r7GMa/iK0OFh/lbLkuYzxGM IlOlJ5eP7GxVmZQStFt0bRFc43ljCXcLQ4c0t31hQWbx18bfBh9SlvGxZ6MhTsIztPwW lx6rkvCwPkkPaq+y463qFLDHHen4O3rEtUOvxcszxsEI+xN7uaHjQUZeThAvNX9h/wAk b94Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=hdPussaMOwx5eq9zggMvF7xXCLAv98sIlWjHG9vkK3o=; b=gv+ORUpTe5jTfsk7T3iLPRpMifLbINnau0odU7ihlF9IJibeZy6q8/wWECDrz9p6Ky dzix98PQqsEnLumVd1h9Bl/kgfeNczbZmJCHT7+2qy606mCAO5pIa4ZRYSU4jLaC7sBj KpsaBAA+gXS1ehqvnuRaEVF0T8oFlpS+YQLZ2fpokpARtBVF4cjuTTljR/JTPJpeslG4 2sn/16SM8YAIHJnHsUXbFGZzbshnM5AaWcA6BQpC0rQ7ZovKDCwXj8ZIx9m78515RRqw bfeVGjb4c+TjN/WdyR+r6jLgDsCOL0cH/TI4ZjDclZZiJCQSyeXgmoZDoUikVzZqh3aA y63A== X-Gm-Message-State: AOUpUlFRWd4X82gvu5WsBqSVLgqiannLKQ4pKf7Z8e+u69TbHkMKsys+ KrcyZJlFDKdRX4EF52VGeo4= X-Google-Smtp-Source: AAOMgpcGrRtxxDQAMmBrHhZnMGwp4lEiDZrUL0TQrtj5Zznk5JeQqNgk66icIG1o4WLraNt4qrhy3w== X-Received: by 2002:a2e:4951:: with SMTP id b17-v6mr7635973ljd.67.1532006553342; Thu, 19 Jul 2018 06:22:33 -0700 (PDT) Received: from localhost.localdomain ([109.252.91.91]) by smtp.gmail.com with ESMTPSA id o4-v6sm1109592ljc.67.2018.07.19.06.22.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 19 Jul 2018 06:22:32 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Peter De Schrijver , Jonathan Hunter , Prashant Gaikwad , Michael Turquette , Stephen Boyd Cc: Rob Herring , linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 2/8] dt: bindings: tegra20-emc: Document clock property Date: Thu, 19 Jul 2018 16:21:26 +0300 Message-Id: <20180719132132.16153-3-digetx@gmail.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180719132132.16153-1-digetx@gmail.com> References: <20180719132132.16153-1-digetx@gmail.com> Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Embedded memory controller has a corresponding clock, document the clock property. Signed-off-by: Dmitry Osipenko Acked-by: Rob Herring --- .../devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt index a6fe401d0d48..add95367640b 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt @@ -11,6 +11,7 @@ Properties: set of tables can be present and said tables will be used irrespective of ram-code configuration. - interrupts : Should contain EMC General interrupt. +- clocks : Should contain EMC clock. Child device nodes describe the memory settings for different configurations and clock rates. @@ -22,6 +23,7 @@ Example: compatible = "nvidia,tegra20-emc"; reg = <0x7000f4000 0x200>; interrupts = <0 78 0x04>; + clocks = <&tegra_car TEGRA20_CLK_EMC>; } From patchwork Thu Jul 19 13:21:27 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 946304 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="p1XGFtc9"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 41WZTV5Jndz9s5c for ; Thu, 19 Jul 2018 23:23:26 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731587AbeGSOGW (ORCPT ); Thu, 19 Jul 2018 10:06:22 -0400 Received: from mail-lj1-f196.google.com ([209.85.208.196]:38722 "EHLO mail-lj1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731769AbeGSOFp (ORCPT ); Thu, 19 Jul 2018 10:05:45 -0400 Received: by mail-lj1-f196.google.com with SMTP id p6-v6so7456956ljc.5; Thu, 19 Jul 2018 06:22:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=UhBtfyk6EpvGULLmrb67ektbatVXeOakArBXKH6UOYo=; b=p1XGFtc9QJIOZbR0euzyexClOKel95qWYH0H9R5X5Do6Zmuy1OHC+cPxdmgs9T6z9T k5MP66+7CcAXkow65zwjEdizmhCBPMhEvEKPw4rzxxCV3GCIaNd+alN4d4jsMe/EekK0 lFB/UNtASP043taUspo5hx9fRps1HEs1FfJKD+6oafqV+tnhFqtaPaK6vgKhJaNKN9wv JLuOyXj4GSGogVI2QC5SoL7Ik8tyo9a+cz+ii89Qrf/DRO6qjjwkLTUXzM0IErldS9iT bS3tLi3vkLhgm8Z2U/0Kl9sy3Vm7ZPDQnLyvwYiOJ1fAliQCxCtf2+5SAuVhX8iEnW2h Fd+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=UhBtfyk6EpvGULLmrb67ektbatVXeOakArBXKH6UOYo=; b=q4IAknmXRL/GvZ7wyaKWFp4hRPYelneZlEH7j1CoxYd5ix/rhJN1fhZTvH4lARv+jh BJ5E987cEhXqkjP/FBA+90tcoBF+iQR23CEmOJuXsP7hKjQh1rjToMgaiYYzF5IH/znL bRvFWrTjh8oAqvRuj6Lxocx+/F+t9xFd877I0l1qusenUnOskAngLelTxyZ9PvqLF9NE DDMGoJlc8KxzC/rll0pKSPy0h5+JZhRvQsLdnzjW8z04VsN1yYcaFjLA8Y9xySC9jts7 cxzCsMRoBvnFiu6WR0mGfGI67IxqLEW2dsNZr42DDVD7CmaCEK1Oh+Zds/nmcLCHIfZ8 dqPw== X-Gm-Message-State: AOUpUlGcPnJK/J0wGh9E7Ldd/GVj6t7S+3LI/8oELFvCsivtCzcpgE01 SVzYGQP7IgURcj3cXEX3kQ4= X-Google-Smtp-Source: AAOMgpejw9fp6ufe1zygZXUL0oD2TrbvGbp+cue9gOc9kXllhDsYgzRP47BSJ2mpnKrvB+KeBQOlDQ== X-Received: by 2002:a19:a111:: with SMTP id k17-v6mr6351591lfe.131.1532006554321; Thu, 19 Jul 2018 06:22:34 -0700 (PDT) Received: from localhost.localdomain ([109.252.91.91]) by smtp.gmail.com with ESMTPSA id o4-v6sm1109592ljc.67.2018.07.19.06.22.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 19 Jul 2018 06:22:33 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Peter De Schrijver , Jonathan Hunter , Prashant Gaikwad , Michael Turquette , Stephen Boyd Cc: Rob Herring , linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 3/8] dt: bindings: Move tegra20-emc binding to memory-controllers directory Date: Thu, 19 Jul 2018 16:21:27 +0300 Message-Id: <20180719132132.16153-4-digetx@gmail.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180719132132.16153-1-digetx@gmail.com> References: <20180719132132.16153-1-digetx@gmail.com> Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Move tegra20-emc binding to the memory-controllers directory for consistency with the other Tegra memory bindings. Signed-off-by: Dmitry Osipenko Acked-by: Rob Herring --- .../{arm/tegra => memory-controllers}/nvidia,tegra20-emc.txt | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename Documentation/devicetree/bindings/{arm/tegra => memory-controllers}/nvidia,tegra20-emc.txt (100%) diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt similarity index 100% rename from Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt rename to Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt From patchwork Thu Jul 19 13:21:28 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 946302 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="XM4+e128"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 41WZTC1Hk5z9sB4 for ; Thu, 19 Jul 2018 23:23:11 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731829AbeGSOFr (ORCPT ); Thu, 19 Jul 2018 10:05:47 -0400 Received: from mail-lj1-f193.google.com ([209.85.208.193]:44091 "EHLO mail-lj1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731595AbeGSOFq (ORCPT ); Thu, 19 Jul 2018 10:05:46 -0400 Received: by mail-lj1-f193.google.com with SMTP id q127-v6so7448618ljq.11; Thu, 19 Jul 2018 06:22:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=rVKbXczfv+RzlB+yL++j1SAXIAyX+n3XTuzqDXSqkC8=; b=XM4+e128G+4dnXkKsRga44iXN4XFPBPWDKXDIf7QfoZPuy6Pj6srjXyFl0321kmGyx 9U65epQDzxQ6UosSLzx2PViJkIFVMpIm6bTAhwCezE1FVmOXj51oYCLBB1A/27hBRfkU CtnzS0AfwIkSd/Sc306hZv7V+feHpTLPh2iRNAeD9r080skzOrDZwB7d4jMOth9nIO+w YpuIT6uP3HSRZiG31mti6bK6QnEPmymCIKzBQDGVD19IHy8cV3m/YeXelsXBfWdkfsas YC1ZpwLeIKUKXSNpsN1PqlEi+k3j8Fn6nE+3z8pNg8e3CraYnAknMrmy/zcNCbdcdt4K c00A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=rVKbXczfv+RzlB+yL++j1SAXIAyX+n3XTuzqDXSqkC8=; b=WUigv2dtdQC73onsbJbrDrOW8dl/AZ3KgWMhIIfUlPLRR+R8K7gwpUxVonmFVb+8wv qA4n4krTE0h3hV4Js6awJYrYTfGsWmiuSekpfpHoB2p/yTw7cP85br6V1/JafX8Frpns sK2Hkf+WTDCdbtBxXgtMbXKR+imweWtQnrVAE7y295GTq/19zMRiYqy3Frjf3pSbm7FS xRe940M+ZDqASLc0zWD5KV417ogEC8k6YENWLAHfXWLNALUVBH0l9BpqnDoYDxbKZlw7 htk3rBqtOX+bFRoI22Wf4nHd+Ck/5FmqZazcOuCDYrd6Uj6YEV8z1qaB9fRhhRPLnUpZ qSKA== X-Gm-Message-State: AOUpUlELzk6IDPAGFUbOwmjrXSbjZVD0Q3Go/YpTa3py0s9x9n3hLTjr 7d1aw6TNKYEMVjGdiSPsRA4= X-Google-Smtp-Source: AAOMgpf+kkIHPbx7aHbpOO5Vn63r7aviH0ihN99p+wVaaVh1KIWgkuTj4NCfFx9Ga7uY4uZmW9QDqQ== X-Received: by 2002:a19:548e:: with SMTP id b14-v6mr6414020lfl.10.1532006555250; Thu, 19 Jul 2018 06:22:35 -0700 (PDT) Received: from localhost.localdomain ([109.252.91.91]) by smtp.gmail.com with ESMTPSA id o4-v6sm1109592ljc.67.2018.07.19.06.22.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 19 Jul 2018 06:22:34 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Peter De Schrijver , Jonathan Hunter , Prashant Gaikwad , Michael Turquette , Stephen Boyd Cc: Rob Herring , linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 4/8] ARM: dts: tegra20: Add interrupt entry to External Memory Controller Date: Thu, 19 Jul 2018 16:21:28 +0300 Message-Id: <20180719132132.16153-5-digetx@gmail.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180719132132.16153-1-digetx@gmail.com> References: <20180719132132.16153-1-digetx@gmail.com> Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Add interrupt entry into the EMC DT node. Signed-off-by: Dmitry Osipenko Acked-by: Peter De Schrijver --- arch/arm/boot/dts/tegra20.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 15b73bd377f0..9eb4163a4390 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -632,6 +632,7 @@ memory-controller@7000f400 { compatible = "nvidia,tegra20-emc"; reg = <0x7000f400 0x200>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; }; From patchwork Thu Jul 19 13:21:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 946298 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="KngN6QU5"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 41WZSf6N5pz9s55 for ; Thu, 19 Jul 2018 23:22:42 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731848AbeGSOFt (ORCPT ); Thu, 19 Jul 2018 10:05:49 -0400 Received: from mail-lj1-f194.google.com ([209.85.208.194]:44095 "EHLO mail-lj1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727501AbeGSOFs (ORCPT ); Thu, 19 Jul 2018 10:05:48 -0400 Received: by mail-lj1-f194.google.com with SMTP id q127-v6so7448784ljq.11; Thu, 19 Jul 2018 06:22:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=xr6zoJuis9T7PH6Y1NR12kXsVCPvALyX6ctcsGCCpqU=; b=KngN6QU5bU5Mbn7XwjDYx8vqiezrzzRifZ7ugsuAsgbzIhGO2gb0z0elyB7HujwNAS oMD1d1Qtr6Cw2vkHjrr/aBk3dm14jps4LFwJCEwX0LzlyMJr7XxE4W4J6Sxgw9EuMJlu ILnO2Q+txZHhT4u/vXDmDalmkXoN1RhPrGedIH7vJzN6dopmBmZskCJYIBEZb7BHMW0p wwsPyItk6mZ9ZKzO5nziAAjpsvcgwKm7KXuvM7zjwUXSc8SRFnxVEKZN7MEla4Q//ycN QAQNuNq82aIQRuKh9+3EYS3withKN4q9KQq/QZ2Nygoxdp6HgR/9Y+ru5xX0T06fXvsD 4PRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=xr6zoJuis9T7PH6Y1NR12kXsVCPvALyX6ctcsGCCpqU=; b=Ol1PgQV5uNidpxl7lha7KS41pBw58d4yoY9Lj66kx8weOye7zgFuKRLcLmSGc4mWWQ Bqy+5WJL9aasB3OWlua0tahVivNrKJp+FNOcvK49HGvtkX/eSl4Or+h2VBg+XV1qv6B4 HRdsVF8u2jtItCLV1T0mQs2T6a3TMhciTmSxWz2CMbLYL3FCzm8jOJbcpc03ywt3abh5 MyoRCKqPCyy/onBcLmsvw0UKkTh7+yybuAT2azllSt5yWVcbEC5QYGSOnRXjbpBlp55W WMAn80K3pfjZ1wp3s1W9lo9DsRDE/UWVPG4ne9+cmzP8x/gU2Cwpn7lVclMep0WvCa4f cMbQ== X-Gm-Message-State: AOUpUlFNhnZrRfVgVOAMNldtaS0+Wvp2Qqv5dP/c1peDi8bIHFfwYQwe yrTwpOwCrWJiTb9vdJ2T4haDmO6w X-Google-Smtp-Source: AAOMgpdQ1WDR3GCIiT0QYuTwH4S3+f1IoR5g7dDCRFWkE6jhbMSVDvh6HdjvFLzgOLpKvlSXDEQWOw== X-Received: by 2002:a19:5418:: with SMTP id i24-v6mr6429942lfb.34.1532006556228; Thu, 19 Jul 2018 06:22:36 -0700 (PDT) Received: from localhost.localdomain ([109.252.91.91]) by smtp.gmail.com with ESMTPSA id o4-v6sm1109592ljc.67.2018.07.19.06.22.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 19 Jul 2018 06:22:35 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Peter De Schrijver , Jonathan Hunter , Prashant Gaikwad , Michael Turquette , Stephen Boyd Cc: Rob Herring , linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 5/8] ARM: dts: tegra20: Add clock entry to External Memory Controller Date: Thu, 19 Jul 2018 16:21:29 +0300 Message-Id: <20180719132132.16153-6-digetx@gmail.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180719132132.16153-1-digetx@gmail.com> References: <20180719132132.16153-1-digetx@gmail.com> Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Add clock entry into the EMC DT node. Signed-off-by: Dmitry Osipenko --- arch/arm/boot/dts/tegra20.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 9eb4163a4390..979f38293fe5 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -633,6 +633,7 @@ compatible = "nvidia,tegra20-emc"; reg = <0x7000f400 0x200>; interrupts = ; + clocks = <&tegra_car TEGRA20_CLK_EMC>; #address-cells = <1>; #size-cells = <0>; }; From patchwork Thu Jul 19 13:21:30 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 946301 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="ImysuCnx"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 41WZT55FThz9s5c for ; Thu, 19 Jul 2018 23:23:05 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731595AbeGSOGG (ORCPT ); Thu, 19 Jul 2018 10:06:06 -0400 Received: from mail-lj1-f193.google.com ([209.85.208.193]:44096 "EHLO mail-lj1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731842AbeGSOFu (ORCPT ); Thu, 19 Jul 2018 10:05:50 -0400 Received: by mail-lj1-f193.google.com with SMTP id q127-v6so7448878ljq.11; Thu, 19 Jul 2018 06:22:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=SQTRny113LNxRmec6/bLm6uD/H077n6KTOjiQBp4Z2E=; b=ImysuCnxjnONLCLMs2o22bUfWnWkxZ7xAqrNFzsiHTlIBTNumCNGADwVx1+JZg6yPh VP0uONv/f1ilnGQ/bfXceYazfGrGDMiSFLaRt7QKDDuX4F8ThwBi8DLvncHFY3zUJkej VaXeisj9a6BrCZsjBJ1IiY0QabE2sC3/RNV7YiYXon56Qny9dynDnGqc6KmgGbTSw0Rn cLsMdLOefLld0XwvQDLz3PeDhpjFoth3u0j8eroHwQcGHaTUNJ8ccdHpSfhXTtvl9tYO /7D9vqT1CPxee4s6jR7rxEZVV2zAyEvG+KVigL4FMq76B2xfjRAzXQ2Xf45LMQ5wtkQ8 A0ug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=SQTRny113LNxRmec6/bLm6uD/H077n6KTOjiQBp4Z2E=; b=M41uLjxJBrjO6FSJ2aPC6xsrnJEru8YzjLXEZKrnCnG8fTMrZMyiZ1jmXMJMqL2ver go0IHpPfh14tPKEvENOOdBDyToQdNCorw1JesifZi509XL0RFiNktL1iVbTy3RESAhfo 4JlvPFkMwu4ImOvxp6VO/XQh4B2hBCgeTlDdUMrwOHiYqSXIxiT3uHg4q28Dy96fnBvG SeIrMHd/AZvp0RzyNXvhbqz3Fj45WeDSvI95LTOV09GbSg6n8NnAEfnuJKlIbqbtsMzI pEFKgGvQEvX+owmDn7NX//8SBBxbVr4IXS1weOx5kvV/gGlNob4fJmOk3baKKTUDFuYw 4RSQ== X-Gm-Message-State: AOUpUlHUqnhFWfUZDHfKT7nckRskH9pCCk1u9H9vc1phkHLNMFpp+ght j0a7+pCdca3J1bFAj8BfphU= X-Google-Smtp-Source: AAOMgpeQX+45OePCxhxrcBMsFVl2i5tI/svKtqejyfV5gW0mSe1zkB1GKRJ0qAA26hsQ0rJNyLjaUw== X-Received: by 2002:a19:7403:: with SMTP id v3-v6mr3050376lfe.97.1532006557234; Thu, 19 Jul 2018 06:22:37 -0700 (PDT) Received: from localhost.localdomain ([109.252.91.91]) by smtp.gmail.com with ESMTPSA id o4-v6sm1109592ljc.67.2018.07.19.06.22.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 19 Jul 2018 06:22:36 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Peter De Schrijver , Jonathan Hunter , Prashant Gaikwad , Michael Turquette , Stephen Boyd Cc: Rob Herring , linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 6/8] clk: tegra20: Turn EMC clock gate into divider Date: Thu, 19 Jul 2018 16:21:30 +0300 Message-Id: <20180719132132.16153-7-digetx@gmail.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180719132132.16153-1-digetx@gmail.com> References: <20180719132132.16153-1-digetx@gmail.com> Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Kernel should never gate the EMC clock as it causes immediate lockup, so removing clk-gate functionality doesn't affect anything. Turning EMC clk gate into divider allows to implement glitch-less EMC scaling, avoiding reparenting to a backup clock. Signed-off-by: Dmitry Osipenko Acked-by: Peter De Schrijver --- drivers/clk/tegra/clk-tegra20.c | 36 ++++++++++++++++++++++++--------- 1 file changed, 26 insertions(+), 10 deletions(-) diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index cc857d4d4a86..ebea97016d58 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -578,7 +578,6 @@ static struct tegra_clk tegra20_clks[tegra_clk_max] __initdata = { [tegra_clk_afi] = { .dt_id = TEGRA20_CLK_AFI, .present = true }, [tegra_clk_fuse] = { .dt_id = TEGRA20_CLK_FUSE, .present = true }, [tegra_clk_kfuse] = { .dt_id = TEGRA20_CLK_KFUSE, .present = true }, - [tegra_clk_emc] = { .dt_id = TEGRA20_CLK_EMC, .present = true }, }; static unsigned long tegra20_clk_measure_input_freq(void) @@ -799,6 +798,31 @@ static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = { TEGRA_INIT_DATA_NODIV("disp2", mux_pllpdc_clkm, CLK_SOURCE_DISP2, 30, 2, 26, 0, TEGRA20_CLK_DISP2), }; +static void __init tegra20_emc_clk_init(void) +{ + struct clk *clk; + + clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm, + ARRAY_SIZE(mux_pllmcp_clkm), + CLK_SET_RATE_NO_REPARENT, + clk_base + CLK_SOURCE_EMC, + 30, 2, 0, &emc_lock); + + clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC, + &emc_lock); + clks[TEGRA20_CLK_MC] = clk; + + /* + * Note that 'emc_mux' source and 'emc' rate shouldn't be changed at + * the same time due to a HW bug, this won't happen because we're + * defining 'emc_mux' and 'emc' as distinct clocks. + */ + clk = clk_register_divider(NULL, "emc", "emc_mux", CLK_IS_CRITICAL, + clk_base + CLK_SOURCE_EMC, 0, 7, + 0, &emc_lock); + clks[TEGRA20_CLK_EMC] = clk; +} + static void __init tegra20_periph_clk_init(void) { struct tegra_periph_init_data *data; @@ -812,15 +836,7 @@ static void __init tegra20_periph_clk_init(void) clks[TEGRA20_CLK_AC97] = clk; /* emc */ - clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm, - ARRAY_SIZE(mux_pllmcp_clkm), - CLK_SET_RATE_NO_REPARENT, - clk_base + CLK_SOURCE_EMC, - 30, 2, 0, &emc_lock); - - clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC, - &emc_lock); - clks[TEGRA20_CLK_MC] = clk; + tegra20_emc_clk_init(); /* dsi */ clk = tegra_clk_register_periph_gate("dsi", "pll_d", 0, clk_base, 0, From patchwork Thu Jul 19 13:21:31 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 946300 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="sd+OEi5b"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 41WZSx4HRpz9s9G for ; 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Thu, 19 Jul 2018 06:22:37 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Peter De Schrijver , Jonathan Hunter , Prashant Gaikwad , Michael Turquette , Stephen Boyd Cc: Rob Herring , linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 7/8] clk: tegra20: Check whether direct PLLM sourcing is turned off for EMC Date: Thu, 19 Jul 2018 16:21:31 +0300 Message-Id: <20180719132132.16153-8-digetx@gmail.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180719132132.16153-1-digetx@gmail.com> References: <20180719132132.16153-1-digetx@gmail.com> Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Ensure that direct PLLM sourcing is turned off for EMC as we don't support that configuration in the clk driver. Signed-off-by: Dmitry Osipenko Acked-by: Peter De Schrijver --- drivers/clk/tegra/clk-tegra20.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index ebea97016d58..e1f039aa8ca9 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -800,7 +800,9 @@ static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = { static void __init tegra20_emc_clk_init(void) { + const u32 use_pllm_ud = BIT(29); struct clk *clk; + u32 emc_reg; clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm, ARRAY_SIZE(mux_pllmcp_clkm), @@ -812,6 +814,14 @@ static void __init tegra20_emc_clk_init(void) &emc_lock); clks[TEGRA20_CLK_MC] = clk; + /* un-divided pll_m_out0 is currently unsupported */ + emc_reg = readl_relaxed(clk_base + CLK_SOURCE_EMC); + if (emc_reg & use_pllm_ud) { + pr_err("%s: un-divided PllM_out0 used as clock source\n", + __func__); + return; + } + /* * Note that 'emc_mux' source and 'emc' rate shouldn't be changed at * the same time due to a HW bug, this won't happen because we're From patchwork Thu Jul 19 13:21:32 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 946299 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="HMtjhQIb"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 41WZSs4npbz9s8f for ; Thu, 19 Jul 2018 23:22:53 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731889AbeGSOFv (ORCPT ); Thu, 19 Jul 2018 10:05:51 -0400 Received: from mail-lj1-f196.google.com ([209.85.208.196]:41510 "EHLO mail-lj1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731595AbeGSOFv (ORCPT ); Thu, 19 Jul 2018 10:05:51 -0400 Received: by mail-lj1-f196.google.com with SMTP id y17-v6so7454529ljy.8; Thu, 19 Jul 2018 06:22:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=KujdazEonh8hoTE6UrQ09RC6Ad/DxZja9GU4lfdq6P4=; b=HMtjhQIb6T9y40w9pLCzoX3gO7a1ODB5Geg/LTKBVKnMcozHcg84ITV59G5hUWYxVw 0EPCr1gZdPnKOHEcSeCh5NXCqxkQmajKdhsRLG3GYW+X8QHrbi5DRB+5bz1GRzVKScFH ccElbxNtVcCIFg6Fy2lph0BdNJkQpAg/TR46yL6AAGojTmqw6yfqe/5rdlYZd8nDh1i9 0MkZe1CQORuo3QfjMvfrWSN4G73OFFxCmI+Tnjt63Wr/EIyG01AP/5q5cszWV5udhiBT jhYXB5yN89uRdygI0+ZE7biPsXC+XYeptXbLxT6ELcJNWpKowmWJlfC/MlmN0sOI2bdI 1JHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=KujdazEonh8hoTE6UrQ09RC6Ad/DxZja9GU4lfdq6P4=; b=P3gnIneHcMs0KQIPwV7vEt5Gd5K1nvaSPqV/3/iYXjoCk33A+VCD2RqV0FUe4lDTJn isnULT59Llmomt8WMmTS6iV7l1ruSph6nOkjhtee8AkiRmvAEmOLbRkAwVgl8YN4KrRs XCVNJUwpnUyVBbudeHuSf2CshA7jgbXbLUqgE4it0Vf6TW+R7vKOfpxSCy/Dy35r/xzi gx/AZiWzrRrm3siboRp508EIvt4g1GTRyK+RypobZmmHdwuKs/E7QTQfBwdgk69/qm2f XD2Hwn8/ziFJF6CVIgU+7403GspJvn+fN6sPddkGXWc67FmC5L1S+W5V2lUuKn0jw1XG Bl4g== X-Gm-Message-State: AOUpUlEwKvNL5hsFLqmC4YMfNAz/mxFLRTUMtvNGgX7EqEaWKxgparD2 iw+L8WOsdl36o7sfVTTVCNU= X-Google-Smtp-Source: AAOMgpeEidQLczHF9iPhejkbYEOU3RcmCUeMydImxAQpMLhaf64o/CsvjM67i76bzBln7PLgD8aoKg== X-Received: by 2002:a2e:63c5:: with SMTP id s66-v6mr8169660lje.23.1532006559246; Thu, 19 Jul 2018 06:22:39 -0700 (PDT) Received: from localhost.localdomain ([109.252.91.91]) by smtp.gmail.com with ESMTPSA id o4-v6sm1109592ljc.67.2018.07.19.06.22.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 19 Jul 2018 06:22:38 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Peter De Schrijver , Jonathan Hunter , Prashant Gaikwad , Michael Turquette , Stephen Boyd Cc: Rob Herring , linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 8/8] memory: tegra: Introduce Tegra20 EMC driver Date: Thu, 19 Jul 2018 16:21:32 +0300 Message-Id: <20180719132132.16153-9-digetx@gmail.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180719132132.16153-1-digetx@gmail.com> References: <20180719132132.16153-1-digetx@gmail.com> Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Introduce driver for the External Memory Controller (EMC) found on Tegra20 chips, which controls the external DRAM on the board. The purpose of this driver is to program memory timing for external memory on the EMC clock rate change. Signed-off-by: Dmitry Osipenko Acked-by: Peter De Schrijver --- drivers/memory/tegra/Kconfig | 10 + drivers/memory/tegra/Makefile | 1 + drivers/memory/tegra/tegra20-emc.c | 575 +++++++++++++++++++++++++++++ 3 files changed, 586 insertions(+) create mode 100644 drivers/memory/tegra/tegra20-emc.c diff --git a/drivers/memory/tegra/Kconfig b/drivers/memory/tegra/Kconfig index 6d74e499e18d..34e0b70f5c5f 100644 --- a/drivers/memory/tegra/Kconfig +++ b/drivers/memory/tegra/Kconfig @@ -6,6 +6,16 @@ config TEGRA_MC This driver supports the Memory Controller (MC) hardware found on NVIDIA Tegra SoCs. +config TEGRA20_EMC + bool "NVIDIA Tegra20 External Memory Controller driver" + default y + depends on ARCH_TEGRA_2x_SOC + help + This driver is for the External Memory Controller (EMC) found on + Tegra20 chips. The EMC controls the external DRAM on the board. + This driver is required to change memory timings / clock rate for + external memory. + config TEGRA124_EMC bool "NVIDIA Tegra124 External Memory Controller driver" default y diff --git a/drivers/memory/tegra/Makefile b/drivers/memory/tegra/Makefile index 94ab16ba075b..3971a6b7c487 100644 --- a/drivers/memory/tegra/Makefile +++ b/drivers/memory/tegra/Makefile @@ -10,5 +10,6 @@ tegra-mc-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210.o obj-$(CONFIG_TEGRA_MC) += tegra-mc.o +obj-$(CONFIG_TEGRA20_EMC) += tegra20-emc.o obj-$(CONFIG_TEGRA124_EMC) += tegra124-emc.o obj-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186.o diff --git a/drivers/memory/tegra/tegra20-emc.c b/drivers/memory/tegra/tegra20-emc.c new file mode 100644 index 000000000000..0fa839a577c8 --- /dev/null +++ b/drivers/memory/tegra/tegra20-emc.c @@ -0,0 +1,575 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Tegra20 External Memory Controller driver + * + * Author: Dmitry Osipenko + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define EMC_INTSTATUS 0x000 +#define EMC_INTMASK 0x004 +#define EMC_TIMING_CONTROL 0x028 +#define EMC_RC 0x02c +#define EMC_RFC 0x030 +#define EMC_RAS 0x034 +#define EMC_RP 0x038 +#define EMC_R2W 0x03c +#define EMC_W2R 0x040 +#define EMC_R2P 0x044 +#define EMC_W2P 0x048 +#define EMC_RD_RCD 0x04c +#define EMC_WR_RCD 0x050 +#define EMC_RRD 0x054 +#define EMC_REXT 0x058 +#define EMC_WDV 0x05c +#define EMC_QUSE 0x060 +#define EMC_QRST 0x064 +#define EMC_QSAFE 0x068 +#define EMC_RDV 0x06c +#define EMC_REFRESH 0x070 +#define EMC_BURST_REFRESH_NUM 0x074 +#define EMC_PDEX2WR 0x078 +#define EMC_PDEX2RD 0x07c +#define EMC_PCHG2PDEN 0x080 +#define EMC_ACT2PDEN 0x084 +#define EMC_AR2PDEN 0x088 +#define EMC_RW2PDEN 0x08c +#define EMC_TXSR 0x090 +#define EMC_TCKE 0x094 +#define EMC_TFAW 0x098 +#define EMC_TRPAB 0x09c +#define EMC_TCLKSTABLE 0x0a0 +#define EMC_TCLKSTOP 0x0a4 +#define EMC_TREFBW 0x0a8 +#define EMC_QUSE_EXTRA 0x0ac +#define EMC_ODT_WRITE 0x0b0 +#define EMC_ODT_READ 0x0b4 +#define EMC_FBIO_CFG5 0x104 +#define EMC_FBIO_CFG6 0x114 +#define EMC_AUTO_CAL_INTERVAL 0x2a8 +#define EMC_CFG_2 0x2b8 +#define EMC_CFG_DIG_DLL 0x2bc +#define EMC_DLL_XFORM_DQS 0x2c0 +#define EMC_DLL_XFORM_QUSE 0x2c4 +#define EMC_ZCAL_REF_CNT 0x2e0 +#define EMC_ZCAL_WAIT_CNT 0x2e4 +#define EMC_CFG_CLKTRIM_0 0x2d0 +#define EMC_CFG_CLKTRIM_1 0x2d4 +#define EMC_CFG_CLKTRIM_2 0x2d8 + +#define EMC_CLKCHANGE_REQ_ENABLE BIT(0) +#define EMC_CLKCHANGE_PD_ENABLE BIT(1) +#define EMC_CLKCHANGE_SR_ENABLE BIT(2) + +#define EMC_TIMING_UPDATE BIT(0) + +#define EMC_CLKCHANGE_COMPLETE_INT BIT(4) + +static const u16 emc_timing_registers[] = { + EMC_RC, + EMC_RFC, + EMC_RAS, + EMC_RP, + EMC_R2W, + EMC_W2R, + EMC_R2P, + EMC_W2P, + EMC_RD_RCD, + EMC_WR_RCD, + EMC_RRD, + EMC_REXT, + EMC_WDV, + EMC_QUSE, + EMC_QRST, + EMC_QSAFE, + EMC_RDV, + EMC_REFRESH, + EMC_BURST_REFRESH_NUM, + EMC_PDEX2WR, + EMC_PDEX2RD, + EMC_PCHG2PDEN, + EMC_ACT2PDEN, + EMC_AR2PDEN, + EMC_RW2PDEN, + EMC_TXSR, + EMC_TCKE, + EMC_TFAW, + EMC_TRPAB, + EMC_TCLKSTABLE, + EMC_TCLKSTOP, + EMC_TREFBW, + EMC_QUSE_EXTRA, + EMC_FBIO_CFG6, + EMC_ODT_WRITE, + EMC_ODT_READ, + EMC_FBIO_CFG5, + EMC_CFG_DIG_DLL, + EMC_DLL_XFORM_DQS, + EMC_DLL_XFORM_QUSE, + EMC_ZCAL_REF_CNT, + EMC_ZCAL_WAIT_CNT, + EMC_AUTO_CAL_INTERVAL, + EMC_CFG_CLKTRIM_0, + EMC_CFG_CLKTRIM_1, + EMC_CFG_CLKTRIM_2, +}; + +struct emc_timing { + unsigned long rate; + u32 data[ARRAY_SIZE(emc_timing_registers)]; +}; + +struct tegra_emc { + struct device *dev; + struct completion clk_handshake_complete; + struct notifier_block clk_nb; + struct clk *backup_clk; + struct clk *emc_mux; + struct clk *pll_m; + struct clk *clk; + void __iomem *regs; + + struct emc_timing *timings; + unsigned int num_timings; +}; + +static irqreturn_t tegra_emc_isr(int irq, void *data) +{ + struct tegra_emc *emc = data; + u32 intmask = EMC_CLKCHANGE_COMPLETE_INT; + u32 status; + + status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask; + if (!status) + return IRQ_NONE; + + /* clear interrupts */ + writel_relaxed(status, emc->regs + EMC_INTSTATUS); + + /* notify about EMC-CAR handshake completion */ + complete(&emc->clk_handshake_complete); + + return IRQ_HANDLED; +} + +static struct emc_timing *tegra_emc_find_timing(struct tegra_emc *emc, + unsigned long rate) +{ + struct emc_timing *timing = NULL; + unsigned int i; + + for (i = 0; i < emc->num_timings; i++) { + if (emc->timings[i].rate >= rate) { + timing = &emc->timings[i]; + break; + } + } + + if (!timing) { + dev_err(emc->dev, "no timing for rate %lu\n", rate); + return NULL; + } + + return timing; +} + +static int emc_prepare_timing_change(struct tegra_emc *emc, unsigned long rate) +{ + struct emc_timing *timing = tegra_emc_find_timing(emc, rate); + unsigned int i; + + if (!timing) + return -EINVAL; + + dev_dbg(emc->dev, "%s: using timing rate %lu for requested rate %lu\n", + __func__, timing->rate, rate); + + /* program shadow registers */ + for (i = 0; i < ARRAY_SIZE(timing->data); i++) + writel_relaxed(timing->data[i], + emc->regs + emc_timing_registers[i]); + + /* wait until programming has settled */ + readl_relaxed(emc->regs + emc_timing_registers[0]); + + reinit_completion(&emc->clk_handshake_complete); + + return 0; +} + +static int emc_complete_timing_change(struct tegra_emc *emc, bool flush) +{ + long timeout; + + dev_dbg(emc->dev, "%s: flush %d\n", __func__, flush); + + if (flush) { + /* manually initiate memory timing update */ + writel_relaxed(EMC_TIMING_UPDATE, + emc->regs + EMC_TIMING_CONTROL); + return 0; + } + + timeout = wait_for_completion_timeout(&emc->clk_handshake_complete, + usecs_to_jiffies(100)); + if (timeout == 0) { + dev_err(emc->dev, "EMC-CAR handshake failed\n"); + return -EIO; + } else if (timeout < 0) { + dev_err(emc->dev, "failed to wait for EMC-CAR handshake: %ld\n", + timeout); + return timeout; + } + + return 0; +} + +static int tegra_emc_clk_change_notify(struct notifier_block *nb, + unsigned long msg, void *data) +{ + struct tegra_emc *emc = container_of(nb, struct tegra_emc, clk_nb); + struct clk_notifier_data *cnd = data; + int err; + + switch (msg) { + case PRE_RATE_CHANGE: + err = emc_prepare_timing_change(emc, cnd->new_rate); + break; + + case ABORT_RATE_CHANGE: + err = emc_prepare_timing_change(emc, cnd->old_rate); + if (err) + break; + + err = emc_complete_timing_change(emc, true); + break; + + case POST_RATE_CHANGE: + err = emc_complete_timing_change(emc, false); + break; + + default: + return NOTIFY_DONE; + } + + return notifier_from_errno(err); +} + +static int load_one_timing_from_dt(struct tegra_emc *emc, + struct emc_timing *timing, + struct device_node *node) +{ + u32 rate; + int err; + + if (!of_device_is_compatible(node, "nvidia,tegra20-emc-table")) { + dev_err(emc->dev, "incompatible DT node: %pOF\n", node); + return -EINVAL; + } + + err = of_property_read_u32(node, "clock-frequency", &rate); + if (err) { + dev_err(emc->dev, "timing %pOF: failed to read rate: %d\n", + node, err); + return err; + } + + err = of_property_read_u32_array(node, "nvidia,emc-registers", + timing->data, + ARRAY_SIZE(emc_timing_registers)); + if (err) { + dev_err(emc->dev, + "timing %pOF: failed to read emc timing data: %d\n", + node, err); + return err; + } + + /* + * The EMC clock rate is twice the bus rate, and the bus rate is + * measured in kHz. + */ + timing->rate = rate * 2 * 1000; + + dev_dbg(emc->dev, "%s: %pOF: EMC rate %lu\n", + __func__, node, timing->rate); + + return 0; +} + +static int cmp_timings(const void *_a, const void *_b) +{ + const struct emc_timing *a = _a; + const struct emc_timing *b = _b; + + if (a->rate < b->rate) + return -1; + + if (a->rate > b->rate) + return 1; + + return 0; +} + +static int tegra_emc_load_timings_from_dt(struct tegra_emc *emc, + struct device_node *node) +{ + struct device_node *child; + struct emc_timing *timing; + int child_count; + int err; + + child_count = of_get_child_count(node); + if (!child_count) { + dev_err(emc->dev, "no memory timings in DT node: %pOF\n", node); + return -EINVAL; + } + + emc->timings = devm_kcalloc(emc->dev, child_count, sizeof(*timing), + GFP_KERNEL); + if (!emc->timings) + return -ENOMEM; + + emc->num_timings = child_count; + timing = emc->timings; + + for_each_child_of_node(node, child) { + err = load_one_timing_from_dt(emc, timing++, child); + if (err) { + of_node_put(child); + return err; + } + } + + sort(emc->timings, emc->num_timings, sizeof(*timing), cmp_timings, + NULL); + + return 0; +} + +static struct device_node * +tegra_emc_find_node_by_ram_code(struct device *dev) +{ + struct device_node *np; + u32 value, ram_code; + int err; + + if (!of_property_read_bool(dev->of_node, "nvidia,use-ram-code")) + return of_node_get(dev->of_node); + + ram_code = tegra_read_ram_code(); + + for (np = of_find_node_by_name(dev->of_node, "emc-tables"); np; + np = of_find_node_by_name(np, "emc-tables")) { + err = of_property_read_u32(np, "nvidia,ram-code", &value); + if (err || value != ram_code) { + of_node_put(np); + continue; + } + + return np; + } + + dev_err(dev, "no memory timings for RAM code %u found in device tree\n", + ram_code); + + return NULL; +} + +static int emc_setup_hw(struct tegra_emc *emc) +{ + u32 emc_cfg; + + emc_cfg = readl_relaxed(emc->regs + EMC_CFG_2); + + /* + * Depending on a memory type, DRAM should enter either self-refresh + * or power-down state on EMC clock change. + */ + if (!(emc_cfg & EMC_CLKCHANGE_PD_ENABLE) && + !(emc_cfg & EMC_CLKCHANGE_SR_ENABLE)) + { + dev_err(emc->dev, + "bootloader didn't specify DRAM auto-suspend mode\n"); + return -EINVAL; + } + + /* allow EMC and CAR to handshake on PLL divider/source changes */ + emc_cfg |= EMC_CLKCHANGE_REQ_ENABLE; + writel_relaxed(emc_cfg, emc->regs + EMC_CFG_2); + + /* initialize interrupt */ + writel_relaxed(EMC_CLKCHANGE_COMPLETE_INT, emc->regs + EMC_INTMASK); + writel_relaxed(EMC_CLKCHANGE_COMPLETE_INT, emc->regs + EMC_INTSTATUS); + + return 0; +} + +static int emc_init(struct tegra_emc *emc, unsigned long rate) +{ + int err, ret; + + err = clk_set_parent(emc->emc_mux, emc->backup_clk); + if (err) { + dev_err(emc->dev, + "failed to reparent to backup source: %d\n", err); + return err; + } + + ret = clk_set_rate(emc->pll_m, rate); + if (ret) + dev_err(emc->dev, + "failed to change pll_m rate: %d\n", ret); + + err = clk_set_parent(emc->emc_mux, emc->pll_m); + if (err) { + dev_err(emc->dev, + "failed to reparent to pll_m: %d\n", err); + return err; + } + + return ret; +} + +static int tegra_emc_probe(struct platform_device *pdev) +{ + struct device_node *np; + struct tegra_emc *emc; + struct resource *res; + int irq, err; + + /* driver has nothing to do in a case of memory timing absence */ + if (of_get_child_count(pdev->dev.of_node) == 0) { + dev_info(&pdev->dev, + "EMC device tree node doesn't have memory timings\n"); + return 0; + } + + irq = platform_get_irq(pdev, 0); + if (irq < 0) { + dev_err(&pdev->dev, "interrupt not specified\n"); + dev_err(&pdev->dev, "please update your device tree\n"); + return irq; + } + + np = tegra_emc_find_node_by_ram_code(&pdev->dev); + if (!np) + return -EINVAL; + + emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL); + if (!emc) { + of_node_put(np); + return -ENOMEM; + } + + init_completion(&emc->clk_handshake_complete); + emc->clk_nb.notifier_call = tegra_emc_clk_change_notify; + emc->dev = &pdev->dev; + + err = tegra_emc_load_timings_from_dt(emc, np); + of_node_put(np); + if (err) + return err; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + emc->regs = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(emc->regs)) + return PTR_ERR(emc->regs); + + err = emc_setup_hw(emc); + if (err) + return err; + + err = devm_request_irq(&pdev->dev, irq, tegra_emc_isr, 0, + dev_name(&pdev->dev), emc); + if (err) { + dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", irq, err); + return err; + } + + emc->clk = devm_clk_get(&pdev->dev, "emc"); + if (IS_ERR(emc->clk)) { + err = PTR_ERR(emc->clk); + dev_err(&pdev->dev, "failed to get emc clock: %d\n", err); + return err; + } + + emc->pll_m = clk_get_sys(NULL, "pll_m"); + if (IS_ERR(emc->pll_m)) { + err = PTR_ERR(emc->pll_m); + dev_err(&pdev->dev, "failed to get pll_m clock: %d\n", err); + return err; + } + + emc->backup_clk = clk_get_sys(NULL, "pll_p"); + if (IS_ERR(emc->backup_clk)) { + err = PTR_ERR(emc->backup_clk); + dev_err(&pdev->dev, "failed to get pll_p clock: %d\n", err); + goto put_pll_m; + } + + emc->emc_mux = clk_get_parent(emc->clk); + if (IS_ERR(emc->emc_mux)) { + err = PTR_ERR(emc->emc_mux); + dev_err(&pdev->dev, "failed to get emc_mux clock: %d\n", err); + goto put_backup; + } + + err = clk_notifier_register(emc->clk, &emc->clk_nb); + if (err) { + dev_err(&pdev->dev, "failed to register clk notifier: %d\n", + err); + goto put_backup; + } + + /* set DRAM clock rate to maximum */ + err = emc_init(emc, emc->timings[emc->num_timings - 1].rate); + if (err) { + dev_err(&pdev->dev, "failed to initialize EMC clock rate: %d\n", + err); + goto unreg_notifier; + } + + return 0; + +unreg_notifier: + clk_notifier_unregister(emc->clk, &emc->clk_nb); +put_backup: + clk_put(emc->backup_clk); +put_pll_m: + clk_put(emc->pll_m); + + return err; +} + +static const struct of_device_id tegra_emc_of_match[] = { + { .compatible = "nvidia,tegra20-emc", }, + {}, +}; + +static struct platform_driver tegra_emc_driver = { + .probe = tegra_emc_probe, + .driver = { + .name = "tegra20-emc", + .of_match_table = tegra_emc_of_match, + .suppress_bind_attrs = true, + }, +}; + +static int __init tegra_emc_init(void) +{ + return platform_driver_register(&tegra_emc_driver); +} +subsys_initcall(tegra_emc_init);